1c8b08822SBiju Das // SPDX-License-Identifier: GPL-2.0 2c8b08822SBiju Das /* 3c8b08822SBiju Das * RZ/G2UL CPG driver 4c8b08822SBiju Das * 5c8b08822SBiju Das * Copyright (C) 2022 Renesas Electronics Corp. 6c8b08822SBiju Das */ 7c8b08822SBiju Das 8c8b08822SBiju Das #include <linux/clk-provider.h> 9c8b08822SBiju Das #include <linux/device.h> 10c8b08822SBiju Das #include <linux/init.h> 11c8b08822SBiju Das #include <linux/kernel.h> 12c8b08822SBiju Das 13c8b08822SBiju Das #include <dt-bindings/clock/r9a07g043-cpg.h> 14c8b08822SBiju Das 15c8b08822SBiju Das #include "rzg2l-cpg.h" 16c8b08822SBiju Das 17c8b08822SBiju Das enum clk_ids { 18c8b08822SBiju Das /* Core Clock Outputs exported to DT */ 19c8b08822SBiju Das LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2, 20c8b08822SBiju Das 21c8b08822SBiju Das /* External Input Clocks */ 22c8b08822SBiju Das CLK_EXTAL, 23c8b08822SBiju Das 24c8b08822SBiju Das /* Internal Core Clocks */ 25c8b08822SBiju Das CLK_OSC_DIV1000, 26c8b08822SBiju Das CLK_PLL1, 27c8b08822SBiju Das CLK_PLL2, 28c8b08822SBiju Das CLK_PLL2_DIV2, 29c8b08822SBiju Das CLK_PLL2_DIV2_8, 30b6768530SBiju Das CLK_PLL2_DIV2_10, 31c8b08822SBiju Das CLK_PLL3, 324e683604SBiju Das CLK_PLL3_400, 334e683604SBiju Das CLK_PLL3_533, 34c8b08822SBiju Das CLK_PLL3_DIV2, 35c8b08822SBiju Das CLK_PLL3_DIV2_4, 36c8b08822SBiju Das CLK_PLL3_DIV2_4_2, 374e683604SBiju Das CLK_SEL_PLL3_3, 384e683604SBiju Das CLK_DIV_PLL3_C, 39*95d48d27SLad Prabhakar #ifdef CONFIG_ARM64 40c8b08822SBiju Das CLK_PLL5, 41f201eb84SBiju Das CLK_PLL5_500, 42f201eb84SBiju Das CLK_PLL5_250, 43*95d48d27SLad Prabhakar #endif 44c8b08822SBiju Das CLK_PLL6, 45f201eb84SBiju Das CLK_PLL6_250, 46c8b08822SBiju Das CLK_P1_DIV2, 4759086e41SBiju Das CLK_PLL2_800, 4859086e41SBiju Das CLK_PLL2_SDHI_533, 4959086e41SBiju Das CLK_PLL2_SDHI_400, 5059086e41SBiju Das CLK_PLL2_SDHI_266, 5159086e41SBiju Das CLK_SD0_DIV4, 5259086e41SBiju Das CLK_SD1_DIV4, 53c8b08822SBiju Das 54c8b08822SBiju Das /* Module Clocks */ 55c8b08822SBiju Das MOD_CLK_BASE, 56c8b08822SBiju Das }; 57c8b08822SBiju Das 58c8b08822SBiju Das /* Divider tables */ 59c8b08822SBiju Das static const struct clk_div_table dtable_1_8[] = { 60c8b08822SBiju Das {0, 1}, 61c8b08822SBiju Das {1, 2}, 62c8b08822SBiju Das {2, 4}, 63c8b08822SBiju Das {3, 8}, 64c8b08822SBiju Das {0, 0}, 65c8b08822SBiju Das }; 66c8b08822SBiju Das 67c8b08822SBiju Das static const struct clk_div_table dtable_1_32[] = { 68c8b08822SBiju Das {0, 1}, 69c8b08822SBiju Das {1, 2}, 70c8b08822SBiju Das {2, 4}, 71c8b08822SBiju Das {3, 8}, 72c8b08822SBiju Das {4, 32}, 73c8b08822SBiju Das {0, 0}, 74c8b08822SBiju Das }; 75c8b08822SBiju Das 76f201eb84SBiju Das /* Mux clock tables */ 774e683604SBiju Das static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; 78f201eb84SBiju Das static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; 7959086e41SBiju Das static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; 80f201eb84SBiju Das 81c8b08822SBiju Das static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 82c8b08822SBiju Das /* External Clock Inputs */ 83c8b08822SBiju Das DEF_INPUT("extal", CLK_EXTAL), 84c8b08822SBiju Das 85c8b08822SBiju Das /* Internal Core Clocks */ 86c8b08822SBiju Das DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1), 87c8b08822SBiju Das DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), 88c8b08822SBiju Das DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), 89c8b08822SBiju Das DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), 90c8b08822SBiju Das DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), 9159086e41SBiju Das DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), 9259086e41SBiju Das DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), 9359086e41SBiju Das DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), 9459086e41SBiju Das DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), 95c8b08822SBiju Das DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), 96b6768530SBiju Das DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), 97c8b08822SBiju Das DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), 98c8b08822SBiju Das DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), 99c8b08822SBiju Das DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), 100c8b08822SBiju Das DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), 1014e683604SBiju Das DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), 1024e683604SBiju Das DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), 1038282fe00SPhil Edworthy DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), 10475b0ad42SPhil Edworthy DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), 105*95d48d27SLad Prabhakar #ifdef CONFIG_ARM64 106c8b08822SBiju Das DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), 107f201eb84SBiju Das DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6), 108f201eb84SBiju Das DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2), 109*95d48d27SLad Prabhakar #endif 110c8b08822SBiju Das DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), 111f201eb84SBiju Das DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), 112c8b08822SBiju Das 113c8b08822SBiju Das /* Core output clk */ 11475b0ad42SPhil Edworthy DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8), 11575b0ad42SPhil Edworthy DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32), 1161cbda377SBiju Das DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2), 117b6768530SBiju Das DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), 11875b0ad42SPhil Edworthy DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32), 119c8b08822SBiju Das DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), 12075b0ad42SPhil Edworthy DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32), 121f201eb84SBiju Das DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), 122f201eb84SBiju Das DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), 12375b0ad42SPhil Edworthy DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2), 1244e683604SBiju Das DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), 1254e683604SBiju Das DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), 126ceb3bfabSPhil Edworthy DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi), 127ceb3bfabSPhil Edworthy DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, sel_shdi), 12859086e41SBiju Das DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), 12959086e41SBiju Das DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4), 130c8b08822SBiju Das }; 131c8b08822SBiju Das 132c8b08822SBiju Das static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 133*95d48d27SLad Prabhakar #ifdef CONFIG_ARM64 134c8b08822SBiju Das DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, 135c8b08822SBiju Das 0x514, 0), 136c8b08822SBiju Das DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2, 137c8b08822SBiju Das 0x518, 0), 138c8b08822SBiju Das DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1, 139c8b08822SBiju Das 0x518, 1), 140*95d48d27SLad Prabhakar #endif 141*95d48d27SLad Prabhakar #ifdef CONFIG_RISCV 142*95d48d27SLad Prabhakar DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2, 143*95d48d27SLad Prabhakar 0x518, 0), 144*95d48d27SLad Prabhakar DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1, 145*95d48d27SLad Prabhakar 0x518, 1), 146*95d48d27SLad Prabhakar #endif 147c8b08822SBiju Das DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1, 148c8b08822SBiju Das 0x52c, 0), 149c8b08822SBiju Das DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, 150c8b08822SBiju Das 0x52c, 1), 1516c05648bSBiju Das DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0, 1526c05648bSBiju Das 0x534, 0), 1536c05648bSBiju Das DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0, 1546c05648bSBiju Das 0x534, 1), 1556c05648bSBiju Das DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, 1566c05648bSBiju Das 0x534, 2), 1575d33481fSBiju Das DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0, 1585d33481fSBiju Das 0x548, 0), 1595d33481fSBiju Das DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, 1605d33481fSBiju Das 0x548, 1), 1615d33481fSBiju Das DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0, 1625d33481fSBiju Das 0x548, 4), 1635d33481fSBiju Das DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK, 1645d33481fSBiju Das 0x548, 5), 1654e683604SBiju Das DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1, 1664e683604SBiju Das 0x550, 0), 1674e683604SBiju Das DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0, 1684e683604SBiju Das 0x550, 1), 16959086e41SBiju Das DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 17059086e41SBiju Das 0x554, 0), 17159086e41SBiju Das DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, 17259086e41SBiju Das 0x554, 1), 17359086e41SBiju Das DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0, 17459086e41SBiju Das 0x554, 2), 17559086e41SBiju Das DEF_MOD("sdhi0_aclk", R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1, 17659086e41SBiju Das 0x554, 3), 17759086e41SBiju Das DEF_MOD("sdhi1_imclk", R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4, 17859086e41SBiju Das 0x554, 4), 17959086e41SBiju Das DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4, 18059086e41SBiju Das 0x554, 5), 18159086e41SBiju Das DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1, 18259086e41SBiju Das 0x554, 6), 18359086e41SBiju Das DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1, 18459086e41SBiju Das 0x554, 7), 185be5b5fcbSBiju Das DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0, 186be5b5fcbSBiju Das 0x570, 0), 187be5b5fcbSBiju Das DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0, 188be5b5fcbSBiju Das 0x570, 1), 189be5b5fcbSBiju Das DEF_MOD("ssi1_pclk", R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0, 190be5b5fcbSBiju Das 0x570, 2), 191be5b5fcbSBiju Das DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0, 192be5b5fcbSBiju Das 0x570, 3), 193be5b5fcbSBiju Das DEF_MOD("ssi2_pclk", R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0, 194be5b5fcbSBiju Das 0x570, 4), 195be5b5fcbSBiju Das DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0, 196be5b5fcbSBiju Das 0x570, 5), 197be5b5fcbSBiju Das DEF_MOD("ssi3_pclk", R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0, 198be5b5fcbSBiju Das 0x570, 6), 199be5b5fcbSBiju Das DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0, 200be5b5fcbSBiju Das 0x570, 7), 201666b5a01SBiju Das DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1, 202666b5a01SBiju Das 0x578, 0), 203666b5a01SBiju Das DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1, 204666b5a01SBiju Das 0x578, 1), 205666b5a01SBiju Das DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1, 206666b5a01SBiju Das 0x578, 2), 207666b5a01SBiju Das DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1, 208666b5a01SBiju Das 0x578, 3), 209e11f804aSBiju Das DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, 210e11f804aSBiju Das 0x57c, 0), 211e11f804aSBiju Das DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, 212e11f804aSBiju Das 0x57c, 0), 213e11f804aSBiju Das DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0, 214e11f804aSBiju Das 0x57c, 1), 215e11f804aSBiju Das DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT, 216e11f804aSBiju Das 0x57c, 1), 217a9391e01SBiju Das DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0, 218a9391e01SBiju Das 0x580, 0), 219a9391e01SBiju Das DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0, 220a9391e01SBiju Das 0x580, 1), 221a9391e01SBiju Das DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0, 222a9391e01SBiju Das 0x580, 2), 223a9391e01SBiju Das DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0, 224a9391e01SBiju Das 0x580, 3), 225c8b08822SBiju Das DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0, 226c8b08822SBiju Das 0x584, 0), 227c8b08822SBiju Das DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0, 228c8b08822SBiju Das 0x584, 1), 229c8b08822SBiju Das DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0, 230c8b08822SBiju Das 0x584, 2), 231c8b08822SBiju Das DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0, 232c8b08822SBiju Das 0x584, 3), 233c8b08822SBiju Das DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0, 234c8b08822SBiju Das 0x584, 4), 235c8b08822SBiju Das DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0, 236c8b08822SBiju Das 0x588, 0), 237c8b08822SBiju Das DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, 238c8b08822SBiju Das 0x588, 1), 23914d8857dSBiju Das DEF_MOD("rspi0", R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0, 24014d8857dSBiju Das 0x590, 0), 24114d8857dSBiju Das DEF_MOD("rspi1", R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0, 24214d8857dSBiju Das 0x590, 1), 24314d8857dSBiju Das DEF_MOD("rspi2", R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0, 24414d8857dSBiju Das 0x590, 2), 2451cbda377SBiju Das DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0, 2461cbda377SBiju Das 0x594, 0), 2476c185664SBiju Das DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, 2486c185664SBiju Das 0x598, 0), 24984c9829dSBiju Das DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU, 25084c9829dSBiju Das 0x5a8, 0), 25184c9829dSBiju Das DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0, 25284c9829dSBiju Das 0x5a8, 1), 253b6768530SBiju Das DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU, 254b6768530SBiju Das 0x5ac, 0), 255c8b08822SBiju Das }; 256c8b08822SBiju Das 257c8b08822SBiju Das static struct rzg2l_reset r9a07g043_resets[] = { 258*95d48d27SLad Prabhakar #ifdef CONFIG_ARM64 259c8b08822SBiju Das DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0), 260c8b08822SBiju Das DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1), 261c8b08822SBiju Das DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), 262*95d48d27SLad Prabhakar #endif 263*95d48d27SLad Prabhakar #ifdef CONFIG_RISCV 264*95d48d27SLad Prabhakar DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0), 265*95d48d27SLad Prabhakar #endif 266c8b08822SBiju Das DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), 267c8b08822SBiju Das DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), 2686c05648bSBiju Das DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), 2696c05648bSBiju Das DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), 2706c05648bSBiju Das DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), 2715d33481fSBiju Das DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), 2725d33481fSBiju Das DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2), 2734e683604SBiju Das DEF_RST(R9A07G043_SPI_RST, 0x850, 0), 27459086e41SBiju Das DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), 27559086e41SBiju Das DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), 276be5b5fcbSBiju Das DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0), 277be5b5fcbSBiju Das DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1), 278be5b5fcbSBiju Das DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2), 279be5b5fcbSBiju Das DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3), 280666b5a01SBiju Das DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0), 281666b5a01SBiju Das DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1), 282666b5a01SBiju Das DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2), 283666b5a01SBiju Das DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3), 284e11f804aSBiju Das DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), 285e11f804aSBiju Das DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), 286a9391e01SBiju Das DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0), 287a9391e01SBiju Das DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1), 288a9391e01SBiju Das DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2), 289a9391e01SBiju Das DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3), 290c8b08822SBiju Das DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0), 291c8b08822SBiju Das DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1), 292c8b08822SBiju Das DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2), 293c8b08822SBiju Das DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3), 294c8b08822SBiju Das DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), 295c8b08822SBiju Das DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), 296c8b08822SBiju Das DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), 29714d8857dSBiju Das DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0), 29814d8857dSBiju Das DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1), 29914d8857dSBiju Das DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2), 3001cbda377SBiju Das DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0), 3011cbda377SBiju Das DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1), 3026c185664SBiju Das DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), 3036c185664SBiju Das DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), 3046c185664SBiju Das DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), 30584c9829dSBiju Das DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0), 30684c9829dSBiju Das DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1), 307b6768530SBiju Das DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0), 308c8b08822SBiju Das }; 309c8b08822SBiju Das 310c8b08822SBiju Das static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { 311*95d48d27SLad Prabhakar #ifdef CONFIG_ARM64 312c8b08822SBiju Das MOD_CLK_BASE + R9A07G043_GIC600_GICCLK, 313c8b08822SBiju Das MOD_CLK_BASE + R9A07G043_IA55_CLK, 314*95d48d27SLad Prabhakar #endif 315*95d48d27SLad Prabhakar #ifdef CONFIG_RISCV 316*95d48d27SLad Prabhakar MOD_CLK_BASE + R9A07G043_IAX45_CLK, 317*95d48d27SLad Prabhakar #endif 318c8b08822SBiju Das MOD_CLK_BASE + R9A07G043_DMAC_ACLK, 319c8b08822SBiju Das }; 320c8b08822SBiju Das 321c8b08822SBiju Das const struct rzg2l_cpg_info r9a07g043_cpg_info = { 322c8b08822SBiju Das /* Core Clocks */ 323c8b08822SBiju Das .core_clks = r9a07g043_core_clks, 324c8b08822SBiju Das .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks), 325c8b08822SBiju Das .last_dt_core_clk = LAST_DT_CORE_CLK, 326c8b08822SBiju Das .num_total_core_clks = MOD_CLK_BASE, 327c8b08822SBiju Das 328c8b08822SBiju Das /* Critical Module Clocks */ 329c8b08822SBiju Das .crit_mod_clks = r9a07g043_crit_mod_clks, 330c8b08822SBiju Das .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks), 331c8b08822SBiju Das 332c8b08822SBiju Das /* Module Clocks */ 333c8b08822SBiju Das .mod_clks = r9a07g043_mod_clks, 334c8b08822SBiju Das .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks), 335*95d48d27SLad Prabhakar #ifdef CONFIG_ARM64 336c8b08822SBiju Das .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1, 337*95d48d27SLad Prabhakar #endif 338*95d48d27SLad Prabhakar #ifdef CONFIG_RISCV 339*95d48d27SLad Prabhakar .num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1, 340*95d48d27SLad Prabhakar #endif 341c8b08822SBiju Das 342c8b08822SBiju Das /* Resets */ 343c8b08822SBiju Das .resets = r9a07g043_resets, 344*95d48d27SLad Prabhakar #ifdef CONFIG_ARM64 345c8b08822SBiju Das .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ 346*95d48d27SLad Prabhakar #endif 347*95d48d27SLad Prabhakar #ifdef CONFIG_RISCV 348*95d48d27SLad Prabhakar .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */ 349*95d48d27SLad Prabhakar #endif 35063804400SPhil Edworthy 35163804400SPhil Edworthy .has_clk_mon_regs = true, 352c8b08822SBiju Das }; 353