1c8b08822SBiju Das // SPDX-License-Identifier: GPL-2.0 2c8b08822SBiju Das /* 3c8b08822SBiju Das * RZ/G2UL CPG driver 4c8b08822SBiju Das * 5c8b08822SBiju Das * Copyright (C) 2022 Renesas Electronics Corp. 6c8b08822SBiju Das */ 7c8b08822SBiju Das 8c8b08822SBiju Das #include <linux/clk-provider.h> 9c8b08822SBiju Das #include <linux/device.h> 10c8b08822SBiju Das #include <linux/init.h> 11c8b08822SBiju Das #include <linux/kernel.h> 12c8b08822SBiju Das 13c8b08822SBiju Das #include <dt-bindings/clock/r9a07g043-cpg.h> 14c8b08822SBiju Das 15c8b08822SBiju Das #include "rzg2l-cpg.h" 16c8b08822SBiju Das 17c8b08822SBiju Das enum clk_ids { 18c8b08822SBiju Das /* Core Clock Outputs exported to DT */ 19c8b08822SBiju Das LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2, 20c8b08822SBiju Das 21c8b08822SBiju Das /* External Input Clocks */ 22c8b08822SBiju Das CLK_EXTAL, 23c8b08822SBiju Das 24c8b08822SBiju Das /* Internal Core Clocks */ 25c8b08822SBiju Das CLK_OSC_DIV1000, 26c8b08822SBiju Das CLK_PLL1, 27c8b08822SBiju Das CLK_PLL2, 28c8b08822SBiju Das CLK_PLL2_DIV2, 29c8b08822SBiju Das CLK_PLL2_DIV2_8, 30c8b08822SBiju Das CLK_PLL3, 31c8b08822SBiju Das CLK_PLL3_DIV2, 32c8b08822SBiju Das CLK_PLL3_DIV2_4, 33c8b08822SBiju Das CLK_PLL3_DIV2_4_2, 34c8b08822SBiju Das CLK_PLL5, 35c8b08822SBiju Das CLK_PLL6, 36c8b08822SBiju Das CLK_P1_DIV2, 37c8b08822SBiju Das 38c8b08822SBiju Das /* Module Clocks */ 39c8b08822SBiju Das MOD_CLK_BASE, 40c8b08822SBiju Das }; 41c8b08822SBiju Das 42c8b08822SBiju Das /* Divider tables */ 43c8b08822SBiju Das static const struct clk_div_table dtable_1_8[] = { 44c8b08822SBiju Das {0, 1}, 45c8b08822SBiju Das {1, 2}, 46c8b08822SBiju Das {2, 4}, 47c8b08822SBiju Das {3, 8}, 48c8b08822SBiju Das {0, 0}, 49c8b08822SBiju Das }; 50c8b08822SBiju Das 51c8b08822SBiju Das static const struct clk_div_table dtable_1_32[] = { 52c8b08822SBiju Das {0, 1}, 53c8b08822SBiju Das {1, 2}, 54c8b08822SBiju Das {2, 4}, 55c8b08822SBiju Das {3, 8}, 56c8b08822SBiju Das {4, 32}, 57c8b08822SBiju Das {0, 0}, 58c8b08822SBiju Das }; 59c8b08822SBiju Das 60c8b08822SBiju Das static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 61c8b08822SBiju Das /* External Clock Inputs */ 62c8b08822SBiju Das DEF_INPUT("extal", CLK_EXTAL), 63c8b08822SBiju Das 64c8b08822SBiju Das /* Internal Core Clocks */ 65c8b08822SBiju Das DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1), 66c8b08822SBiju Das DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), 67c8b08822SBiju Das DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), 68c8b08822SBiju Das DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), 69c8b08822SBiju Das DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), 70c8b08822SBiju Das DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), 71c8b08822SBiju Das DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), 72c8b08822SBiju Das DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), 73c8b08822SBiju Das DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), 74c8b08822SBiju Das DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), 75c8b08822SBiju Das DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), 76c8b08822SBiju Das DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), 77c8b08822SBiju Das 78c8b08822SBiju Das /* Core output clk */ 79c8b08822SBiju Das DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, 80c8b08822SBiju Das CLK_DIVIDER_HIWORD_MASK), 81c8b08822SBiju Das DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, 82c8b08822SBiju Das dtable_1_32, CLK_DIVIDER_HIWORD_MASK), 83c8b08822SBiju Das DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, 84c8b08822SBiju Das DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), 85c8b08822SBiju Das DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), 86c8b08822SBiju Das DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, 87c8b08822SBiju Das DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), 88c8b08822SBiju Das }; 89c8b08822SBiju Das 90c8b08822SBiju Das static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 91c8b08822SBiju Das DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, 92c8b08822SBiju Das 0x514, 0), 93c8b08822SBiju Das DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2, 94c8b08822SBiju Das 0x518, 0), 95c8b08822SBiju Das DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1, 96c8b08822SBiju Das 0x518, 1), 97c8b08822SBiju Das DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1, 98c8b08822SBiju Das 0x52c, 0), 99c8b08822SBiju Das DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, 100c8b08822SBiju Das 0x52c, 1), 101c8b08822SBiju Das DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0, 102c8b08822SBiju Das 0x584, 0), 103c8b08822SBiju Das DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0, 104c8b08822SBiju Das 0x584, 1), 105c8b08822SBiju Das DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0, 106c8b08822SBiju Das 0x584, 2), 107c8b08822SBiju Das DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0, 108c8b08822SBiju Das 0x584, 3), 109c8b08822SBiju Das DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0, 110c8b08822SBiju Das 0x584, 4), 111c8b08822SBiju Das DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0, 112c8b08822SBiju Das 0x588, 0), 113c8b08822SBiju Das DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, 114c8b08822SBiju Das 0x588, 1), 115*6c185664SBiju Das DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, 116*6c185664SBiju Das 0x598, 0), 117c8b08822SBiju Das }; 118c8b08822SBiju Das 119c8b08822SBiju Das static struct rzg2l_reset r9a07g043_resets[] = { 120c8b08822SBiju Das DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0), 121c8b08822SBiju Das DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1), 122c8b08822SBiju Das DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), 123c8b08822SBiju Das DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), 124c8b08822SBiju Das DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), 125c8b08822SBiju Das DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0), 126c8b08822SBiju Das DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1), 127c8b08822SBiju Das DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2), 128c8b08822SBiju Das DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3), 129c8b08822SBiju Das DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), 130c8b08822SBiju Das DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), 131c8b08822SBiju Das DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), 132*6c185664SBiju Das DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), 133*6c185664SBiju Das DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), 134*6c185664SBiju Das DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), 135c8b08822SBiju Das }; 136c8b08822SBiju Das 137c8b08822SBiju Das static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { 138c8b08822SBiju Das MOD_CLK_BASE + R9A07G043_GIC600_GICCLK, 139c8b08822SBiju Das MOD_CLK_BASE + R9A07G043_IA55_CLK, 140c8b08822SBiju Das MOD_CLK_BASE + R9A07G043_DMAC_ACLK, 141c8b08822SBiju Das }; 142c8b08822SBiju Das 143c8b08822SBiju Das const struct rzg2l_cpg_info r9a07g043_cpg_info = { 144c8b08822SBiju Das /* Core Clocks */ 145c8b08822SBiju Das .core_clks = r9a07g043_core_clks, 146c8b08822SBiju Das .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks), 147c8b08822SBiju Das .last_dt_core_clk = LAST_DT_CORE_CLK, 148c8b08822SBiju Das .num_total_core_clks = MOD_CLK_BASE, 149c8b08822SBiju Das 150c8b08822SBiju Das /* Critical Module Clocks */ 151c8b08822SBiju Das .crit_mod_clks = r9a07g043_crit_mod_clks, 152c8b08822SBiju Das .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks), 153c8b08822SBiju Das 154c8b08822SBiju Das /* Module Clocks */ 155c8b08822SBiju Das .mod_clks = r9a07g043_mod_clks, 156c8b08822SBiju Das .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks), 157c8b08822SBiju Das .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1, 158c8b08822SBiju Das 159c8b08822SBiju Das /* Resets */ 160c8b08822SBiju Das .resets = r9a07g043_resets, 161c8b08822SBiju Das .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ 162c8b08822SBiju Das }; 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