1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R9A06G032 clock driver 4 * 5 * Copyright (C) 2018 Renesas Electronics Europe Limited 6 * 7 * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/math64.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_clock.h> 22 #include <linux/pm_domain.h> 23 #include <linux/slab.h> 24 #include <linux/soc/renesas/r9a06g032-sysctrl.h> 25 #include <linux/spinlock.h> 26 #include <dt-bindings/clock/r9a06g032-sysctrl.h> 27 28 #define R9A06G032_SYSCTRL_DMAMUX 0xA0 29 30 struct r9a06g032_gate { 31 u16 gate, reset, ready, midle, 32 scon, mirack, mistat; 33 }; 34 35 /* This is used to describe a clock for instantiation */ 36 struct r9a06g032_clkdesc { 37 const char *name; 38 uint32_t managed: 1; 39 uint32_t type: 3; 40 uint32_t index: 8; 41 uint32_t source : 8; /* source index + 1 (0 == none) */ 42 /* these are used to populate the bitsel struct */ 43 union { 44 struct r9a06g032_gate gate; 45 /* for dividers */ 46 struct { 47 unsigned int div_min : 10, div_max : 10, reg: 10; 48 u16 div_table[4]; 49 }; 50 /* For fixed-factor ones */ 51 struct { 52 u16 div, mul; 53 }; 54 unsigned int factor; 55 unsigned int frequency; 56 /* for dual gate */ 57 struct { 58 uint16_t group : 1, index: 3; 59 u16 sel, g1, r1, g2, r2; 60 } dual; 61 }; 62 }; 63 64 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \ 65 { .gate = _clk, .reset = _rst, \ 66 .ready = _rdy, .midle = _midle, \ 67 .scon = _scon, .mirack = _mirack, .mistat = _mistat } 68 #define D_GATE(_idx, _n, _src, ...) \ 69 { .type = K_GATE, .index = R9A06G032_##_idx, \ 70 .source = 1 + R9A06G032_##_src, .name = _n, \ 71 .gate = I_GATE(__VA_ARGS__) } 72 #define D_MODULE(_idx, _n, _src, ...) \ 73 { .type = K_GATE, .index = R9A06G032_##_idx, \ 74 .source = 1 + R9A06G032_##_src, .name = _n, \ 75 .managed = 1, .gate = I_GATE(__VA_ARGS__) } 76 #define D_ROOT(_idx, _n, _mul, _div) \ 77 { .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \ 78 .div = _div, .mul = _mul } 79 #define D_FFC(_idx, _n, _src, _div) \ 80 { .type = K_FFC, .index = R9A06G032_##_idx, \ 81 .source = 1 + R9A06G032_##_src, .name = _n, \ 82 .div = _div, .mul = 1} 83 #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \ 84 { .type = K_DIV, .index = R9A06G032_##_idx, \ 85 .source = 1 + R9A06G032_##_src, .name = _n, \ 86 .reg = _reg, .div_min = _min, .div_max = _max, \ 87 .div_table = { __VA_ARGS__ } } 88 #define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \ 89 { .type = K_DUALGATE, .index = R9A06G032_##_idx, \ 90 .source = 1 + R9A06G032_##_src, .name = _n, \ 91 .dual = { .group = _g, .index = _gi, \ 92 .g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, } 93 94 enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE }; 95 96 /* Internal clock IDs */ 97 #define R9A06G032_CLKOUT 0 98 #define R9A06G032_CLKOUT_D10 2 99 #define R9A06G032_CLKOUT_D16 3 100 #define R9A06G032_CLKOUT_D160 4 101 #define R9A06G032_CLKOUT_D1OR2 5 102 #define R9A06G032_CLKOUT_D20 6 103 #define R9A06G032_CLKOUT_D40 7 104 #define R9A06G032_CLKOUT_D5 8 105 #define R9A06G032_CLKOUT_D8 9 106 #define R9A06G032_DIV_ADC 10 107 #define R9A06G032_DIV_I2C 11 108 #define R9A06G032_DIV_NAND 12 109 #define R9A06G032_DIV_P1_PG 13 110 #define R9A06G032_DIV_P2_PG 14 111 #define R9A06G032_DIV_P3_PG 15 112 #define R9A06G032_DIV_P4_PG 16 113 #define R9A06G032_DIV_P5_PG 17 114 #define R9A06G032_DIV_P6_PG 18 115 #define R9A06G032_DIV_QSPI0 19 116 #define R9A06G032_DIV_QSPI1 20 117 #define R9A06G032_DIV_REF_SYNC 21 118 #define R9A06G032_DIV_SDIO0 22 119 #define R9A06G032_DIV_SDIO1 23 120 #define R9A06G032_DIV_SWITCH 24 121 #define R9A06G032_DIV_UART 25 122 #define R9A06G032_DIV_MOTOR 64 123 #define R9A06G032_CLK_DDRPHY_PLLCLK_D4 78 124 #define R9A06G032_CLK_ECAT100_D4 79 125 #define R9A06G032_CLK_HSR100_D2 80 126 #define R9A06G032_CLK_REF_SYNC_D4 81 127 #define R9A06G032_CLK_REF_SYNC_D8 82 128 #define R9A06G032_CLK_SERCOS100_D2 83 129 #define R9A06G032_DIV_CA7 84 130 131 #define R9A06G032_UART_GROUP_012 154 132 #define R9A06G032_UART_GROUP_34567 155 133 134 #define R9A06G032_CLOCK_COUNT (R9A06G032_UART_GROUP_34567 + 1) 135 136 static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { 137 D_ROOT(CLKOUT, "clkout", 25, 1), 138 D_ROOT(CLK_PLL_USB, "clk_pll_usb", 12, 10), 139 D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10), 140 D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16), 141 D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160), 142 D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2), 143 D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20), 144 D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40), 145 D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5), 146 D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8), 147 D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250), 148 D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16), 149 D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32), 150 D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200), 151 D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128), 152 D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128), 153 D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128), 154 D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40), 155 D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64), 156 D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7), 157 D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7), 158 D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16), 159 D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128), 160 D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128), 161 D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40), 162 D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128), 163 D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0), 164 D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0), 165 D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0), 166 D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0), 167 D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0), 168 D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0), 169 D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, 0x405, 0, 0, 0, 0, 0, 0), 170 D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, 0x483, 0, 0, 0, 0, 0, 0), 171 D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, 0x1e6, 0x1e7, 0, 0, 0, 0, 0), 172 D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, 0x1e8, 0x1e9, 0, 0, 0, 0, 0), 173 D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, 0x342, 0, 0, 0, 0, 0, 0), 174 D_GATE(CLK_NAND, "clk_nand", DIV_NAND, 0x284, 0x285, 0, 0, 0, 0, 0), 175 D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, 0x774, 0x775, 0, 0, 0, 0, 0), 176 D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, 0x862, 0x863, 0, 0, 0, 0, 0), 177 D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, 0x864, 0x865, 0, 0, 0, 0, 0), 178 D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, 0x866, 0x867, 0, 0, 0, 0, 0), 179 D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, 0x824, 0x825, 0, 0, 0, 0, 0), 180 D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, 0x826, 0x827, 0, 0, 0, 0, 0), 181 D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, 0x8a0, 0x8a1, 0x8a2, 0, 0xb60, 0, 0), 182 D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0), 183 D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0), 184 D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0), 185 D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0), 186 D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0), 187 D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0), 188 D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0), 189 D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, 0x341, 0, 0, 0, 0, 0, 0), 190 D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, 0x64, 0, 0, 0, 0, 0, 0), 191 D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, 0x644, 0, 0, 0, 0, 0, 0), 192 D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, 0x425, 0, 0, 0, 0, 0, 0), 193 D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, 0x860, 0x861, 0, 0, 0, 0, 0), 194 D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, 0x7e0, 0x7e1, 0, 0, 0, 0, 0), 195 D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, 0x7e2, 0x7e3, 0, 0, 0, 0, 0), 196 D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, 0x7e4, 0x7e5, 0, 0, 0, 0, 0), 197 D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, 0x7e6, 0x7e7, 0, 0, 0, 0, 0), 198 D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, 0x820, 0x821, 0, 0, 0, 0, 0), 199 D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, 0x822, 0x823, 0, 0, 0, 0, 0), 200 D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, 0x982, 0x983, 0, 0, 0, 0, 0), 201 D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8), 202 D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441), 203 D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0), 204 D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461), 205 D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0), 206 D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0), 207 D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0), 208 D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0), 209 D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0), 210 D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103), 211 D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101), 212 D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0), 213 D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, 0x78c, 0x78d, 0, 0x78e, 0, 0xb04, 0xb05), 214 D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, 0x789, 0x78a, 0x78b, 0, 0xb03, 0, 0), 215 D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4), 216 D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4), 217 D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2), 218 D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4), 219 D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8), 220 D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2), 221 D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4), 222 D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0), 223 D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0), 224 D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0), 225 D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0), 226 D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0), 227 D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0), 228 D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0), 229 D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640), 230 D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, 0xba0, 0xba1, 0, 0xba2, 0, 0xbc0, 0xbc1), 231 D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, 0x323, 0x324, 0, 0, 0, 0, 0), 232 D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, 0x403, 0x404, 0, 0, 0, 0, 0), 233 D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, 0x484, 0x485, 0, 0, 0, 0, 0), 234 D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, 0xc60, 0xc61, 0, 0, 0, 0, 0), 235 D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, 0x424, 0x423, 0, 0, 0, 0, 0), 236 D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0), 237 D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0), 238 D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0), 239 D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141), 240 D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1), 241 D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2), 242 D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5), 243 D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2), 244 D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2), 245 D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0), 246 D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0), 247 D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0), 248 D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1), 249 D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0), 250 D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0), 251 D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0), 252 D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0), 253 D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182), 254 D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2), 255 D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25), 256 D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0), 257 D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0), 258 D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0), 259 D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0), 260 D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302), 261 D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2), 262 D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0), 263 D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0xa03, 0, 0xa02, 0, 0, 0), 264 D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82), 265 D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662), 266 D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0), 267 D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0), 268 D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0), 269 D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0), 270 D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0), 271 D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0), 272 D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0), 273 D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0), 274 D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0), 275 D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0), 276 D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0), 277 D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0), 278 D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0), 279 D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0), 280 D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0), 281 D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0), 282 D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0), 283 /* 284 * These are not hardware clocks, but are needed to handle the special 285 * case where we have a 'selector bit' that doesn't just change the 286 * parent for a clock, but also the gate it's supposed to use. 287 */ 288 { 289 .index = R9A06G032_UART_GROUP_012, 290 .name = "uart_group_012", 291 .type = K_BITSEL, 292 .source = 1 + R9A06G032_DIV_UART, 293 /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */ 294 .dual.sel = ((0xec / 4) << 5) | 24, 295 .dual.group = 0, 296 }, 297 { 298 .index = R9A06G032_UART_GROUP_34567, 299 .name = "uart_group_34567", 300 .type = K_BITSEL, 301 .source = 1 + R9A06G032_DIV_P2_PG, 302 /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */ 303 .dual.sel = ((0x34 / 4) << 5) | 30, 304 .dual.group = 1, 305 }, 306 D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5), 307 D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9), 308 D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd), 309 D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763), 310 D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767), 311 D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b), 312 D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f), 313 D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773), 314 }; 315 316 struct r9a06g032_priv { 317 struct clk_onecell_data data; 318 spinlock_t lock; /* protects concurrent access to gates */ 319 void __iomem *reg; 320 }; 321 322 static struct r9a06g032_priv *sysctrl_priv; 323 324 /* Exported helper to access the DMAMUX register */ 325 int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) 326 { 327 unsigned long flags; 328 u32 dmamux; 329 330 if (!sysctrl_priv) 331 return -EPROBE_DEFER; 332 333 spin_lock_irqsave(&sysctrl_priv->lock, flags); 334 335 dmamux = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX); 336 dmamux &= ~mask; 337 dmamux |= val & mask; 338 writel(dmamux, sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX); 339 340 spin_unlock_irqrestore(&sysctrl_priv->lock, flags); 341 342 return 0; 343 } 344 EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux); 345 346 /* register/bit pairs are encoded as an uint16_t */ 347 static void 348 clk_rdesc_set(struct r9a06g032_priv *clocks, 349 u16 one, unsigned int on) 350 { 351 u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); 352 u32 val = readl(reg); 353 354 val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f)); 355 writel(val, reg); 356 } 357 358 static int 359 clk_rdesc_get(struct r9a06g032_priv *clocks, 360 uint16_t one) 361 { 362 u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); 363 u32 val = readl(reg); 364 365 return !!(val & (1U << (one & 0x1f))); 366 } 367 368 /* 369 * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's 370 * clock gate framework as the gates on the R9A06G032 have a special enabling 371 * sequence, therefore we use this little proxy. 372 */ 373 struct r9a06g032_clk_gate { 374 struct clk_hw hw; 375 struct r9a06g032_priv *clocks; 376 u16 index; 377 378 struct r9a06g032_gate gate; 379 }; 380 381 #define to_r9a06g032_gate(_hw) container_of(_hw, struct r9a06g032_clk_gate, hw) 382 383 static int create_add_module_clock(struct of_phandle_args *clkspec, 384 struct device *dev) 385 { 386 struct clk *clk; 387 int error; 388 389 clk = of_clk_get_from_provider(clkspec); 390 if (IS_ERR(clk)) 391 return PTR_ERR(clk); 392 393 error = pm_clk_create(dev); 394 if (error) { 395 clk_put(clk); 396 return error; 397 } 398 399 error = pm_clk_add_clk(dev, clk); 400 if (error) { 401 pm_clk_destroy(dev); 402 clk_put(clk); 403 } 404 405 return error; 406 } 407 408 static int r9a06g032_attach_dev(struct generic_pm_domain *pd, 409 struct device *dev) 410 { 411 struct device_node *np = dev->of_node; 412 struct of_phandle_args clkspec; 413 int i = 0; 414 int error; 415 int index; 416 417 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, 418 &clkspec)) { 419 if (clkspec.np != pd->dev.of_node) 420 continue; 421 422 index = clkspec.args[0]; 423 if (index < R9A06G032_CLOCK_COUNT && 424 r9a06g032_clocks[index].managed) { 425 error = create_add_module_clock(&clkspec, dev); 426 of_node_put(clkspec.np); 427 if (error) 428 return error; 429 } 430 i++; 431 } 432 433 return 0; 434 } 435 436 static void r9a06g032_detach_dev(struct generic_pm_domain *unused, struct device *dev) 437 { 438 if (!pm_clk_no_clocks(dev)) 439 pm_clk_destroy(dev); 440 } 441 442 static int r9a06g032_add_clk_domain(struct device *dev) 443 { 444 struct device_node *np = dev->of_node; 445 struct generic_pm_domain *pd; 446 447 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); 448 if (!pd) 449 return -ENOMEM; 450 451 pd->name = np->name; 452 pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | 453 GENPD_FLAG_ACTIVE_WAKEUP; 454 pd->attach_dev = r9a06g032_attach_dev; 455 pd->detach_dev = r9a06g032_detach_dev; 456 pm_genpd_init(pd, &pm_domain_always_on_gov, false); 457 458 of_genpd_add_provider_simple(np, pd); 459 return 0; 460 } 461 462 static void 463 r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks, 464 struct r9a06g032_gate *g, int on) 465 { 466 unsigned long flags; 467 468 WARN_ON(!g->gate); 469 470 spin_lock_irqsave(&clocks->lock, flags); 471 clk_rdesc_set(clocks, g->gate, on); 472 /* De-assert reset */ 473 if (g->reset) 474 clk_rdesc_set(clocks, g->reset, 1); 475 spin_unlock_irqrestore(&clocks->lock, flags); 476 477 /* Hardware manual recommends 5us delay after enabling clock & reset */ 478 udelay(5); 479 480 /* If the peripheral is memory mapped (i.e. an AXI slave), there is an 481 * associated SLVRDY bit in the System Controller that needs to be set 482 * so that the FlexWAY bus fabric passes on the read/write requests. 483 */ 484 if (g->ready || g->midle) { 485 spin_lock_irqsave(&clocks->lock, flags); 486 if (g->ready) 487 clk_rdesc_set(clocks, g->ready, on); 488 /* Clear 'Master Idle Request' bit */ 489 if (g->midle) 490 clk_rdesc_set(clocks, g->midle, !on); 491 spin_unlock_irqrestore(&clocks->lock, flags); 492 } 493 /* Note: We don't wait for FlexWAY Socket Connection signal */ 494 } 495 496 static int r9a06g032_clk_gate_enable(struct clk_hw *hw) 497 { 498 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw); 499 500 r9a06g032_clk_gate_set(g->clocks, &g->gate, 1); 501 return 0; 502 } 503 504 static void r9a06g032_clk_gate_disable(struct clk_hw *hw) 505 { 506 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw); 507 508 r9a06g032_clk_gate_set(g->clocks, &g->gate, 0); 509 } 510 511 static int r9a06g032_clk_gate_is_enabled(struct clk_hw *hw) 512 { 513 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw); 514 515 /* if clock is in reset, the gate might be on, and still not 'be' on */ 516 if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset)) 517 return 0; 518 519 return clk_rdesc_get(g->clocks, g->gate.gate); 520 } 521 522 static const struct clk_ops r9a06g032_clk_gate_ops = { 523 .enable = r9a06g032_clk_gate_enable, 524 .disable = r9a06g032_clk_gate_disable, 525 .is_enabled = r9a06g032_clk_gate_is_enabled, 526 }; 527 528 static struct clk * 529 r9a06g032_register_gate(struct r9a06g032_priv *clocks, 530 const char *parent_name, 531 const struct r9a06g032_clkdesc *desc) 532 { 533 struct clk *clk; 534 struct r9a06g032_clk_gate *g; 535 struct clk_init_data init = {}; 536 537 g = kzalloc(sizeof(*g), GFP_KERNEL); 538 if (!g) 539 return NULL; 540 541 init.name = desc->name; 542 init.ops = &r9a06g032_clk_gate_ops; 543 init.flags = CLK_SET_RATE_PARENT; 544 init.parent_names = parent_name ? &parent_name : NULL; 545 init.num_parents = parent_name ? 1 : 0; 546 547 g->clocks = clocks; 548 g->index = desc->index; 549 g->gate = desc->gate; 550 g->hw.init = &init; 551 552 /* 553 * important here, some clocks are already in use by the CM3, we 554 * have to assume they are not Linux's to play with and try to disable 555 * at the end of the boot! 556 */ 557 if (r9a06g032_clk_gate_is_enabled(&g->hw)) { 558 init.flags |= CLK_IS_CRITICAL; 559 pr_debug("%s was enabled, making read-only\n", desc->name); 560 } 561 562 clk = clk_register(NULL, &g->hw); 563 if (IS_ERR(clk)) { 564 kfree(g); 565 return NULL; 566 } 567 return clk; 568 } 569 570 struct r9a06g032_clk_div { 571 struct clk_hw hw; 572 struct r9a06g032_priv *clocks; 573 u16 index; 574 u16 reg; 575 u16 min, max; 576 u8 table_size; 577 u16 table[8]; /* we know there are no more than 8 */ 578 }; 579 580 #define to_r9a06g032_div(_hw) \ 581 container_of(_hw, struct r9a06g032_clk_div, hw) 582 583 static unsigned long 584 r9a06g032_div_recalc_rate(struct clk_hw *hw, 585 unsigned long parent_rate) 586 { 587 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); 588 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg); 589 u32 div = readl(reg); 590 591 if (div < clk->min) 592 div = clk->min; 593 else if (div > clk->max) 594 div = clk->max; 595 return DIV_ROUND_UP(parent_rate, div); 596 } 597 598 /* 599 * Attempts to find a value that is in range of min,max, 600 * and if a table of set dividers was specified for this 601 * register, try to find the fixed divider that is the closest 602 * to the target frequency 603 */ 604 static long 605 r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk, 606 unsigned long rate, unsigned long prate) 607 { 608 /* + 1 to cope with rates that have the remainder dropped */ 609 u32 div = DIV_ROUND_UP(prate, rate + 1); 610 int i; 611 612 if (div <= clk->min) 613 return clk->min; 614 if (div >= clk->max) 615 return clk->max; 616 617 for (i = 0; clk->table_size && i < clk->table_size - 1; i++) { 618 if (div >= clk->table[i] && div <= clk->table[i + 1]) { 619 unsigned long m = rate - 620 DIV_ROUND_UP(prate, clk->table[i]); 621 unsigned long p = 622 DIV_ROUND_UP(prate, clk->table[i + 1]) - 623 rate; 624 /* 625 * select the divider that generates 626 * the value closest to the ideal frequency 627 */ 628 div = p >= m ? clk->table[i] : clk->table[i + 1]; 629 return div; 630 } 631 } 632 return div; 633 } 634 635 static int 636 r9a06g032_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 637 { 638 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); 639 u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate); 640 641 pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__, 642 hw->clk, req->rate, req->best_parent_rate, div); 643 pr_devel(" min %d (%ld) max %d (%ld)\n", 644 clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min), 645 clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max)); 646 647 div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate); 648 /* 649 * this is a hack. Currently the serial driver asks for a clock rate 650 * that is 16 times the baud rate -- and that is wildly outside the 651 * range of the UART divider, somehow there is no provision for that 652 * case of 'let the divider as is if outside range'. 653 * The serial driver *shouldn't* play with these clocks anyway, there's 654 * several uarts attached to this divider, and changing this impacts 655 * everyone. 656 */ 657 if (clk->index == R9A06G032_DIV_UART || 658 clk->index == R9A06G032_DIV_P2_PG) { 659 pr_devel("%s div uart hack!\n", __func__); 660 req->rate = clk_get_rate(hw->clk); 661 return 0; 662 } 663 req->rate = DIV_ROUND_UP(req->best_parent_rate, div); 664 pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk, 665 req->best_parent_rate, div, req->rate); 666 return 0; 667 } 668 669 static int 670 r9a06g032_div_set_rate(struct clk_hw *hw, 671 unsigned long rate, unsigned long parent_rate) 672 { 673 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); 674 /* + 1 to cope with rates that have the remainder dropped */ 675 u32 div = DIV_ROUND_UP(parent_rate, rate + 1); 676 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg); 677 678 pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk, 679 rate, parent_rate, div); 680 681 /* 682 * Need to write the bit 31 with the divider value to 683 * latch it. Technically we should wait until it has been 684 * cleared too. 685 * TODO: Find whether this callback is sleepable, in case 686 * the hardware /does/ require some sort of spinloop here. 687 */ 688 writel(div | BIT(31), reg); 689 690 return 0; 691 } 692 693 static const struct clk_ops r9a06g032_clk_div_ops = { 694 .recalc_rate = r9a06g032_div_recalc_rate, 695 .determine_rate = r9a06g032_div_determine_rate, 696 .set_rate = r9a06g032_div_set_rate, 697 }; 698 699 static struct clk * 700 r9a06g032_register_div(struct r9a06g032_priv *clocks, 701 const char *parent_name, 702 const struct r9a06g032_clkdesc *desc) 703 { 704 struct r9a06g032_clk_div *div; 705 struct clk *clk; 706 struct clk_init_data init = {}; 707 unsigned int i; 708 709 div = kzalloc(sizeof(*div), GFP_KERNEL); 710 if (!div) 711 return NULL; 712 713 init.name = desc->name; 714 init.ops = &r9a06g032_clk_div_ops; 715 init.flags = CLK_SET_RATE_PARENT; 716 init.parent_names = parent_name ? &parent_name : NULL; 717 init.num_parents = parent_name ? 1 : 0; 718 719 div->clocks = clocks; 720 div->index = desc->index; 721 div->reg = desc->reg; 722 div->hw.init = &init; 723 div->min = desc->div_min; 724 div->max = desc->div_max; 725 /* populate (optional) divider table fixed values */ 726 for (i = 0; i < ARRAY_SIZE(div->table) && 727 i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) { 728 div->table[div->table_size++] = desc->div_table[i]; 729 } 730 731 clk = clk_register(NULL, &div->hw); 732 if (IS_ERR(clk)) { 733 kfree(div); 734 return NULL; 735 } 736 return clk; 737 } 738 739 /* 740 * This clock provider handles the case of the R9A06G032 where you have 741 * peripherals that have two potential clock source and two gates, one for 742 * each of the clock source - the used clock source (for all sub clocks) 743 * is selected by a single bit. 744 * That single bit affects all sub-clocks, and therefore needs to change the 745 * active gate (and turn the others off) and force a recalculation of the rates. 746 * 747 * This implements two clock providers, one 'bitselect' that 748 * handles the switch between both parents, and another 'dualgate' 749 * that knows which gate to poke at, depending on the parent's bit position. 750 */ 751 struct r9a06g032_clk_bitsel { 752 struct clk_hw hw; 753 struct r9a06g032_priv *clocks; 754 u16 index; 755 u16 selector; /* selector register + bit */ 756 }; 757 758 #define to_clk_bitselect(_hw) \ 759 container_of(_hw, struct r9a06g032_clk_bitsel, hw) 760 761 static u8 r9a06g032_clk_mux_get_parent(struct clk_hw *hw) 762 { 763 struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw); 764 765 return clk_rdesc_get(set->clocks, set->selector); 766 } 767 768 static int r9a06g032_clk_mux_set_parent(struct clk_hw *hw, u8 index) 769 { 770 struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw); 771 772 /* a single bit in the register selects one of two parent clocks */ 773 clk_rdesc_set(set->clocks, set->selector, !!index); 774 775 return 0; 776 } 777 778 static const struct clk_ops clk_bitselect_ops = { 779 .get_parent = r9a06g032_clk_mux_get_parent, 780 .set_parent = r9a06g032_clk_mux_set_parent, 781 }; 782 783 static struct clk * 784 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks, 785 const char *parent_name, 786 const struct r9a06g032_clkdesc *desc) 787 { 788 struct clk *clk; 789 struct r9a06g032_clk_bitsel *g; 790 struct clk_init_data init = {}; 791 const char *names[2]; 792 793 /* allocate the gate */ 794 g = kzalloc(sizeof(*g), GFP_KERNEL); 795 if (!g) 796 return NULL; 797 798 names[0] = parent_name; 799 names[1] = "clk_pll_usb"; 800 801 init.name = desc->name; 802 init.ops = &clk_bitselect_ops; 803 init.flags = CLK_SET_RATE_PARENT; 804 init.parent_names = names; 805 init.num_parents = 2; 806 807 g->clocks = clocks; 808 g->index = desc->index; 809 g->selector = desc->dual.sel; 810 g->hw.init = &init; 811 812 clk = clk_register(NULL, &g->hw); 813 if (IS_ERR(clk)) { 814 kfree(g); 815 return NULL; 816 } 817 return clk; 818 } 819 820 struct r9a06g032_clk_dualgate { 821 struct clk_hw hw; 822 struct r9a06g032_priv *clocks; 823 u16 index; 824 u16 selector; /* selector register + bit */ 825 struct r9a06g032_gate gate[2]; 826 }; 827 828 #define to_clk_dualgate(_hw) \ 829 container_of(_hw, struct r9a06g032_clk_dualgate, hw) 830 831 static int 832 r9a06g032_clk_dualgate_setenable(struct r9a06g032_clk_dualgate *g, int enable) 833 { 834 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector); 835 836 /* we always turn off the 'other' gate, regardless */ 837 r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0); 838 r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable); 839 840 return 0; 841 } 842 843 static int r9a06g032_clk_dualgate_enable(struct clk_hw *hw) 844 { 845 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw); 846 847 r9a06g032_clk_dualgate_setenable(gate, 1); 848 849 return 0; 850 } 851 852 static void r9a06g032_clk_dualgate_disable(struct clk_hw *hw) 853 { 854 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw); 855 856 r9a06g032_clk_dualgate_setenable(gate, 0); 857 } 858 859 static int r9a06g032_clk_dualgate_is_enabled(struct clk_hw *hw) 860 { 861 struct r9a06g032_clk_dualgate *g = to_clk_dualgate(hw); 862 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector); 863 864 return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate); 865 } 866 867 static const struct clk_ops r9a06g032_clk_dualgate_ops = { 868 .enable = r9a06g032_clk_dualgate_enable, 869 .disable = r9a06g032_clk_dualgate_disable, 870 .is_enabled = r9a06g032_clk_dualgate_is_enabled, 871 }; 872 873 static struct clk * 874 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks, 875 const char *parent_name, 876 const struct r9a06g032_clkdesc *desc, 877 uint16_t sel) 878 { 879 struct r9a06g032_clk_dualgate *g; 880 struct clk *clk; 881 struct clk_init_data init = {}; 882 883 /* allocate the gate */ 884 g = kzalloc(sizeof(*g), GFP_KERNEL); 885 if (!g) 886 return NULL; 887 g->clocks = clocks; 888 g->index = desc->index; 889 g->selector = sel; 890 g->gate[0].gate = desc->dual.g1; 891 g->gate[0].reset = desc->dual.r1; 892 g->gate[1].gate = desc->dual.g2; 893 g->gate[1].reset = desc->dual.r2; 894 895 init.name = desc->name; 896 init.ops = &r9a06g032_clk_dualgate_ops; 897 init.flags = CLK_SET_RATE_PARENT; 898 init.parent_names = &parent_name; 899 init.num_parents = 1; 900 g->hw.init = &init; 901 /* 902 * important here, some clocks are already in use by the CM3, we 903 * have to assume they are not Linux's to play with and try to disable 904 * at the end of the boot! 905 */ 906 if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) { 907 init.flags |= CLK_IS_CRITICAL; 908 pr_debug("%s was enabled, making read-only\n", desc->name); 909 } 910 911 clk = clk_register(NULL, &g->hw); 912 if (IS_ERR(clk)) { 913 kfree(g); 914 return NULL; 915 } 916 return clk; 917 } 918 919 static void r9a06g032_clocks_del_clk_provider(void *data) 920 { 921 of_clk_del_provider(data); 922 } 923 924 static int __init r9a06g032_clocks_probe(struct platform_device *pdev) 925 { 926 struct device *dev = &pdev->dev; 927 struct device_node *np = dev->of_node; 928 struct r9a06g032_priv *clocks; 929 struct clk **clks; 930 struct clk *mclk; 931 unsigned int i; 932 u16 uart_group_sel[2]; 933 int error; 934 935 clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL); 936 clks = devm_kcalloc(dev, R9A06G032_CLOCK_COUNT, sizeof(struct clk *), 937 GFP_KERNEL); 938 if (!clocks || !clks) 939 return -ENOMEM; 940 941 spin_lock_init(&clocks->lock); 942 943 clocks->data.clks = clks; 944 clocks->data.clk_num = R9A06G032_CLOCK_COUNT; 945 946 mclk = devm_clk_get(dev, "mclk"); 947 if (IS_ERR(mclk)) 948 return PTR_ERR(mclk); 949 950 clocks->reg = of_iomap(np, 0); 951 if (WARN_ON(!clocks->reg)) 952 return -ENOMEM; 953 for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) { 954 const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i]; 955 const char *parent_name = d->source ? 956 __clk_get_name(clocks->data.clks[d->source - 1]) : 957 __clk_get_name(mclk); 958 struct clk *clk = NULL; 959 960 switch (d->type) { 961 case K_FFC: 962 clk = clk_register_fixed_factor(NULL, d->name, 963 parent_name, 0, 964 d->mul, d->div); 965 break; 966 case K_GATE: 967 clk = r9a06g032_register_gate(clocks, parent_name, d); 968 break; 969 case K_DIV: 970 clk = r9a06g032_register_div(clocks, parent_name, d); 971 break; 972 case K_BITSEL: 973 /* keep that selector register around */ 974 uart_group_sel[d->dual.group] = d->dual.sel; 975 clk = r9a06g032_register_bitsel(clocks, parent_name, d); 976 break; 977 case K_DUALGATE: 978 clk = r9a06g032_register_dualgate(clocks, parent_name, 979 d, 980 uart_group_sel[d->dual.group]); 981 break; 982 } 983 clocks->data.clks[d->index] = clk; 984 } 985 error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data); 986 if (error) 987 return error; 988 989 error = devm_add_action_or_reset(dev, 990 r9a06g032_clocks_del_clk_provider, np); 991 if (error) 992 return error; 993 994 error = r9a06g032_add_clk_domain(dev); 995 if (error) 996 return error; 997 998 sysctrl_priv = clocks; 999 1000 error = of_platform_populate(np, NULL, NULL, dev); 1001 if (error) 1002 dev_err(dev, "Failed to populate children (%d)\n", error); 1003 1004 return 0; 1005 } 1006 1007 static const struct of_device_id r9a06g032_match[] = { 1008 { .compatible = "renesas,r9a06g032-sysctrl" }, 1009 { } 1010 }; 1011 1012 static struct platform_driver r9a06g032_clock_driver = { 1013 .driver = { 1014 .name = "renesas,r9a06g032-sysctrl", 1015 .of_match_table = r9a06g032_match, 1016 }, 1017 }; 1018 1019 static int __init r9a06g032_clocks_init(void) 1020 { 1021 return platform_driver_probe(&r9a06g032_clock_driver, 1022 r9a06g032_clocks_probe); 1023 } 1024 1025 subsys_initcall(r9a06g032_clocks_init); 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