1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R9A06G032 clock driver 4 * 5 * Copyright (C) 2018 Renesas Electronics Europe Limited 6 * 7 * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/math64.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_clock.h> 22 #include <linux/pm_domain.h> 23 #include <linux/slab.h> 24 #include <linux/soc/renesas/r9a06g032-sysctrl.h> 25 #include <linux/spinlock.h> 26 #include <dt-bindings/clock/r9a06g032-sysctrl.h> 27 28 #define R9A06G032_SYSCTRL_DMAMUX 0xA0 29 30 struct r9a06g032_gate { 31 u16 gate, reset, ready, midle, 32 scon, mirack, mistat; 33 }; 34 35 /* This is used to describe a clock for instantiation */ 36 struct r9a06g032_clkdesc { 37 const char *name; 38 uint32_t managed: 1; 39 uint32_t type: 3; 40 uint32_t index: 8; 41 uint32_t source : 8; /* source index + 1 (0 == none) */ 42 /* these are used to populate the bitsel struct */ 43 union { 44 struct r9a06g032_gate gate; 45 /* for dividers */ 46 struct { 47 unsigned int div_min : 10, div_max : 10, reg: 10; 48 u16 div_table[4]; 49 }; 50 /* For fixed-factor ones */ 51 struct { 52 u16 div, mul; 53 }; 54 /* for dual gate */ 55 struct { 56 uint16_t group : 1; 57 u16 sel, g1, r1, g2, r2; 58 } dual; 59 }; 60 }; 61 62 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \ 63 { .gate = _clk, .reset = _rst, \ 64 .ready = _rdy, .midle = _midle, \ 65 .scon = _scon, .mirack = _mirack, .mistat = _mistat } 66 #define D_GATE(_idx, _n, _src, ...) \ 67 { .type = K_GATE, .index = R9A06G032_##_idx, \ 68 .source = 1 + R9A06G032_##_src, .name = _n, \ 69 .gate = I_GATE(__VA_ARGS__) } 70 #define D_MODULE(_idx, _n, _src, ...) \ 71 { .type = K_GATE, .index = R9A06G032_##_idx, \ 72 .source = 1 + R9A06G032_##_src, .name = _n, \ 73 .managed = 1, .gate = I_GATE(__VA_ARGS__) } 74 #define D_ROOT(_idx, _n, _mul, _div) \ 75 { .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \ 76 .div = _div, .mul = _mul } 77 #define D_FFC(_idx, _n, _src, _div) \ 78 { .type = K_FFC, .index = R9A06G032_##_idx, \ 79 .source = 1 + R9A06G032_##_src, .name = _n, \ 80 .div = _div, .mul = 1} 81 #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \ 82 { .type = K_DIV, .index = R9A06G032_##_idx, \ 83 .source = 1 + R9A06G032_##_src, .name = _n, \ 84 .reg = _reg, .div_min = _min, .div_max = _max, \ 85 .div_table = { __VA_ARGS__ } } 86 #define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \ 87 { .type = K_DUALGATE, .index = R9A06G032_##_idx, \ 88 .source = 1 + R9A06G032_##_src, .name = _n, \ 89 .dual = { .group = _g, \ 90 .g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, } 91 92 enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE }; 93 94 /* Internal clock IDs */ 95 #define R9A06G032_CLKOUT 0 96 #define R9A06G032_CLKOUT_D10 2 97 #define R9A06G032_CLKOUT_D16 3 98 #define R9A06G032_CLKOUT_D160 4 99 #define R9A06G032_CLKOUT_D1OR2 5 100 #define R9A06G032_CLKOUT_D20 6 101 #define R9A06G032_CLKOUT_D40 7 102 #define R9A06G032_CLKOUT_D5 8 103 #define R9A06G032_CLKOUT_D8 9 104 #define R9A06G032_DIV_ADC 10 105 #define R9A06G032_DIV_I2C 11 106 #define R9A06G032_DIV_NAND 12 107 #define R9A06G032_DIV_P1_PG 13 108 #define R9A06G032_DIV_P2_PG 14 109 #define R9A06G032_DIV_P3_PG 15 110 #define R9A06G032_DIV_P4_PG 16 111 #define R9A06G032_DIV_P5_PG 17 112 #define R9A06G032_DIV_P6_PG 18 113 #define R9A06G032_DIV_QSPI0 19 114 #define R9A06G032_DIV_QSPI1 20 115 #define R9A06G032_DIV_REF_SYNC 21 116 #define R9A06G032_DIV_SDIO0 22 117 #define R9A06G032_DIV_SDIO1 23 118 #define R9A06G032_DIV_SWITCH 24 119 #define R9A06G032_DIV_UART 25 120 #define R9A06G032_DIV_MOTOR 64 121 #define R9A06G032_CLK_DDRPHY_PLLCLK_D4 78 122 #define R9A06G032_CLK_ECAT100_D4 79 123 #define R9A06G032_CLK_HSR100_D2 80 124 #define R9A06G032_CLK_REF_SYNC_D4 81 125 #define R9A06G032_CLK_REF_SYNC_D8 82 126 #define R9A06G032_CLK_SERCOS100_D2 83 127 #define R9A06G032_DIV_CA7 84 128 129 #define R9A06G032_UART_GROUP_012 154 130 #define R9A06G032_UART_GROUP_34567 155 131 132 #define R9A06G032_CLOCK_COUNT (R9A06G032_UART_GROUP_34567 + 1) 133 134 static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { 135 D_ROOT(CLKOUT, "clkout", 25, 1), 136 D_ROOT(CLK_PLL_USB, "clk_pll_usb", 12, 10), 137 D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10), 138 D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16), 139 D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160), 140 D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2), 141 D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20), 142 D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40), 143 D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5), 144 D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8), 145 D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250), 146 D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16), 147 D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32), 148 D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200), 149 D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128), 150 D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128), 151 D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128), 152 D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40), 153 D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64), 154 D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7), 155 D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7), 156 D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16), 157 D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128), 158 D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128), 159 D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40), 160 D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128), 161 D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0), 162 D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0), 163 D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0), 164 D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0), 165 D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0), 166 D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0), 167 D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, 0x405, 0, 0, 0, 0, 0, 0), 168 D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, 0x483, 0, 0, 0, 0, 0, 0), 169 D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, 0x1e6, 0x1e7, 0, 0, 0, 0, 0), 170 D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, 0x1e8, 0x1e9, 0, 0, 0, 0, 0), 171 D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, 0x342, 0, 0, 0, 0, 0, 0), 172 D_GATE(CLK_NAND, "clk_nand", DIV_NAND, 0x284, 0x285, 0, 0, 0, 0, 0), 173 D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, 0x774, 0x775, 0, 0, 0, 0, 0), 174 D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, 0x862, 0x863, 0, 0, 0, 0, 0), 175 D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, 0x864, 0x865, 0, 0, 0, 0, 0), 176 D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, 0x866, 0x867, 0, 0, 0, 0, 0), 177 D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, 0x824, 0x825, 0, 0, 0, 0, 0), 178 D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, 0x826, 0x827, 0, 0, 0, 0, 0), 179 D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, 0x8a0, 0x8a1, 0x8a2, 0, 0xb60, 0, 0), 180 D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0), 181 D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0), 182 D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0), 183 D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0), 184 D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0), 185 D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0), 186 D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0), 187 D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, 0x341, 0, 0, 0, 0, 0, 0), 188 D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, 0x64, 0, 0, 0, 0, 0, 0), 189 D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, 0x644, 0, 0, 0, 0, 0, 0), 190 D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, 0x425, 0, 0, 0, 0, 0, 0), 191 D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, 0x860, 0x861, 0, 0, 0, 0, 0), 192 D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, 0x7e0, 0x7e1, 0, 0, 0, 0, 0), 193 D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, 0x7e2, 0x7e3, 0, 0, 0, 0, 0), 194 D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, 0x7e4, 0x7e5, 0, 0, 0, 0, 0), 195 D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, 0x7e6, 0x7e7, 0, 0, 0, 0, 0), 196 D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, 0x820, 0x821, 0, 0, 0, 0, 0), 197 D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, 0x822, 0x823, 0, 0, 0, 0, 0), 198 D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, 0x982, 0x983, 0, 0, 0, 0, 0), 199 D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8), 200 D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441), 201 D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0), 202 D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461), 203 D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0), 204 D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0), 205 D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0), 206 D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0), 207 D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0), 208 D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103), 209 D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101), 210 D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0), 211 D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, 0x78c, 0x78d, 0, 0x78e, 0, 0xb04, 0xb05), 212 D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, 0x789, 0x78a, 0x78b, 0, 0xb03, 0, 0), 213 D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4), 214 D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4), 215 D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2), 216 D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4), 217 D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8), 218 D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2), 219 D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4), 220 D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0), 221 D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0), 222 D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0), 223 D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0), 224 D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0), 225 D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0), 226 D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0), 227 D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640), 228 D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, 0xba0, 0xba1, 0, 0xba2, 0, 0xbc0, 0xbc1), 229 D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, 0x323, 0x324, 0, 0, 0, 0, 0), 230 D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, 0x403, 0x404, 0, 0, 0, 0, 0), 231 D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, 0x484, 0x485, 0, 0, 0, 0, 0), 232 D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, 0xc60, 0xc61, 0, 0, 0, 0, 0), 233 D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, 0x424, 0x423, 0, 0, 0, 0, 0), 234 D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0), 235 D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0), 236 D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0), 237 D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141), 238 D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1), 239 D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2), 240 D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5), 241 D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2), 242 D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2), 243 D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0), 244 D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0), 245 D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0), 246 D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1), 247 D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0), 248 D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0), 249 D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0), 250 D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0), 251 D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182), 252 D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2), 253 D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25), 254 D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0), 255 D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0), 256 D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0), 257 D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0), 258 D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302), 259 D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2), 260 D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0), 261 D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0xa03, 0, 0xa02, 0, 0, 0), 262 D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82), 263 D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662), 264 D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0), 265 D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0), 266 D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0), 267 D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0), 268 D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0), 269 D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0), 270 D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0), 271 D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0), 272 D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0), 273 D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0), 274 D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0), 275 D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0), 276 D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0), 277 D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0), 278 D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0), 279 D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0), 280 D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0), 281 /* 282 * These are not hardware clocks, but are needed to handle the special 283 * case where we have a 'selector bit' that doesn't just change the 284 * parent for a clock, but also the gate it's supposed to use. 285 */ 286 { 287 .index = R9A06G032_UART_GROUP_012, 288 .name = "uart_group_012", 289 .type = K_BITSEL, 290 .source = 1 + R9A06G032_DIV_UART, 291 /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */ 292 .dual.sel = ((0x34 / 4) << 5) | 30, 293 .dual.group = 0, 294 }, 295 { 296 .index = R9A06G032_UART_GROUP_34567, 297 .name = "uart_group_34567", 298 .type = K_BITSEL, 299 .source = 1 + R9A06G032_DIV_P2_PG, 300 /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */ 301 .dual.sel = ((0xec / 4) << 5) | 24, 302 .dual.group = 1, 303 }, 304 D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5), 305 D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, 0x1b8, 0x1b9), 306 D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, 0x1bc, 0x1bd), 307 D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763), 308 D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767), 309 D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b), 310 D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f), 311 D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773), 312 }; 313 314 struct r9a06g032_priv { 315 struct clk_onecell_data data; 316 spinlock_t lock; /* protects concurrent access to gates */ 317 void __iomem *reg; 318 }; 319 320 static struct r9a06g032_priv *sysctrl_priv; 321 322 /* Exported helper to access the DMAMUX register */ 323 int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) 324 { 325 unsigned long flags; 326 u32 dmamux; 327 328 if (!sysctrl_priv) 329 return -EPROBE_DEFER; 330 331 spin_lock_irqsave(&sysctrl_priv->lock, flags); 332 333 dmamux = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX); 334 dmamux &= ~mask; 335 dmamux |= val & mask; 336 writel(dmamux, sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX); 337 338 spin_unlock_irqrestore(&sysctrl_priv->lock, flags); 339 340 return 0; 341 } 342 EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux); 343 344 /* register/bit pairs are encoded as an uint16_t */ 345 static void 346 clk_rdesc_set(struct r9a06g032_priv *clocks, 347 u16 one, unsigned int on) 348 { 349 u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); 350 u32 val = readl(reg); 351 352 val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f)); 353 writel(val, reg); 354 } 355 356 static int 357 clk_rdesc_get(struct r9a06g032_priv *clocks, 358 uint16_t one) 359 { 360 u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); 361 u32 val = readl(reg); 362 363 return !!(val & (1U << (one & 0x1f))); 364 } 365 366 /* 367 * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's 368 * clock gate framework as the gates on the R9A06G032 have a special enabling 369 * sequence, therefore we use this little proxy. 370 */ 371 struct r9a06g032_clk_gate { 372 struct clk_hw hw; 373 struct r9a06g032_priv *clocks; 374 u16 index; 375 376 struct r9a06g032_gate gate; 377 }; 378 379 #define to_r9a06g032_gate(_hw) container_of(_hw, struct r9a06g032_clk_gate, hw) 380 381 static int create_add_module_clock(struct of_phandle_args *clkspec, 382 struct device *dev) 383 { 384 struct clk *clk; 385 int error; 386 387 clk = of_clk_get_from_provider(clkspec); 388 if (IS_ERR(clk)) 389 return PTR_ERR(clk); 390 391 error = pm_clk_create(dev); 392 if (error) { 393 clk_put(clk); 394 return error; 395 } 396 397 error = pm_clk_add_clk(dev, clk); 398 if (error) { 399 pm_clk_destroy(dev); 400 clk_put(clk); 401 } 402 403 return error; 404 } 405 406 static int r9a06g032_attach_dev(struct generic_pm_domain *pd, 407 struct device *dev) 408 { 409 struct device_node *np = dev->of_node; 410 struct of_phandle_args clkspec; 411 int i = 0; 412 int error; 413 int index; 414 415 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++, 416 &clkspec)) { 417 if (clkspec.np != pd->dev.of_node) 418 continue; 419 420 index = clkspec.args[0]; 421 if (index < R9A06G032_CLOCK_COUNT && 422 r9a06g032_clocks[index].managed) { 423 error = create_add_module_clock(&clkspec, dev); 424 of_node_put(clkspec.np); 425 if (error) 426 return error; 427 } 428 } 429 430 return 0; 431 } 432 433 static void r9a06g032_detach_dev(struct generic_pm_domain *unused, struct device *dev) 434 { 435 if (!pm_clk_no_clocks(dev)) 436 pm_clk_destroy(dev); 437 } 438 439 static int r9a06g032_add_clk_domain(struct device *dev) 440 { 441 struct device_node *np = dev->of_node; 442 struct generic_pm_domain *pd; 443 444 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); 445 if (!pd) 446 return -ENOMEM; 447 448 pd->name = np->name; 449 pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | 450 GENPD_FLAG_ACTIVE_WAKEUP; 451 pd->attach_dev = r9a06g032_attach_dev; 452 pd->detach_dev = r9a06g032_detach_dev; 453 pm_genpd_init(pd, &pm_domain_always_on_gov, false); 454 455 of_genpd_add_provider_simple(np, pd); 456 return 0; 457 } 458 459 static void 460 r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks, 461 struct r9a06g032_gate *g, int on) 462 { 463 unsigned long flags; 464 465 WARN_ON(!g->gate); 466 467 spin_lock_irqsave(&clocks->lock, flags); 468 clk_rdesc_set(clocks, g->gate, on); 469 /* De-assert reset */ 470 if (g->reset) 471 clk_rdesc_set(clocks, g->reset, 1); 472 spin_unlock_irqrestore(&clocks->lock, flags); 473 474 /* Hardware manual recommends 5us delay after enabling clock & reset */ 475 udelay(5); 476 477 /* If the peripheral is memory mapped (i.e. an AXI slave), there is an 478 * associated SLVRDY bit in the System Controller that needs to be set 479 * so that the FlexWAY bus fabric passes on the read/write requests. 480 */ 481 if (g->ready || g->midle) { 482 spin_lock_irqsave(&clocks->lock, flags); 483 if (g->ready) 484 clk_rdesc_set(clocks, g->ready, on); 485 /* Clear 'Master Idle Request' bit */ 486 if (g->midle) 487 clk_rdesc_set(clocks, g->midle, !on); 488 spin_unlock_irqrestore(&clocks->lock, flags); 489 } 490 /* Note: We don't wait for FlexWAY Socket Connection signal */ 491 } 492 493 static int r9a06g032_clk_gate_enable(struct clk_hw *hw) 494 { 495 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw); 496 497 r9a06g032_clk_gate_set(g->clocks, &g->gate, 1); 498 return 0; 499 } 500 501 static void r9a06g032_clk_gate_disable(struct clk_hw *hw) 502 { 503 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw); 504 505 r9a06g032_clk_gate_set(g->clocks, &g->gate, 0); 506 } 507 508 static int r9a06g032_clk_gate_is_enabled(struct clk_hw *hw) 509 { 510 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw); 511 512 /* if clock is in reset, the gate might be on, and still not 'be' on */ 513 if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset)) 514 return 0; 515 516 return clk_rdesc_get(g->clocks, g->gate.gate); 517 } 518 519 static const struct clk_ops r9a06g032_clk_gate_ops = { 520 .enable = r9a06g032_clk_gate_enable, 521 .disable = r9a06g032_clk_gate_disable, 522 .is_enabled = r9a06g032_clk_gate_is_enabled, 523 }; 524 525 static struct clk * 526 r9a06g032_register_gate(struct r9a06g032_priv *clocks, 527 const char *parent_name, 528 const struct r9a06g032_clkdesc *desc) 529 { 530 struct clk *clk; 531 struct r9a06g032_clk_gate *g; 532 struct clk_init_data init = {}; 533 534 g = kzalloc(sizeof(*g), GFP_KERNEL); 535 if (!g) 536 return NULL; 537 538 init.name = desc->name; 539 init.ops = &r9a06g032_clk_gate_ops; 540 init.flags = CLK_SET_RATE_PARENT; 541 init.parent_names = parent_name ? &parent_name : NULL; 542 init.num_parents = parent_name ? 1 : 0; 543 544 g->clocks = clocks; 545 g->index = desc->index; 546 g->gate = desc->gate; 547 g->hw.init = &init; 548 549 /* 550 * important here, some clocks are already in use by the CM3, we 551 * have to assume they are not Linux's to play with and try to disable 552 * at the end of the boot! 553 */ 554 if (r9a06g032_clk_gate_is_enabled(&g->hw)) { 555 init.flags |= CLK_IS_CRITICAL; 556 pr_debug("%s was enabled, making read-only\n", desc->name); 557 } 558 559 clk = clk_register(NULL, &g->hw); 560 if (IS_ERR(clk)) { 561 kfree(g); 562 return NULL; 563 } 564 return clk; 565 } 566 567 struct r9a06g032_clk_div { 568 struct clk_hw hw; 569 struct r9a06g032_priv *clocks; 570 u16 index; 571 u16 reg; 572 u16 min, max; 573 u8 table_size; 574 u16 table[8]; /* we know there are no more than 8 */ 575 }; 576 577 #define to_r9a06g032_div(_hw) \ 578 container_of(_hw, struct r9a06g032_clk_div, hw) 579 580 static unsigned long 581 r9a06g032_div_recalc_rate(struct clk_hw *hw, 582 unsigned long parent_rate) 583 { 584 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); 585 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg); 586 u32 div = readl(reg); 587 588 if (div < clk->min) 589 div = clk->min; 590 else if (div > clk->max) 591 div = clk->max; 592 return DIV_ROUND_UP(parent_rate, div); 593 } 594 595 /* 596 * Attempts to find a value that is in range of min,max, 597 * and if a table of set dividers was specified for this 598 * register, try to find the fixed divider that is the closest 599 * to the target frequency 600 */ 601 static long 602 r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk, 603 unsigned long rate, unsigned long prate) 604 { 605 /* + 1 to cope with rates that have the remainder dropped */ 606 u32 div = DIV_ROUND_UP(prate, rate + 1); 607 int i; 608 609 if (div <= clk->min) 610 return clk->min; 611 if (div >= clk->max) 612 return clk->max; 613 614 for (i = 0; clk->table_size && i < clk->table_size - 1; i++) { 615 if (div >= clk->table[i] && div <= clk->table[i + 1]) { 616 unsigned long m = rate - 617 DIV_ROUND_UP(prate, clk->table[i]); 618 unsigned long p = 619 DIV_ROUND_UP(prate, clk->table[i + 1]) - 620 rate; 621 /* 622 * select the divider that generates 623 * the value closest to the ideal frequency 624 */ 625 div = p >= m ? clk->table[i] : clk->table[i + 1]; 626 return div; 627 } 628 } 629 return div; 630 } 631 632 static int 633 r9a06g032_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 634 { 635 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); 636 u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate); 637 638 pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__, 639 hw->clk, req->rate, req->best_parent_rate, div); 640 pr_devel(" min %d (%ld) max %d (%ld)\n", 641 clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min), 642 clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max)); 643 644 div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate); 645 /* 646 * this is a hack. Currently the serial driver asks for a clock rate 647 * that is 16 times the baud rate -- and that is wildly outside the 648 * range of the UART divider, somehow there is no provision for that 649 * case of 'let the divider as is if outside range'. 650 * The serial driver *shouldn't* play with these clocks anyway, there's 651 * several uarts attached to this divider, and changing this impacts 652 * everyone. 653 */ 654 if (clk->index == R9A06G032_DIV_UART || 655 clk->index == R9A06G032_DIV_P2_PG) { 656 pr_devel("%s div uart hack!\n", __func__); 657 req->rate = clk_get_rate(hw->clk); 658 return 0; 659 } 660 req->rate = DIV_ROUND_UP(req->best_parent_rate, div); 661 pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk, 662 req->best_parent_rate, div, req->rate); 663 return 0; 664 } 665 666 static int 667 r9a06g032_div_set_rate(struct clk_hw *hw, 668 unsigned long rate, unsigned long parent_rate) 669 { 670 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); 671 /* + 1 to cope with rates that have the remainder dropped */ 672 u32 div = DIV_ROUND_UP(parent_rate, rate + 1); 673 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg); 674 675 pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk, 676 rate, parent_rate, div); 677 678 /* 679 * Need to write the bit 31 with the divider value to 680 * latch it. Technically we should wait until it has been 681 * cleared too. 682 * TODO: Find whether this callback is sleepable, in case 683 * the hardware /does/ require some sort of spinloop here. 684 */ 685 writel(div | BIT(31), reg); 686 687 return 0; 688 } 689 690 static const struct clk_ops r9a06g032_clk_div_ops = { 691 .recalc_rate = r9a06g032_div_recalc_rate, 692 .determine_rate = r9a06g032_div_determine_rate, 693 .set_rate = r9a06g032_div_set_rate, 694 }; 695 696 static struct clk * 697 r9a06g032_register_div(struct r9a06g032_priv *clocks, 698 const char *parent_name, 699 const struct r9a06g032_clkdesc *desc) 700 { 701 struct r9a06g032_clk_div *div; 702 struct clk *clk; 703 struct clk_init_data init = {}; 704 unsigned int i; 705 706 div = kzalloc(sizeof(*div), GFP_KERNEL); 707 if (!div) 708 return NULL; 709 710 init.name = desc->name; 711 init.ops = &r9a06g032_clk_div_ops; 712 init.flags = CLK_SET_RATE_PARENT; 713 init.parent_names = parent_name ? &parent_name : NULL; 714 init.num_parents = parent_name ? 1 : 0; 715 716 div->clocks = clocks; 717 div->index = desc->index; 718 div->reg = desc->reg; 719 div->hw.init = &init; 720 div->min = desc->div_min; 721 div->max = desc->div_max; 722 /* populate (optional) divider table fixed values */ 723 for (i = 0; i < ARRAY_SIZE(div->table) && 724 i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) { 725 div->table[div->table_size++] = desc->div_table[i]; 726 } 727 728 clk = clk_register(NULL, &div->hw); 729 if (IS_ERR(clk)) { 730 kfree(div); 731 return NULL; 732 } 733 return clk; 734 } 735 736 /* 737 * This clock provider handles the case of the R9A06G032 where you have 738 * peripherals that have two potential clock source and two gates, one for 739 * each of the clock source - the used clock source (for all sub clocks) 740 * is selected by a single bit. 741 * That single bit affects all sub-clocks, and therefore needs to change the 742 * active gate (and turn the others off) and force a recalculation of the rates. 743 * 744 * This implements two clock providers, one 'bitselect' that 745 * handles the switch between both parents, and another 'dualgate' 746 * that knows which gate to poke at, depending on the parent's bit position. 747 */ 748 struct r9a06g032_clk_bitsel { 749 struct clk_hw hw; 750 struct r9a06g032_priv *clocks; 751 u16 index; 752 u16 selector; /* selector register + bit */ 753 }; 754 755 #define to_clk_bitselect(_hw) \ 756 container_of(_hw, struct r9a06g032_clk_bitsel, hw) 757 758 static u8 r9a06g032_clk_mux_get_parent(struct clk_hw *hw) 759 { 760 struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw); 761 762 return clk_rdesc_get(set->clocks, set->selector); 763 } 764 765 static int r9a06g032_clk_mux_set_parent(struct clk_hw *hw, u8 index) 766 { 767 struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw); 768 769 /* a single bit in the register selects one of two parent clocks */ 770 clk_rdesc_set(set->clocks, set->selector, !!index); 771 772 return 0; 773 } 774 775 static const struct clk_ops clk_bitselect_ops = { 776 .get_parent = r9a06g032_clk_mux_get_parent, 777 .set_parent = r9a06g032_clk_mux_set_parent, 778 }; 779 780 static struct clk * 781 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks, 782 const char *parent_name, 783 const struct r9a06g032_clkdesc *desc) 784 { 785 struct clk *clk; 786 struct r9a06g032_clk_bitsel *g; 787 struct clk_init_data init = {}; 788 const char *names[2]; 789 790 /* allocate the gate */ 791 g = kzalloc(sizeof(*g), GFP_KERNEL); 792 if (!g) 793 return NULL; 794 795 names[0] = parent_name; 796 names[1] = "clk_pll_usb"; 797 798 init.name = desc->name; 799 init.ops = &clk_bitselect_ops; 800 init.flags = CLK_SET_RATE_PARENT; 801 init.parent_names = names; 802 init.num_parents = 2; 803 804 g->clocks = clocks; 805 g->index = desc->index; 806 g->selector = desc->dual.sel; 807 g->hw.init = &init; 808 809 clk = clk_register(NULL, &g->hw); 810 if (IS_ERR(clk)) { 811 kfree(g); 812 return NULL; 813 } 814 return clk; 815 } 816 817 struct r9a06g032_clk_dualgate { 818 struct clk_hw hw; 819 struct r9a06g032_priv *clocks; 820 u16 index; 821 u16 selector; /* selector register + bit */ 822 struct r9a06g032_gate gate[2]; 823 }; 824 825 #define to_clk_dualgate(_hw) \ 826 container_of(_hw, struct r9a06g032_clk_dualgate, hw) 827 828 static int 829 r9a06g032_clk_dualgate_setenable(struct r9a06g032_clk_dualgate *g, int enable) 830 { 831 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector); 832 833 /* we always turn off the 'other' gate, regardless */ 834 r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0); 835 r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable); 836 837 return 0; 838 } 839 840 static int r9a06g032_clk_dualgate_enable(struct clk_hw *hw) 841 { 842 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw); 843 844 r9a06g032_clk_dualgate_setenable(gate, 1); 845 846 return 0; 847 } 848 849 static void r9a06g032_clk_dualgate_disable(struct clk_hw *hw) 850 { 851 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw); 852 853 r9a06g032_clk_dualgate_setenable(gate, 0); 854 } 855 856 static int r9a06g032_clk_dualgate_is_enabled(struct clk_hw *hw) 857 { 858 struct r9a06g032_clk_dualgate *g = to_clk_dualgate(hw); 859 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector); 860 861 return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate); 862 } 863 864 static const struct clk_ops r9a06g032_clk_dualgate_ops = { 865 .enable = r9a06g032_clk_dualgate_enable, 866 .disable = r9a06g032_clk_dualgate_disable, 867 .is_enabled = r9a06g032_clk_dualgate_is_enabled, 868 }; 869 870 static struct clk * 871 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks, 872 const char *parent_name, 873 const struct r9a06g032_clkdesc *desc, 874 uint16_t sel) 875 { 876 struct r9a06g032_clk_dualgate *g; 877 struct clk *clk; 878 struct clk_init_data init = {}; 879 880 /* allocate the gate */ 881 g = kzalloc(sizeof(*g), GFP_KERNEL); 882 if (!g) 883 return NULL; 884 g->clocks = clocks; 885 g->index = desc->index; 886 g->selector = sel; 887 g->gate[0].gate = desc->dual.g1; 888 g->gate[0].reset = desc->dual.r1; 889 g->gate[1].gate = desc->dual.g2; 890 g->gate[1].reset = desc->dual.r2; 891 892 init.name = desc->name; 893 init.ops = &r9a06g032_clk_dualgate_ops; 894 init.flags = CLK_SET_RATE_PARENT; 895 init.parent_names = &parent_name; 896 init.num_parents = 1; 897 g->hw.init = &init; 898 /* 899 * important here, some clocks are already in use by the CM3, we 900 * have to assume they are not Linux's to play with and try to disable 901 * at the end of the boot! 902 */ 903 if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) { 904 init.flags |= CLK_IS_CRITICAL; 905 pr_debug("%s was enabled, making read-only\n", desc->name); 906 } 907 908 clk = clk_register(NULL, &g->hw); 909 if (IS_ERR(clk)) { 910 kfree(g); 911 return NULL; 912 } 913 return clk; 914 } 915 916 static void r9a06g032_clocks_del_clk_provider(void *data) 917 { 918 of_clk_del_provider(data); 919 } 920 921 static int __init r9a06g032_clocks_probe(struct platform_device *pdev) 922 { 923 struct device *dev = &pdev->dev; 924 struct device_node *np = dev->of_node; 925 struct r9a06g032_priv *clocks; 926 struct clk **clks; 927 struct clk *mclk; 928 unsigned int i; 929 u16 uart_group_sel[2]; 930 int error; 931 932 clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL); 933 clks = devm_kcalloc(dev, R9A06G032_CLOCK_COUNT, sizeof(struct clk *), 934 GFP_KERNEL); 935 if (!clocks || !clks) 936 return -ENOMEM; 937 938 spin_lock_init(&clocks->lock); 939 940 clocks->data.clks = clks; 941 clocks->data.clk_num = R9A06G032_CLOCK_COUNT; 942 943 mclk = devm_clk_get(dev, "mclk"); 944 if (IS_ERR(mclk)) 945 return PTR_ERR(mclk); 946 947 clocks->reg = of_iomap(np, 0); 948 if (WARN_ON(!clocks->reg)) 949 return -ENOMEM; 950 for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) { 951 const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i]; 952 const char *parent_name = d->source ? 953 __clk_get_name(clocks->data.clks[d->source - 1]) : 954 __clk_get_name(mclk); 955 struct clk *clk = NULL; 956 957 switch (d->type) { 958 case K_FFC: 959 clk = clk_register_fixed_factor(NULL, d->name, 960 parent_name, 0, 961 d->mul, d->div); 962 break; 963 case K_GATE: 964 clk = r9a06g032_register_gate(clocks, parent_name, d); 965 break; 966 case K_DIV: 967 clk = r9a06g032_register_div(clocks, parent_name, d); 968 break; 969 case K_BITSEL: 970 /* keep that selector register around */ 971 uart_group_sel[d->dual.group] = d->dual.sel; 972 clk = r9a06g032_register_bitsel(clocks, parent_name, d); 973 break; 974 case K_DUALGATE: 975 clk = r9a06g032_register_dualgate(clocks, parent_name, 976 d, 977 uart_group_sel[d->dual.group]); 978 break; 979 } 980 clocks->data.clks[d->index] = clk; 981 } 982 error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data); 983 if (error) 984 return error; 985 986 error = devm_add_action_or_reset(dev, 987 r9a06g032_clocks_del_clk_provider, np); 988 if (error) 989 return error; 990 991 error = r9a06g032_add_clk_domain(dev); 992 if (error) 993 return error; 994 995 sysctrl_priv = clocks; 996 997 error = of_platform_populate(np, NULL, NULL, dev); 998 if (error) 999 dev_err(dev, "Failed to populate children (%d)\n", error); 1000 1001 return 0; 1002 } 1003 1004 static const struct of_device_id r9a06g032_match[] = { 1005 { .compatible = "renesas,r9a06g032-sysctrl" }, 1006 { } 1007 }; 1008 1009 static struct platform_driver r9a06g032_clock_driver = { 1010 .driver = { 1011 .name = "renesas,r9a06g032-sysctrl", 1012 .of_match_table = r9a06g032_match, 1013 }, 1014 }; 1015 1016 static int __init r9a06g032_clocks_init(void) 1017 { 1018 return platform_driver_probe(&r9a06g032_clock_driver, 1019 r9a06g032_clocks_probe); 1020 } 1021 1022 subsys_initcall(r9a06g032_clocks_init); 1023