1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
4  *
5  * Copyright (C) 2022 Renesas Electronics Corp.
6  *
7  * Based on r8a779f0-cpg-mssr.c
8  */
9 
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/device.h>
14 #include <linux/err.h>
15 #include <linux/kernel.h>
16 #include <linux/soc/renesas/rcar-rst.h>
17 
18 #include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
19 
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen4-cpg.h"
22 
23 enum clk_ids {
24 	/* Core Clock Outputs exported to DT */
25 	LAST_DT_CORE_CLK = R8A779G0_CLK_R,
26 
27 	/* External Input Clocks */
28 	CLK_EXTAL,
29 	CLK_EXTALR,
30 
31 	/* Internal Core Clocks */
32 	CLK_MAIN,
33 	CLK_PLL1,
34 	CLK_PLL2,
35 	CLK_PLL3,
36 	CLK_PLL4,
37 	CLK_PLL5,
38 	CLK_PLL6,
39 	CLK_PLL1_DIV2,
40 	CLK_PLL2_DIV2,
41 	CLK_PLL3_DIV2,
42 	CLK_PLL4_DIV2,
43 	CLK_PLL5_DIV2,
44 	CLK_PLL5_DIV4,
45 	CLK_PLL6_DIV2,
46 	CLK_S0,
47 	CLK_S0_VIO,
48 	CLK_S0_VC,
49 	CLK_S0_HSC,
50 	CLK_SASYNCPER,
51 	CLK_SV_VIP,
52 	CLK_SV_IR,
53 	CLK_SDSRC,
54 	CLK_RPCSRC,
55 	CLK_VIO,
56 	CLK_VC,
57 	CLK_OCO,
58 
59 	/* Module Clocks */
60 	MOD_CLK_BASE
61 };
62 
63 static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
64 	/* External Clock Inputs */
65 	DEF_INPUT("extal",	CLK_EXTAL),
66 	DEF_INPUT("extalr",	CLK_EXTALR),
67 
68 	/* Internal Core Clocks */
69 	DEF_BASE(".main", CLK_MAIN,	CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
70 	DEF_BASE(".pll1", CLK_PLL1,	CLK_TYPE_GEN4_PLL1, CLK_MAIN),
71 	DEF_BASE(".pll2", CLK_PLL2,	CLK_TYPE_GEN4_PLL2, CLK_MAIN),
72 	DEF_BASE(".pll3", CLK_PLL3,	CLK_TYPE_GEN4_PLL3, CLK_MAIN),
73 	DEF_BASE(".pll4", CLK_PLL4,	CLK_TYPE_GEN4_PLL4, CLK_MAIN),
74 	DEF_BASE(".pll5", CLK_PLL5,	CLK_TYPE_GEN4_PLL5, CLK_MAIN),
75 	DEF_BASE(".pll6", CLK_PLL6,	CLK_TYPE_GEN4_PLL6, CLK_MAIN),
76 
77 	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2,	CLK_PLL1,	2, 1),
78 	DEF_FIXED(".pll2_div2",	CLK_PLL2_DIV2,	CLK_PLL2,	2, 1),
79 	DEF_FIXED(".pll3_div2",	CLK_PLL3_DIV2,	CLK_PLL3,	2, 1),
80 	DEF_FIXED(".pll4_div2",	CLK_PLL4_DIV2,	CLK_PLL4,	2, 1),
81 	DEF_FIXED(".pll5_div2",	CLK_PLL5_DIV2,	CLK_PLL5,	2, 1),
82 	DEF_FIXED(".pll5_div4",	CLK_PLL5_DIV4,	CLK_PLL5_DIV2,	2, 1),
83 	DEF_FIXED(".pll6_div2",	CLK_PLL6_DIV2,	CLK_PLL6,	2, 1),
84 	DEF_FIXED(".s0",	CLK_S0,		CLK_PLL1_DIV2,	2, 1),
85 	DEF_FIXED(".s0_vio",	CLK_S0_VIO,	CLK_PLL1_DIV2,	2, 1),
86 	DEF_FIXED(".s0_vc",	CLK_S0_VC,	CLK_PLL1_DIV2,	2, 1),
87 	DEF_FIXED(".s0_hsc",	CLK_S0_HSC,	CLK_PLL1_DIV2,	2, 1),
88 	DEF_FIXED(".sasyncper",	CLK_SASYNCPER,	CLK_PLL5_DIV4,	3, 1),
89 	DEF_FIXED(".sv_vip",	CLK_SV_VIP,	CLK_PLL1,	5, 1),
90 	DEF_FIXED(".sv_ir",	CLK_SV_IR,	CLK_PLL1,	5, 1),
91 	DEF_BASE(".sdsrc",	CLK_SDSRC,	CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
92 	DEF_RATE(".oco",	CLK_OCO,	32768),
93 
94 	DEF_BASE(".rpcsrc",	CLK_RPCSRC,		CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
95 	DEF_FIXED(".vio",	CLK_VIO,	CLK_PLL5_DIV2,	3, 1),
96 	DEF_FIXED(".vc",	CLK_VC,		CLK_PLL5_DIV2,	3, 1),
97 
98 	/* Core Clock Outputs */
99 	DEF_FIXED("s0d2",	R8A779G0_CLK_S0D2,	CLK_S0,		2, 1),
100 	DEF_FIXED("s0d3",	R8A779G0_CLK_S0D3,	CLK_S0,		3, 1),
101 	DEF_FIXED("s0d4",	R8A779G0_CLK_S0D4,	CLK_S0,		4, 1),
102 	DEF_FIXED("cl16m",	R8A779G0_CLK_CL16M,	CLK_S0,		48, 1),
103 	DEF_FIXED("s0d1_vio",	R8A779G0_CLK_S0D1_VIO,	CLK_S0_VIO,	1, 1),
104 	DEF_FIXED("s0d2_vio",	R8A779G0_CLK_S0D2_VIO,	CLK_S0_VIO,	2, 1),
105 	DEF_FIXED("s0d4_vio",	R8A779G0_CLK_S0D4_VIO,	CLK_S0_VIO,	4, 1),
106 	DEF_FIXED("s0d8_vio",	R8A779G0_CLK_S0D8_VIO,	CLK_S0_VIO,	8, 1),
107 	DEF_FIXED("s0d1_vc",	R8A779G0_CLK_S0D1_VC,	CLK_S0_VC,	1, 1),
108 	DEF_FIXED("s0d2_vc",	R8A779G0_CLK_S0D2_VC,	CLK_S0_VC,	2, 1),
109 	DEF_FIXED("s0d4_vc",	R8A779G0_CLK_S0D4_VC,	CLK_S0_VC,	4, 1),
110 	DEF_FIXED("s0d2_mm",	R8A779G0_CLK_S0D2_MM,	CLK_S0,		2, 1),
111 	DEF_FIXED("s0d4_mm",	R8A779G0_CLK_S0D4_MM,	CLK_S0,		4, 1),
112 	DEF_FIXED("cl16m_mm",	R8A779G0_CLK_CL16M_MM,	CLK_S0,		48, 1),
113 	DEF_FIXED("s0d2_u3dg",	R8A779G0_CLK_S0D2_U3DG,	CLK_S0,		2, 1),
114 	DEF_FIXED("s0d4_u3dg",	R8A779G0_CLK_S0D4_U3DG,	CLK_S0,		4, 1),
115 	DEF_FIXED("s0d2_rt",	R8A779G0_CLK_S0D2_RT,	CLK_S0,		2, 1),
116 	DEF_FIXED("s0d3_rt",	R8A779G0_CLK_S0D3_RT,	CLK_S0,		3, 1),
117 	DEF_FIXED("s0d4_rt",	R8A779G0_CLK_S0D4_RT,	CLK_S0,		4, 1),
118 	DEF_FIXED("s0d6_rt",	R8A779G0_CLK_S0D6_RT,	CLK_S0,		6, 1),
119 	DEF_FIXED("s0d24_rt",	R8A779G0_CLK_S0D24_RT,	CLK_S0,		24, 1),
120 	DEF_FIXED("cl16m_rt",	R8A779G0_CLK_CL16M_RT,	CLK_S0,		48, 1),
121 	DEF_FIXED("s0d2_per",	R8A779G0_CLK_S0D2_PER,	CLK_S0,		2, 1),
122 	DEF_FIXED("s0d3_per",	R8A779G0_CLK_S0D3_PER,	CLK_S0,		3, 1),
123 	DEF_FIXED("s0d4_per",	R8A779G0_CLK_S0D4_PER,	CLK_S0,		4, 1),
124 	DEF_FIXED("s0d6_per",	R8A779G0_CLK_S0D6_PER,	CLK_S0,		6, 1),
125 	DEF_FIXED("s0d12_per",	R8A779G0_CLK_S0D12_PER,	CLK_S0,		12, 1),
126 	DEF_FIXED("s0d24_per",	R8A779G0_CLK_S0D24_PER,	CLK_S0,		24, 1),
127 	DEF_FIXED("cl16m_per",	R8A779G0_CLK_CL16M_PER,	CLK_S0,		48, 1),
128 	DEF_FIXED("s0d1_hsc",	R8A779G0_CLK_S0D1_HSC,	CLK_S0_HSC,	1, 1),
129 	DEF_FIXED("s0d2_hsc",	R8A779G0_CLK_S0D2_HSC,	CLK_S0_HSC,	2, 1),
130 	DEF_FIXED("s0d4_hsc",	R8A779G0_CLK_S0D4_HSC,	CLK_S0_HSC,	4, 1),
131 	DEF_FIXED("cl16m_hsc",	R8A779G0_CLK_CL16M_HSC,	CLK_S0_HSC,	48, 1),
132 	DEF_FIXED("s0d2_cc",	R8A779G0_CLK_S0D2_CC,	CLK_S0,		2, 1),
133 	DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
134 	DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
135 	DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
136 	DEF_FIXED("svd1_ir",	R8A779G0_CLK_SVD1_IR,	CLK_SV_IR,	1, 1),
137 	DEF_FIXED("svd2_ir",	R8A779G0_CLK_SVD2_IR,	CLK_SV_IR,	2, 1),
138 	DEF_FIXED("svd1_vip",	R8A779G0_CLK_SVD1_VIP,	CLK_SV_VIP,	1, 1),
139 	DEF_FIXED("svd2_vip",	R8A779G0_CLK_SVD2_VIP,	CLK_SV_VIP,	2, 1),
140 	DEF_FIXED("cbfusa",	R8A779G0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),
141 	DEF_FIXED("cpex",	R8A779G0_CLK_CPEX,	CLK_EXTAL,	2, 1),
142 	DEF_FIXED("viobus",	R8A779G0_CLK_VIOBUS,	CLK_VIO,	1, 1),
143 	DEF_FIXED("viobusd2",	R8A779G0_CLK_VIOBUSD2,	CLK_VIO,	2, 1),
144 	DEF_FIXED("vcbus",	R8A779G0_CLK_VCBUS,	CLK_VC,		1, 1),
145 	DEF_FIXED("vcbusd2",	R8A779G0_CLK_VCBUSD2,	CLK_VC,		2, 1),
146 
147 	DEF_GEN4_SD("sd0",	R8A779G0_CLK_SD0,	CLK_SDSRC,	0x870),
148 	DEF_DIV6P1("mso",	R8A779G0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),
149 
150 	DEF_BASE("rpc",		R8A779G0_CLK_RPC,	CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
151 	DEF_BASE("rpcd2",	R8A779G0_CLK_RPCD2,	CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
152 
153 	DEF_GEN4_OSC("osc",	R8A779G0_CLK_OSC,	CLK_EXTAL,	8),
154 	DEF_GEN4_MDSEL("r",	R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
155 };
156 
157 static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
158 	DEF_MOD("avb0",		211,	R8A779G0_CLK_S0D4_HSC),
159 	DEF_MOD("avb1",		212,	R8A779G0_CLK_S0D4_HSC),
160 	DEF_MOD("avb2",		213,	R8A779G0_CLK_S0D4_HSC),
161 	DEF_MOD("hscif0",	514,	R8A779G0_CLK_SASYNCPERD1),
162 	DEF_MOD("hscif1",	515,	R8A779G0_CLK_SASYNCPERD1),
163 	DEF_MOD("hscif2",	516,	R8A779G0_CLK_SASYNCPERD1),
164 	DEF_MOD("hscif3",	517,	R8A779G0_CLK_SASYNCPERD1),
165 	DEF_MOD("i2c0",		518,	R8A779G0_CLK_S0D6_PER),
166 	DEF_MOD("i2c1",		519,	R8A779G0_CLK_S0D6_PER),
167 	DEF_MOD("i2c2",		520,	R8A779G0_CLK_S0D6_PER),
168 	DEF_MOD("i2c3",		521,	R8A779G0_CLK_S0D6_PER),
169 	DEF_MOD("i2c4",		522,	R8A779G0_CLK_S0D6_PER),
170 	DEF_MOD("i2c5",		523,	R8A779G0_CLK_S0D6_PER),
171 	DEF_MOD("wdt1:wdt0",	907,	R8A779G0_CLK_R),
172 	DEF_MOD("pfc0",		915,	R8A779G0_CLK_CL16M),
173 	DEF_MOD("pfc1",		916,	R8A779G0_CLK_CL16M),
174 	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CL16M),
175 	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CL16M),
176 };
177 
178 /*
179  * CPG Clock Data
180  */
181 /*
182  *   MD	 EXTAL		PLL1	PLL2	PLL3	PLL4	PLL5	PLL6	OSC
183  * 14 13 (MHz)
184  * ------------------------------------------------------------------------
185  * 0  0	 16.66 / 1	x192	x204	x192	x144	x192	x168	/15
186  * 0  1	 20    / 1	x160	x170	x160	x120	x160	x140	/19
187  * 1  0	 Prohibited setting
188  * 1  1	 33.33 / 2	x192	x204	x192	x144	x192	x168	/38
189  */
190 #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
191 					 (((md) & BIT(13)) >> 13))
192 
193 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
194 	/* EXTAL div	PLL1 mult/div	PLL2 mult/div	PLL3 mult/div	PLL4 mult/div	PLL5 mult/div	PLL6 mult/div	OSC prediv */
195 	{ 1,		192,	1,	204,	1,	192,	1,	144,	1,	192,	1,	168,	1,	15,	},
196 	{ 1,		160,	1,	170,	1,	160,	1,	120,	1,	160,	1,	140,	1,	19,	},
197 	{ 0,		0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	},
198 	{ 2,		192,	1,	204,	1,	192,	1,	144,	1,	192,	1,	168,	1,	38,	},
199 };
200 
201 static int __init r8a779g0_cpg_mssr_init(struct device *dev)
202 {
203 	const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
204 	u32 cpg_mode;
205 	int error;
206 
207 	error = rcar_rst_read_mode_pins(&cpg_mode);
208 	if (error)
209 		return error;
210 
211 	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
212 	if (!cpg_pll_config->extal_div) {
213 		dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
214 		return -EINVAL;
215 	}
216 
217 	return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
218 }
219 
220 const struct cpg_mssr_info r8a779g0_cpg_mssr_info __initconst = {
221 	/* Core Clocks */
222 	.core_clks = r8a779g0_core_clks,
223 	.num_core_clks = ARRAY_SIZE(r8a779g0_core_clks),
224 	.last_dt_core_clk = LAST_DT_CORE_CLK,
225 	.num_total_core_clks = MOD_CLK_BASE,
226 
227 	/* Module Clocks */
228 	.mod_clks = r8a779g0_mod_clks,
229 	.num_mod_clks = ARRAY_SIZE(r8a779g0_mod_clks),
230 	.num_hw_mod_clks = 30 * 32,
231 
232 	/* Callbacks */
233 	.init = r8a779g0_cpg_mssr_init,
234 	.cpg_clk_register = rcar_gen4_cpg_clk_register,
235 
236 	.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
237 };
238