1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 * 7 * Based on r8a7795-cpg-mssr.c 8 * 9 * Copyright (C) 2015 Glider bvba 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/bug.h> 14 #include <linux/bitfield.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/device.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/pm.h> 23 #include <linux/slab.h> 24 #include <linux/soc/renesas/rcar-rst.h> 25 26 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> 27 28 #include "rcar-cpg-lib.h" 29 #include "renesas-cpg-mssr.h" 30 31 enum rcar_r8a779a0_clk_types { 32 CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM, 33 CLK_TYPE_R8A779A0_PLL1, 34 CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ 35 CLK_TYPE_R8A779A0_PLL5, 36 CLK_TYPE_R8A779A0_Z, 37 CLK_TYPE_R8A779A0_SD, 38 CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */ 39 CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */ 40 }; 41 42 struct rcar_r8a779a0_cpg_pll_config { 43 u8 extal_div; 44 u8 pll1_mult; 45 u8 pll1_div; 46 u8 pll5_mult; 47 u8 pll5_div; 48 u8 osc_prediv; 49 }; 50 51 enum clk_ids { 52 /* Core Clock Outputs exported to DT */ 53 LAST_DT_CORE_CLK = R8A779A0_CLK_OSC, 54 55 /* External Input Clocks */ 56 CLK_EXTAL, 57 CLK_EXTALR, 58 59 /* Internal Core Clocks */ 60 CLK_MAIN, 61 CLK_PLL1, 62 CLK_PLL20, 63 CLK_PLL21, 64 CLK_PLL30, 65 CLK_PLL31, 66 CLK_PLL5, 67 CLK_PLL1_DIV2, 68 CLK_PLL20_DIV2, 69 CLK_PLL21_DIV2, 70 CLK_PLL30_DIV2, 71 CLK_PLL31_DIV2, 72 CLK_PLL5_DIV2, 73 CLK_PLL5_DIV4, 74 CLK_S1, 75 CLK_S3, 76 CLK_SDSRC, 77 CLK_RPCSRC, 78 CLK_OCO, 79 80 /* Module Clocks */ 81 MOD_CLK_BASE 82 }; 83 84 #define DEF_PLL(_name, _id, _offset) \ 85 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \ 86 .offset = _offset) 87 88 #define DEF_Z(_name, _id, _parent, _div, _offset) \ 89 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_Z, _parent, .div = _div, \ 90 .offset = _offset) 91 92 #define DEF_SD(_name, _id, _parent, _offset) \ 93 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset) 94 95 #define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 96 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \ 97 (_parent0) << 16 | (_parent1), \ 98 .div = (_div0) << 16 | (_div1), .offset = _md) 99 100 #define DEF_OSC(_name, _id, _parent, _div) \ 101 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div) 102 103 static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 104 /* External Clock Inputs */ 105 DEF_INPUT("extal", CLK_EXTAL), 106 DEF_INPUT("extalr", CLK_EXTALR), 107 108 /* Internal Core Clocks */ 109 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL), 110 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN), 111 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN), 112 DEF_PLL(".pll20", CLK_PLL20, 0x0834), 113 DEF_PLL(".pll21", CLK_PLL21, 0x0838), 114 DEF_PLL(".pll30", CLK_PLL30, 0x083c), 115 DEF_PLL(".pll31", CLK_PLL31, 0x0840), 116 117 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 118 DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1), 119 DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1), 120 DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1), 121 DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1), 122 DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), 123 DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), 124 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1), 125 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1), 126 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1), 127 DEF_RATE(".oco", CLK_OCO, 32768), 128 129 /* Core Clock Outputs */ 130 DEF_Z("z0", R8A779A0_CLK_Z0, CLK_PLL20, 2, 0), 131 DEF_Z("z1", R8A779A0_CLK_Z1, CLK_PLL21, 2, 8), 132 DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1), 133 DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1), 134 DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1), 135 DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1), 136 DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1), 137 DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1), 138 DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1), 139 DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1), 140 DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1), 141 DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1), 142 DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1), 143 DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1), 144 DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1), 145 DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1), 146 DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1), 147 DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1), 148 DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1), 149 DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1), 150 DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), 151 DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1), 152 DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), 153 DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1), 154 155 DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870), 156 157 DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), 158 DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), 159 DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), 160 DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884), 161 162 DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), 163 DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), 164 }; 165 166 static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 167 DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2), 168 DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2), 169 DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2), 170 DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2), 171 DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2), 172 DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2), 173 DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0), 174 DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0), 175 DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0), 176 DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0), 177 DEF_MOD("du", 411, R8A779A0_CLK_S3D1), 178 DEF_MOD("dsi0", 415, R8A779A0_CLK_DSI), 179 DEF_MOD("dsi1", 416, R8A779A0_CLK_DSI), 180 DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1), 181 DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1), 182 DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2), 183 DEF_MOD("hscif1", 515, R8A779A0_CLK_S1D2), 184 DEF_MOD("hscif2", 516, R8A779A0_CLK_S1D2), 185 DEF_MOD("hscif3", 517, R8A779A0_CLK_S1D2), 186 DEF_MOD("i2c0", 518, R8A779A0_CLK_S1D4), 187 DEF_MOD("i2c1", 519, R8A779A0_CLK_S1D4), 188 DEF_MOD("i2c2", 520, R8A779A0_CLK_S1D4), 189 DEF_MOD("i2c3", 521, R8A779A0_CLK_S1D4), 190 DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4), 191 DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4), 192 DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4), 193 DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1), 194 DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1), 195 DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1), 196 DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1), 197 DEF_MOD("msi0", 618, R8A779A0_CLK_MSO), 198 DEF_MOD("msi1", 619, R8A779A0_CLK_MSO), 199 DEF_MOD("msi2", 620, R8A779A0_CLK_MSO), 200 DEF_MOD("msi3", 621, R8A779A0_CLK_MSO), 201 DEF_MOD("msi4", 622, R8A779A0_CLK_MSO), 202 DEF_MOD("msi5", 623, R8A779A0_CLK_MSO), 203 DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), 204 DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), 205 DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8), 206 DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8), 207 DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0), 208 DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2), 209 DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2), 210 DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK), 211 DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4), 212 DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4), 213 DEF_MOD("tmu3", 716, R8A779A0_CLK_S1D4), 214 DEF_MOD("tmu4", 717, R8A779A0_CLK_S1D4), 215 DEF_MOD("tpu0", 718, R8A779A0_CLK_S1D8), 216 DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1), 217 DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1), 218 DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1), 219 DEF_MOD("vin03", 801, R8A779A0_CLK_S1D1), 220 DEF_MOD("vin04", 802, R8A779A0_CLK_S1D1), 221 DEF_MOD("vin05", 803, R8A779A0_CLK_S1D1), 222 DEF_MOD("vin06", 804, R8A779A0_CLK_S1D1), 223 DEF_MOD("vin07", 805, R8A779A0_CLK_S1D1), 224 DEF_MOD("vin10", 806, R8A779A0_CLK_S1D1), 225 DEF_MOD("vin11", 807, R8A779A0_CLK_S1D1), 226 DEF_MOD("vin12", 808, R8A779A0_CLK_S1D1), 227 DEF_MOD("vin13", 809, R8A779A0_CLK_S1D1), 228 DEF_MOD("vin14", 810, R8A779A0_CLK_S1D1), 229 DEF_MOD("vin15", 811, R8A779A0_CLK_S1D1), 230 DEF_MOD("vin16", 812, R8A779A0_CLK_S1D1), 231 DEF_MOD("vin17", 813, R8A779A0_CLK_S1D1), 232 DEF_MOD("vin20", 814, R8A779A0_CLK_S1D1), 233 DEF_MOD("vin21", 815, R8A779A0_CLK_S1D1), 234 DEF_MOD("vin22", 816, R8A779A0_CLK_S1D1), 235 DEF_MOD("vin23", 817, R8A779A0_CLK_S1D1), 236 DEF_MOD("vin24", 818, R8A779A0_CLK_S1D1), 237 DEF_MOD("vin25", 819, R8A779A0_CLK_S1D1), 238 DEF_MOD("vin26", 820, R8A779A0_CLK_S1D1), 239 DEF_MOD("vin27", 821, R8A779A0_CLK_S1D1), 240 DEF_MOD("vin30", 822, R8A779A0_CLK_S1D1), 241 DEF_MOD("vin31", 823, R8A779A0_CLK_S1D1), 242 DEF_MOD("vin32", 824, R8A779A0_CLK_S1D1), 243 DEF_MOD("vin33", 825, R8A779A0_CLK_S1D1), 244 DEF_MOD("vin34", 826, R8A779A0_CLK_S1D1), 245 DEF_MOD("vin35", 827, R8A779A0_CLK_S1D1), 246 DEF_MOD("vin36", 828, R8A779A0_CLK_S1D1), 247 DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1), 248 DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1), 249 DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1), 250 DEF_MOD("rwdt", 907, R8A779A0_CLK_R), 251 DEF_MOD("cmt0", 910, R8A779A0_CLK_R), 252 DEF_MOD("cmt1", 911, R8A779A0_CLK_R), 253 DEF_MOD("cmt2", 912, R8A779A0_CLK_R), 254 DEF_MOD("cmt3", 913, R8A779A0_CLK_R), 255 DEF_MOD("pfc0", 915, R8A779A0_CLK_CP), 256 DEF_MOD("pfc1", 916, R8A779A0_CLK_CP), 257 DEF_MOD("pfc2", 917, R8A779A0_CLK_CP), 258 DEF_MOD("pfc3", 918, R8A779A0_CLK_CP), 259 DEF_MOD("tsc", 919, R8A779A0_CLK_CL16MCK), 260 DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1), 261 DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1), 262 DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1), 263 DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1), 264 }; 265 266 static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata; 267 static unsigned int cpg_clk_extalr __initdata; 268 static u32 cpg_mode __initdata; 269 270 /* 271 * Z0 Clock & Z1 Clock 272 */ 273 #define CPG_FRQCRB 0x00000804 274 #define CPG_FRQCRB_KICK BIT(31) 275 #define CPG_FRQCRC 0x00000808 276 277 struct cpg_z_clk { 278 struct clk_hw hw; 279 void __iomem *reg; 280 void __iomem *kick_reg; 281 unsigned long max_rate; /* Maximum rate for normal mode */ 282 unsigned int fixed_div; 283 u32 mask; 284 }; 285 286 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) 287 288 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, 289 unsigned long parent_rate) 290 { 291 struct cpg_z_clk *zclk = to_z_clk(hw); 292 unsigned int mult; 293 u32 val; 294 295 val = readl(zclk->reg) & zclk->mask; 296 mult = 32 - (val >> __ffs(zclk->mask)); 297 298 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 299 32 * zclk->fixed_div); 300 } 301 302 static int cpg_z_clk_determine_rate(struct clk_hw *hw, 303 struct clk_rate_request *req) 304 { 305 struct cpg_z_clk *zclk = to_z_clk(hw); 306 unsigned int min_mult, max_mult, mult; 307 unsigned long rate, prate; 308 309 rate = min(req->rate, req->max_rate); 310 if (rate <= zclk->max_rate) { 311 /* Set parent rate to initial value for normal modes */ 312 prate = zclk->max_rate; 313 } else { 314 /* Set increased parent rate for boost modes */ 315 prate = rate; 316 } 317 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 318 prate * zclk->fixed_div); 319 320 prate = req->best_parent_rate / zclk->fixed_div; 321 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); 322 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); 323 if (max_mult < min_mult) 324 return -EINVAL; 325 326 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); 327 mult = clamp(mult, min_mult, max_mult); 328 329 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); 330 return 0; 331 } 332 333 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, 334 unsigned long parent_rate) 335 { 336 struct cpg_z_clk *zclk = to_z_clk(hw); 337 unsigned int mult; 338 unsigned int i; 339 340 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, 341 parent_rate); 342 mult = clamp(mult, 1U, 32U); 343 344 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) 345 return -EBUSY; 346 347 cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); 348 349 /* 350 * Set KICK bit in FRQCRB to update hardware setting and wait for 351 * clock change completion. 352 */ 353 cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK); 354 355 /* 356 * Note: There is no HW information about the worst case latency. 357 * 358 * Using experimental measurements, it seems that no more than 359 * ~10 iterations are needed, independently of the CPU rate. 360 * Since this value might be dependent on external xtal rate, pll1 361 * rate or even the other emulation clocks rate, use 1000 as a 362 * "super" safe value. 363 */ 364 for (i = 1000; i; i--) { 365 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) 366 return 0; 367 368 cpu_relax(); 369 } 370 371 return -ETIMEDOUT; 372 } 373 374 static const struct clk_ops cpg_z_clk_ops = { 375 .recalc_rate = cpg_z_clk_recalc_rate, 376 .determine_rate = cpg_z_clk_determine_rate, 377 .set_rate = cpg_z_clk_set_rate, 378 }; 379 380 static struct clk * __init cpg_z_clk_register(const char *name, 381 const char *parent_name, 382 void __iomem *reg, 383 unsigned int div, 384 unsigned int offset) 385 { 386 struct clk_init_data init = {}; 387 struct cpg_z_clk *zclk; 388 struct clk *clk; 389 390 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); 391 if (!zclk) 392 return ERR_PTR(-ENOMEM); 393 394 init.name = name; 395 init.ops = &cpg_z_clk_ops; 396 init.flags = CLK_SET_RATE_PARENT; 397 init.parent_names = &parent_name; 398 init.num_parents = 1; 399 400 zclk->reg = reg + CPG_FRQCRC; 401 zclk->kick_reg = reg + CPG_FRQCRB; 402 zclk->hw.init = &init; 403 zclk->mask = GENMASK(offset + 4, offset); 404 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ 405 406 clk = clk_register(NULL, &zclk->hw); 407 if (IS_ERR(clk)) { 408 kfree(zclk); 409 return clk; 410 } 411 412 zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) / 413 zclk->fixed_div; 414 return clk; 415 } 416 417 static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, 418 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 419 struct clk **clks, void __iomem *base, 420 struct raw_notifier_head *notifiers) 421 { 422 const struct clk *parent; 423 unsigned int mult = 1; 424 unsigned int div = 1; 425 u32 value; 426 427 parent = clks[core->parent & 0xffff]; /* some types use high bits */ 428 if (IS_ERR(parent)) 429 return ERR_CAST(parent); 430 431 switch (core->type) { 432 case CLK_TYPE_R8A779A0_MAIN: 433 div = cpg_pll_config->extal_div; 434 break; 435 436 case CLK_TYPE_R8A779A0_PLL1: 437 mult = cpg_pll_config->pll1_mult; 438 div = cpg_pll_config->pll1_div; 439 break; 440 441 case CLK_TYPE_R8A779A0_PLL2X_3X: 442 value = readl(base + core->offset); 443 mult = (((value >> 24) & 0x7f) + 1) * 2; 444 break; 445 446 case CLK_TYPE_R8A779A0_PLL5: 447 mult = cpg_pll_config->pll5_mult; 448 div = cpg_pll_config->pll5_div; 449 break; 450 451 case CLK_TYPE_R8A779A0_Z: 452 return cpg_z_clk_register(core->name, __clk_get_name(parent), 453 base, core->div, core->offset); 454 455 case CLK_TYPE_R8A779A0_SD: 456 return cpg_sd_clk_register(core->name, base, core->offset, 457 __clk_get_name(parent), notifiers, 458 false); 459 break; 460 461 case CLK_TYPE_R8A779A0_MDSEL: 462 /* 463 * Clock selectable between two parents and two fixed dividers 464 * using a mode pin 465 */ 466 if (cpg_mode & BIT(core->offset)) { 467 div = core->div & 0xffff; 468 } else { 469 parent = clks[core->parent >> 16]; 470 if (IS_ERR(parent)) 471 return ERR_CAST(parent); 472 div = core->div >> 16; 473 } 474 mult = 1; 475 break; 476 477 case CLK_TYPE_R8A779A0_OSC: 478 /* 479 * Clock combining OSC EXTAL predivider and a fixed divider 480 */ 481 div = cpg_pll_config->osc_prediv * core->div; 482 break; 483 484 default: 485 return ERR_PTR(-EINVAL); 486 } 487 488 return clk_register_fixed_factor(NULL, core->name, 489 __clk_get_name(parent), 0, mult, div); 490 } 491 492 static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { 493 MOD_CLK_ID(907), /* RWDT */ 494 }; 495 496 /* 497 * CPG Clock Data 498 */ 499 /* 500 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC 501 * 14 13 (MHz) 21 31 502 * -------------------------------------------------------- 503 * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 504 * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 505 * 1 0 Prohibited setting 506 * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32 507 */ 508 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 509 (((md) & BIT(13)) >> 13)) 510 511 static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = { 512 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */ 513 { 1, 128, 1, 192, 1, 16, }, 514 { 1, 106, 1, 160, 1, 19, }, 515 { 0, 0, 0, 0, 0, 0, }, 516 { 2, 128, 1, 192, 1, 32, }, 517 }; 518 519 static int __init r8a779a0_cpg_mssr_init(struct device *dev) 520 { 521 int error; 522 523 error = rcar_rst_read_mode_pins(&cpg_mode); 524 if (error) 525 return error; 526 527 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 528 cpg_clk_extalr = CLK_EXTALR; 529 spin_lock_init(&cpg_lock); 530 531 return 0; 532 } 533 534 const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { 535 /* Core Clocks */ 536 .core_clks = r8a779a0_core_clks, 537 .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks), 538 .last_dt_core_clk = LAST_DT_CORE_CLK, 539 .num_total_core_clks = MOD_CLK_BASE, 540 541 /* Module Clocks */ 542 .mod_clks = r8a779a0_mod_clks, 543 .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks), 544 .num_hw_mod_clks = 15 * 32, 545 546 /* Critical Module Clocks */ 547 .crit_mod_clks = r8a779a0_crit_mod_clks, 548 .num_crit_mod_clks = ARRAY_SIZE(r8a779a0_crit_mod_clks), 549 550 /* Callbacks */ 551 .init = r8a779a0_cpg_mssr_init, 552 .cpg_clk_register = rcar_r8a779a0_cpg_clk_register, 553 554 .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, 555 }; 556