1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 * 7 * Based on r8a7795-cpg-mssr.c 8 * 9 * Copyright (C) 2015 Glider bvba 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/bug.h> 14 #include <linux/bitfield.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/device.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/pm.h> 23 #include <linux/slab.h> 24 #include <linux/soc/renesas/rcar-rst.h> 25 26 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> 27 28 #include "rcar-cpg-lib.h" 29 #include "renesas-cpg-mssr.h" 30 31 enum rcar_r8a779a0_clk_types { 32 CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM, 33 CLK_TYPE_R8A779A0_PLL1, 34 CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ 35 CLK_TYPE_R8A779A0_PLL5, 36 CLK_TYPE_R8A779A0_Z, 37 CLK_TYPE_R8A779A0_SD, 38 CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */ 39 CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */ 40 CLK_TYPE_R8A779A0_RPCSRC, 41 CLK_TYPE_R8A779A0_RPC, 42 CLK_TYPE_R8A779A0_RPCD2, 43 }; 44 45 struct rcar_r8a779a0_cpg_pll_config { 46 u8 extal_div; 47 u8 pll1_mult; 48 u8 pll1_div; 49 u8 pll5_mult; 50 u8 pll5_div; 51 u8 osc_prediv; 52 }; 53 54 enum clk_ids { 55 /* Core Clock Outputs exported to DT */ 56 LAST_DT_CORE_CLK = R8A779A0_CLK_OSC, 57 58 /* External Input Clocks */ 59 CLK_EXTAL, 60 CLK_EXTALR, 61 62 /* Internal Core Clocks */ 63 CLK_MAIN, 64 CLK_PLL1, 65 CLK_PLL20, 66 CLK_PLL21, 67 CLK_PLL30, 68 CLK_PLL31, 69 CLK_PLL5, 70 CLK_PLL1_DIV2, 71 CLK_PLL20_DIV2, 72 CLK_PLL21_DIV2, 73 CLK_PLL30_DIV2, 74 CLK_PLL31_DIV2, 75 CLK_PLL5_DIV2, 76 CLK_PLL5_DIV4, 77 CLK_S1, 78 CLK_S3, 79 CLK_SDSRC, 80 CLK_RPCSRC, 81 CLK_OCO, 82 83 /* Module Clocks */ 84 MOD_CLK_BASE 85 }; 86 87 #define DEF_PLL(_name, _id, _offset) \ 88 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \ 89 .offset = _offset) 90 91 #define DEF_Z(_name, _id, _parent, _div, _offset) \ 92 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_Z, _parent, .div = _div, \ 93 .offset = _offset) 94 95 #define DEF_SD(_name, _id, _parent, _offset) \ 96 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset) 97 98 #define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 99 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \ 100 (_parent0) << 16 | (_parent1), \ 101 .div = (_div0) << 16 | (_div1), .offset = _md) 102 103 #define DEF_OSC(_name, _id, _parent, _div) \ 104 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div) 105 106 static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 107 /* External Clock Inputs */ 108 DEF_INPUT("extal", CLK_EXTAL), 109 DEF_INPUT("extalr", CLK_EXTALR), 110 111 /* Internal Core Clocks */ 112 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL), 113 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN), 114 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN), 115 DEF_PLL(".pll20", CLK_PLL20, 0x0834), 116 DEF_PLL(".pll21", CLK_PLL21, 0x0838), 117 DEF_PLL(".pll30", CLK_PLL30, 0x083c), 118 DEF_PLL(".pll31", CLK_PLL31, 0x0840), 119 120 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 121 DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1), 122 DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1), 123 DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1), 124 DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1), 125 DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), 126 DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), 127 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1), 128 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1), 129 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1), 130 DEF_RATE(".oco", CLK_OCO, 32768), 131 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_R8A779A0_RPCSRC, CLK_PLL5), 132 DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_R8A779A0_RPC, CLK_RPCSRC), 133 DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_R8A779A0_RPCD2, 134 R8A779A0_CLK_RPC), 135 136 /* Core Clock Outputs */ 137 DEF_Z("z0", R8A779A0_CLK_Z0, CLK_PLL20, 2, 0), 138 DEF_Z("z1", R8A779A0_CLK_Z1, CLK_PLL21, 2, 8), 139 DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1), 140 DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1), 141 DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1), 142 DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1), 143 DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1), 144 DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1), 145 DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1), 146 DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1), 147 DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1), 148 DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1), 149 DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1), 150 DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1), 151 DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1), 152 DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1), 153 DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1), 154 DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1), 155 DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1), 156 DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1), 157 DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), 158 DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1), 159 DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), 160 DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1), 161 162 DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870), 163 164 DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), 165 DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), 166 DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), 167 DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884), 168 169 DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), 170 DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), 171 }; 172 173 static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 174 DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2), 175 DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2), 176 DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2), 177 DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2), 178 DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2), 179 DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2), 180 DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0), 181 DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0), 182 DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0), 183 DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0), 184 DEF_MOD("du", 411, R8A779A0_CLK_S3D1), 185 DEF_MOD("dsi0", 415, R8A779A0_CLK_DSI), 186 DEF_MOD("dsi1", 416, R8A779A0_CLK_DSI), 187 DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1), 188 DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1), 189 DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2), 190 DEF_MOD("hscif1", 515, R8A779A0_CLK_S1D2), 191 DEF_MOD("hscif2", 516, R8A779A0_CLK_S1D2), 192 DEF_MOD("hscif3", 517, R8A779A0_CLK_S1D2), 193 DEF_MOD("i2c0", 518, R8A779A0_CLK_S1D4), 194 DEF_MOD("i2c1", 519, R8A779A0_CLK_S1D4), 195 DEF_MOD("i2c2", 520, R8A779A0_CLK_S1D4), 196 DEF_MOD("i2c3", 521, R8A779A0_CLK_S1D4), 197 DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4), 198 DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4), 199 DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4), 200 DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1), 201 DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1), 202 DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1), 203 DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1), 204 DEF_MOD("msi0", 618, R8A779A0_CLK_MSO), 205 DEF_MOD("msi1", 619, R8A779A0_CLK_MSO), 206 DEF_MOD("msi2", 620, R8A779A0_CLK_MSO), 207 DEF_MOD("msi3", 621, R8A779A0_CLK_MSO), 208 DEF_MOD("msi4", 622, R8A779A0_CLK_MSO), 209 DEF_MOD("msi5", 623, R8A779A0_CLK_MSO), 210 DEF_MOD("rpc-if", 629, R8A779A0_CLK_RPCD2), 211 DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), 212 DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), 213 DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8), 214 DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8), 215 DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0), 216 DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2), 217 DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2), 218 DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK), 219 DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4), 220 DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4), 221 DEF_MOD("tmu3", 716, R8A779A0_CLK_S1D4), 222 DEF_MOD("tmu4", 717, R8A779A0_CLK_S1D4), 223 DEF_MOD("tpu0", 718, R8A779A0_CLK_S1D8), 224 DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1), 225 DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1), 226 DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1), 227 DEF_MOD("vin03", 801, R8A779A0_CLK_S1D1), 228 DEF_MOD("vin04", 802, R8A779A0_CLK_S1D1), 229 DEF_MOD("vin05", 803, R8A779A0_CLK_S1D1), 230 DEF_MOD("vin06", 804, R8A779A0_CLK_S1D1), 231 DEF_MOD("vin07", 805, R8A779A0_CLK_S1D1), 232 DEF_MOD("vin10", 806, R8A779A0_CLK_S1D1), 233 DEF_MOD("vin11", 807, R8A779A0_CLK_S1D1), 234 DEF_MOD("vin12", 808, R8A779A0_CLK_S1D1), 235 DEF_MOD("vin13", 809, R8A779A0_CLK_S1D1), 236 DEF_MOD("vin14", 810, R8A779A0_CLK_S1D1), 237 DEF_MOD("vin15", 811, R8A779A0_CLK_S1D1), 238 DEF_MOD("vin16", 812, R8A779A0_CLK_S1D1), 239 DEF_MOD("vin17", 813, R8A779A0_CLK_S1D1), 240 DEF_MOD("vin20", 814, R8A779A0_CLK_S1D1), 241 DEF_MOD("vin21", 815, R8A779A0_CLK_S1D1), 242 DEF_MOD("vin22", 816, R8A779A0_CLK_S1D1), 243 DEF_MOD("vin23", 817, R8A779A0_CLK_S1D1), 244 DEF_MOD("vin24", 818, R8A779A0_CLK_S1D1), 245 DEF_MOD("vin25", 819, R8A779A0_CLK_S1D1), 246 DEF_MOD("vin26", 820, R8A779A0_CLK_S1D1), 247 DEF_MOD("vin27", 821, R8A779A0_CLK_S1D1), 248 DEF_MOD("vin30", 822, R8A779A0_CLK_S1D1), 249 DEF_MOD("vin31", 823, R8A779A0_CLK_S1D1), 250 DEF_MOD("vin32", 824, R8A779A0_CLK_S1D1), 251 DEF_MOD("vin33", 825, R8A779A0_CLK_S1D1), 252 DEF_MOD("vin34", 826, R8A779A0_CLK_S1D1), 253 DEF_MOD("vin35", 827, R8A779A0_CLK_S1D1), 254 DEF_MOD("vin36", 828, R8A779A0_CLK_S1D1), 255 DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1), 256 DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1), 257 DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1), 258 DEF_MOD("rwdt", 907, R8A779A0_CLK_R), 259 DEF_MOD("cmt0", 910, R8A779A0_CLK_R), 260 DEF_MOD("cmt1", 911, R8A779A0_CLK_R), 261 DEF_MOD("cmt2", 912, R8A779A0_CLK_R), 262 DEF_MOD("cmt3", 913, R8A779A0_CLK_R), 263 DEF_MOD("pfc0", 915, R8A779A0_CLK_CP), 264 DEF_MOD("pfc1", 916, R8A779A0_CLK_CP), 265 DEF_MOD("pfc2", 917, R8A779A0_CLK_CP), 266 DEF_MOD("pfc3", 918, R8A779A0_CLK_CP), 267 DEF_MOD("tsc", 919, R8A779A0_CLK_CL16MCK), 268 DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1), 269 DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1), 270 DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1), 271 DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1), 272 }; 273 274 static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata; 275 static unsigned int cpg_clk_extalr __initdata; 276 static u32 cpg_mode __initdata; 277 278 /* 279 * Z0 Clock & Z1 Clock 280 */ 281 #define CPG_FRQCRB 0x00000804 282 #define CPG_FRQCRB_KICK BIT(31) 283 #define CPG_FRQCRC 0x00000808 284 285 struct cpg_z_clk { 286 struct clk_hw hw; 287 void __iomem *reg; 288 void __iomem *kick_reg; 289 unsigned long max_rate; /* Maximum rate for normal mode */ 290 unsigned int fixed_div; 291 u32 mask; 292 }; 293 294 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) 295 296 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, 297 unsigned long parent_rate) 298 { 299 struct cpg_z_clk *zclk = to_z_clk(hw); 300 unsigned int mult; 301 u32 val; 302 303 val = readl(zclk->reg) & zclk->mask; 304 mult = 32 - (val >> __ffs(zclk->mask)); 305 306 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 307 32 * zclk->fixed_div); 308 } 309 310 static int cpg_z_clk_determine_rate(struct clk_hw *hw, 311 struct clk_rate_request *req) 312 { 313 struct cpg_z_clk *zclk = to_z_clk(hw); 314 unsigned int min_mult, max_mult, mult; 315 unsigned long rate, prate; 316 317 rate = min(req->rate, req->max_rate); 318 if (rate <= zclk->max_rate) { 319 /* Set parent rate to initial value for normal modes */ 320 prate = zclk->max_rate; 321 } else { 322 /* Set increased parent rate for boost modes */ 323 prate = rate; 324 } 325 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 326 prate * zclk->fixed_div); 327 328 prate = req->best_parent_rate / zclk->fixed_div; 329 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); 330 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); 331 if (max_mult < min_mult) 332 return -EINVAL; 333 334 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); 335 mult = clamp(mult, min_mult, max_mult); 336 337 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); 338 return 0; 339 } 340 341 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, 342 unsigned long parent_rate) 343 { 344 struct cpg_z_clk *zclk = to_z_clk(hw); 345 unsigned int mult; 346 unsigned int i; 347 348 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, 349 parent_rate); 350 mult = clamp(mult, 1U, 32U); 351 352 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) 353 return -EBUSY; 354 355 cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); 356 357 /* 358 * Set KICK bit in FRQCRB to update hardware setting and wait for 359 * clock change completion. 360 */ 361 cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK); 362 363 /* 364 * Note: There is no HW information about the worst case latency. 365 * 366 * Using experimental measurements, it seems that no more than 367 * ~10 iterations are needed, independently of the CPU rate. 368 * Since this value might be dependent on external xtal rate, pll1 369 * rate or even the other emulation clocks rate, use 1000 as a 370 * "super" safe value. 371 */ 372 for (i = 1000; i; i--) { 373 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) 374 return 0; 375 376 cpu_relax(); 377 } 378 379 return -ETIMEDOUT; 380 } 381 382 static const struct clk_ops cpg_z_clk_ops = { 383 .recalc_rate = cpg_z_clk_recalc_rate, 384 .determine_rate = cpg_z_clk_determine_rate, 385 .set_rate = cpg_z_clk_set_rate, 386 }; 387 388 static struct clk * __init cpg_z_clk_register(const char *name, 389 const char *parent_name, 390 void __iomem *reg, 391 unsigned int div, 392 unsigned int offset) 393 { 394 struct clk_init_data init = {}; 395 struct cpg_z_clk *zclk; 396 struct clk *clk; 397 398 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); 399 if (!zclk) 400 return ERR_PTR(-ENOMEM); 401 402 init.name = name; 403 init.ops = &cpg_z_clk_ops; 404 init.flags = CLK_SET_RATE_PARENT; 405 init.parent_names = &parent_name; 406 init.num_parents = 1; 407 408 zclk->reg = reg + CPG_FRQCRC; 409 zclk->kick_reg = reg + CPG_FRQCRB; 410 zclk->hw.init = &init; 411 zclk->mask = GENMASK(offset + 4, offset); 412 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ 413 414 clk = clk_register(NULL, &zclk->hw); 415 if (IS_ERR(clk)) { 416 kfree(zclk); 417 return clk; 418 } 419 420 zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) / 421 zclk->fixed_div; 422 return clk; 423 } 424 425 /* 426 * RPC Clocks 427 */ 428 #define CPG_RPCCKCR 0x874 429 430 static const struct clk_div_table cpg_rpcsrc_div_table[] = { 431 { 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 }, 432 }; 433 434 static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, 435 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 436 struct clk **clks, void __iomem *base, 437 struct raw_notifier_head *notifiers) 438 { 439 const struct clk *parent; 440 unsigned int mult = 1; 441 unsigned int div = 1; 442 u32 value; 443 444 parent = clks[core->parent & 0xffff]; /* some types use high bits */ 445 if (IS_ERR(parent)) 446 return ERR_CAST(parent); 447 448 switch (core->type) { 449 case CLK_TYPE_R8A779A0_MAIN: 450 div = cpg_pll_config->extal_div; 451 break; 452 453 case CLK_TYPE_R8A779A0_PLL1: 454 mult = cpg_pll_config->pll1_mult; 455 div = cpg_pll_config->pll1_div; 456 break; 457 458 case CLK_TYPE_R8A779A0_PLL2X_3X: 459 value = readl(base + core->offset); 460 mult = (((value >> 24) & 0x7f) + 1) * 2; 461 break; 462 463 case CLK_TYPE_R8A779A0_PLL5: 464 mult = cpg_pll_config->pll5_mult; 465 div = cpg_pll_config->pll5_div; 466 break; 467 468 case CLK_TYPE_R8A779A0_Z: 469 return cpg_z_clk_register(core->name, __clk_get_name(parent), 470 base, core->div, core->offset); 471 472 case CLK_TYPE_R8A779A0_SD: 473 return cpg_sd_clk_register(core->name, base, core->offset, 474 __clk_get_name(parent), notifiers, 475 false); 476 break; 477 478 case CLK_TYPE_R8A779A0_MDSEL: 479 /* 480 * Clock selectable between two parents and two fixed dividers 481 * using a mode pin 482 */ 483 if (cpg_mode & BIT(core->offset)) { 484 div = core->div & 0xffff; 485 } else { 486 parent = clks[core->parent >> 16]; 487 if (IS_ERR(parent)) 488 return ERR_CAST(parent); 489 div = core->div >> 16; 490 } 491 mult = 1; 492 break; 493 494 case CLK_TYPE_R8A779A0_OSC: 495 /* 496 * Clock combining OSC EXTAL predivider and a fixed divider 497 */ 498 div = cpg_pll_config->osc_prediv * core->div; 499 break; 500 501 case CLK_TYPE_R8A779A0_RPCSRC: 502 return clk_register_divider_table(NULL, core->name, 503 __clk_get_name(parent), 0, 504 base + CPG_RPCCKCR, 3, 2, 0, 505 cpg_rpcsrc_div_table, 506 &cpg_lock); 507 508 case CLK_TYPE_R8A779A0_RPC: 509 return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR, 510 __clk_get_name(parent), notifiers); 511 512 case CLK_TYPE_R8A779A0_RPCD2: 513 return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR, 514 __clk_get_name(parent)); 515 516 default: 517 return ERR_PTR(-EINVAL); 518 } 519 520 return clk_register_fixed_factor(NULL, core->name, 521 __clk_get_name(parent), 0, mult, div); 522 } 523 524 static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { 525 MOD_CLK_ID(907), /* RWDT */ 526 }; 527 528 /* 529 * CPG Clock Data 530 */ 531 /* 532 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC 533 * 14 13 (MHz) 21 31 534 * -------------------------------------------------------- 535 * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 536 * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 537 * 1 0 Prohibited setting 538 * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32 539 */ 540 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 541 (((md) & BIT(13)) >> 13)) 542 543 static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = { 544 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */ 545 { 1, 128, 1, 192, 1, 16, }, 546 { 1, 106, 1, 160, 1, 19, }, 547 { 0, 0, 0, 0, 0, 0, }, 548 { 2, 128, 1, 192, 1, 32, }, 549 }; 550 551 static int __init r8a779a0_cpg_mssr_init(struct device *dev) 552 { 553 int error; 554 555 error = rcar_rst_read_mode_pins(&cpg_mode); 556 if (error) 557 return error; 558 559 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 560 cpg_clk_extalr = CLK_EXTALR; 561 spin_lock_init(&cpg_lock); 562 563 return 0; 564 } 565 566 const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { 567 /* Core Clocks */ 568 .core_clks = r8a779a0_core_clks, 569 .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks), 570 .last_dt_core_clk = LAST_DT_CORE_CLK, 571 .num_total_core_clks = MOD_CLK_BASE, 572 573 /* Module Clocks */ 574 .mod_clks = r8a779a0_mod_clks, 575 .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks), 576 .num_hw_mod_clks = 15 * 32, 577 578 /* Critical Module Clocks */ 579 .crit_mod_clks = r8a779a0_crit_mod_clks, 580 .num_crit_mod_clks = ARRAY_SIZE(r8a779a0_crit_mod_clks), 581 582 /* Callbacks */ 583 .init = r8a779a0_cpg_mssr_init, 584 .cpg_clk_register = rcar_r8a779a0_cpg_clk_register, 585 586 .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, 587 }; 588