1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 * 7 * Based on r8a7795-cpg-mssr.c 8 * 9 * Copyright (C) 2015 Glider bvba 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/bug.h> 14 #include <linux/bitfield.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/device.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/pm.h> 23 #include <linux/slab.h> 24 #include <linux/soc/renesas/rcar-rst.h> 25 26 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> 27 28 #include "rcar-cpg-lib.h" 29 #include "renesas-cpg-mssr.h" 30 31 enum rcar_r8a779a0_clk_types { 32 CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM, 33 CLK_TYPE_R8A779A0_PLL1, 34 CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ 35 CLK_TYPE_R8A779A0_PLL5, 36 CLK_TYPE_R8A779A0_Z, 37 CLK_TYPE_R8A779A0_SDH, 38 CLK_TYPE_R8A779A0_SD, 39 CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */ 40 CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */ 41 CLK_TYPE_R8A779A0_RPCSRC, 42 CLK_TYPE_R8A779A0_RPC, 43 CLK_TYPE_R8A779A0_RPCD2, 44 }; 45 46 struct rcar_r8a779a0_cpg_pll_config { 47 u8 extal_div; 48 u8 pll1_mult; 49 u8 pll1_div; 50 u8 pll5_mult; 51 u8 pll5_div; 52 u8 osc_prediv; 53 }; 54 55 enum clk_ids { 56 /* Core Clock Outputs exported to DT */ 57 LAST_DT_CORE_CLK = R8A779A0_CLK_OSC, 58 59 /* External Input Clocks */ 60 CLK_EXTAL, 61 CLK_EXTALR, 62 63 /* Internal Core Clocks */ 64 CLK_MAIN, 65 CLK_PLL1, 66 CLK_PLL20, 67 CLK_PLL21, 68 CLK_PLL30, 69 CLK_PLL31, 70 CLK_PLL5, 71 CLK_PLL1_DIV2, 72 CLK_PLL20_DIV2, 73 CLK_PLL21_DIV2, 74 CLK_PLL30_DIV2, 75 CLK_PLL31_DIV2, 76 CLK_PLL5_DIV2, 77 CLK_PLL5_DIV4, 78 CLK_S1, 79 CLK_S3, 80 CLK_SDSRC, 81 CLK_RPCSRC, 82 CLK_OCO, 83 84 /* Module Clocks */ 85 MOD_CLK_BASE 86 }; 87 88 #define DEF_PLL(_name, _id, _offset) \ 89 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \ 90 .offset = _offset) 91 92 #define DEF_Z(_name, _id, _parent, _div, _offset) \ 93 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_Z, _parent, .div = _div, \ 94 .offset = _offset) 95 96 #define DEF_SDH(_name, _id, _parent, _offset) \ 97 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SDH, _parent, .offset = _offset) 98 99 #define DEF_SD(_name, _id, _parent, _offset) \ 100 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset) 101 102 #define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 103 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \ 104 (_parent0) << 16 | (_parent1), \ 105 .div = (_div0) << 16 | (_div1), .offset = _md) 106 107 #define DEF_OSC(_name, _id, _parent, _div) \ 108 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div) 109 110 static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 111 /* External Clock Inputs */ 112 DEF_INPUT("extal", CLK_EXTAL), 113 DEF_INPUT("extalr", CLK_EXTALR), 114 115 /* Internal Core Clocks */ 116 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL), 117 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN), 118 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN), 119 DEF_PLL(".pll20", CLK_PLL20, 0x0834), 120 DEF_PLL(".pll21", CLK_PLL21, 0x0838), 121 DEF_PLL(".pll30", CLK_PLL30, 0x083c), 122 DEF_PLL(".pll31", CLK_PLL31, 0x0840), 123 124 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 125 DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1), 126 DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1), 127 DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1), 128 DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1), 129 DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), 130 DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), 131 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1), 132 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1), 133 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1), 134 DEF_RATE(".oco", CLK_OCO, 32768), 135 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_R8A779A0_RPCSRC, CLK_PLL5), 136 DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_R8A779A0_RPC, CLK_RPCSRC), 137 DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_R8A779A0_RPCD2, 138 R8A779A0_CLK_RPC), 139 140 /* Core Clock Outputs */ 141 DEF_Z("z0", R8A779A0_CLK_Z0, CLK_PLL20, 2, 0), 142 DEF_Z("z1", R8A779A0_CLK_Z1, CLK_PLL21, 2, 8), 143 DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1), 144 DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1), 145 DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1), 146 DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1), 147 DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1), 148 DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1), 149 DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1), 150 DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1), 151 DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1), 152 DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1), 153 DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1), 154 DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1), 155 DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1), 156 DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1), 157 DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1), 158 DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1), 159 DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1), 160 DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1), 161 DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), 162 DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1), 163 DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), 164 DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1), 165 166 DEF_SDH("sdh0", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870), 167 DEF_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870), 168 169 DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), 170 DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), 171 DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), 172 DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884), 173 174 DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), 175 DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), 176 }; 177 178 static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 179 DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2), 180 DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2), 181 DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2), 182 DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2), 183 DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2), 184 DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2), 185 DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0), 186 DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0), 187 DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0), 188 DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0), 189 DEF_MOD("du", 411, R8A779A0_CLK_S3D1), 190 DEF_MOD("dsi0", 415, R8A779A0_CLK_DSI), 191 DEF_MOD("dsi1", 416, R8A779A0_CLK_DSI), 192 DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1), 193 DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1), 194 DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2), 195 DEF_MOD("hscif1", 515, R8A779A0_CLK_S1D2), 196 DEF_MOD("hscif2", 516, R8A779A0_CLK_S1D2), 197 DEF_MOD("hscif3", 517, R8A779A0_CLK_S1D2), 198 DEF_MOD("i2c0", 518, R8A779A0_CLK_S1D4), 199 DEF_MOD("i2c1", 519, R8A779A0_CLK_S1D4), 200 DEF_MOD("i2c2", 520, R8A779A0_CLK_S1D4), 201 DEF_MOD("i2c3", 521, R8A779A0_CLK_S1D4), 202 DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4), 203 DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4), 204 DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4), 205 DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1), 206 DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1), 207 DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1), 208 DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1), 209 DEF_MOD("msi0", 618, R8A779A0_CLK_MSO), 210 DEF_MOD("msi1", 619, R8A779A0_CLK_MSO), 211 DEF_MOD("msi2", 620, R8A779A0_CLK_MSO), 212 DEF_MOD("msi3", 621, R8A779A0_CLK_MSO), 213 DEF_MOD("msi4", 622, R8A779A0_CLK_MSO), 214 DEF_MOD("msi5", 623, R8A779A0_CLK_MSO), 215 DEF_MOD("rpc-if", 629, R8A779A0_CLK_RPCD2), 216 DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), 217 DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), 218 DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8), 219 DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8), 220 DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0), 221 DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2), 222 DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2), 223 DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK), 224 DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4), 225 DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4), 226 DEF_MOD("tmu3", 716, R8A779A0_CLK_S1D4), 227 DEF_MOD("tmu4", 717, R8A779A0_CLK_S1D4), 228 DEF_MOD("tpu0", 718, R8A779A0_CLK_S1D8), 229 DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1), 230 DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1), 231 DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1), 232 DEF_MOD("vin03", 801, R8A779A0_CLK_S1D1), 233 DEF_MOD("vin04", 802, R8A779A0_CLK_S1D1), 234 DEF_MOD("vin05", 803, R8A779A0_CLK_S1D1), 235 DEF_MOD("vin06", 804, R8A779A0_CLK_S1D1), 236 DEF_MOD("vin07", 805, R8A779A0_CLK_S1D1), 237 DEF_MOD("vin10", 806, R8A779A0_CLK_S1D1), 238 DEF_MOD("vin11", 807, R8A779A0_CLK_S1D1), 239 DEF_MOD("vin12", 808, R8A779A0_CLK_S1D1), 240 DEF_MOD("vin13", 809, R8A779A0_CLK_S1D1), 241 DEF_MOD("vin14", 810, R8A779A0_CLK_S1D1), 242 DEF_MOD("vin15", 811, R8A779A0_CLK_S1D1), 243 DEF_MOD("vin16", 812, R8A779A0_CLK_S1D1), 244 DEF_MOD("vin17", 813, R8A779A0_CLK_S1D1), 245 DEF_MOD("vin20", 814, R8A779A0_CLK_S1D1), 246 DEF_MOD("vin21", 815, R8A779A0_CLK_S1D1), 247 DEF_MOD("vin22", 816, R8A779A0_CLK_S1D1), 248 DEF_MOD("vin23", 817, R8A779A0_CLK_S1D1), 249 DEF_MOD("vin24", 818, R8A779A0_CLK_S1D1), 250 DEF_MOD("vin25", 819, R8A779A0_CLK_S1D1), 251 DEF_MOD("vin26", 820, R8A779A0_CLK_S1D1), 252 DEF_MOD("vin27", 821, R8A779A0_CLK_S1D1), 253 DEF_MOD("vin30", 822, R8A779A0_CLK_S1D1), 254 DEF_MOD("vin31", 823, R8A779A0_CLK_S1D1), 255 DEF_MOD("vin32", 824, R8A779A0_CLK_S1D1), 256 DEF_MOD("vin33", 825, R8A779A0_CLK_S1D1), 257 DEF_MOD("vin34", 826, R8A779A0_CLK_S1D1), 258 DEF_MOD("vin35", 827, R8A779A0_CLK_S1D1), 259 DEF_MOD("vin36", 828, R8A779A0_CLK_S1D1), 260 DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1), 261 DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1), 262 DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1), 263 DEF_MOD("rwdt", 907, R8A779A0_CLK_R), 264 DEF_MOD("cmt0", 910, R8A779A0_CLK_R), 265 DEF_MOD("cmt1", 911, R8A779A0_CLK_R), 266 DEF_MOD("cmt2", 912, R8A779A0_CLK_R), 267 DEF_MOD("cmt3", 913, R8A779A0_CLK_R), 268 DEF_MOD("pfc0", 915, R8A779A0_CLK_CP), 269 DEF_MOD("pfc1", 916, R8A779A0_CLK_CP), 270 DEF_MOD("pfc2", 917, R8A779A0_CLK_CP), 271 DEF_MOD("pfc3", 918, R8A779A0_CLK_CP), 272 DEF_MOD("tsc", 919, R8A779A0_CLK_CL16MCK), 273 DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1), 274 DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1), 275 DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1), 276 DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1), 277 }; 278 279 static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata; 280 static unsigned int cpg_clk_extalr __initdata; 281 static u32 cpg_mode __initdata; 282 283 /* 284 * Z0 Clock & Z1 Clock 285 */ 286 #define CPG_FRQCRB 0x00000804 287 #define CPG_FRQCRB_KICK BIT(31) 288 #define CPG_FRQCRC 0x00000808 289 290 struct cpg_z_clk { 291 struct clk_hw hw; 292 void __iomem *reg; 293 void __iomem *kick_reg; 294 unsigned long max_rate; /* Maximum rate for normal mode */ 295 unsigned int fixed_div; 296 u32 mask; 297 }; 298 299 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) 300 301 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, 302 unsigned long parent_rate) 303 { 304 struct cpg_z_clk *zclk = to_z_clk(hw); 305 unsigned int mult; 306 u32 val; 307 308 val = readl(zclk->reg) & zclk->mask; 309 mult = 32 - (val >> __ffs(zclk->mask)); 310 311 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 312 32 * zclk->fixed_div); 313 } 314 315 static int cpg_z_clk_determine_rate(struct clk_hw *hw, 316 struct clk_rate_request *req) 317 { 318 struct cpg_z_clk *zclk = to_z_clk(hw); 319 unsigned int min_mult, max_mult, mult; 320 unsigned long rate, prate; 321 322 rate = min(req->rate, req->max_rate); 323 if (rate <= zclk->max_rate) { 324 /* Set parent rate to initial value for normal modes */ 325 prate = zclk->max_rate; 326 } else { 327 /* Set increased parent rate for boost modes */ 328 prate = rate; 329 } 330 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 331 prate * zclk->fixed_div); 332 333 prate = req->best_parent_rate / zclk->fixed_div; 334 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); 335 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); 336 if (max_mult < min_mult) 337 return -EINVAL; 338 339 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); 340 mult = clamp(mult, min_mult, max_mult); 341 342 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); 343 return 0; 344 } 345 346 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, 347 unsigned long parent_rate) 348 { 349 struct cpg_z_clk *zclk = to_z_clk(hw); 350 unsigned int mult; 351 unsigned int i; 352 353 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, 354 parent_rate); 355 mult = clamp(mult, 1U, 32U); 356 357 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) 358 return -EBUSY; 359 360 cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); 361 362 /* 363 * Set KICK bit in FRQCRB to update hardware setting and wait for 364 * clock change completion. 365 */ 366 cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK); 367 368 /* 369 * Note: There is no HW information about the worst case latency. 370 * 371 * Using experimental measurements, it seems that no more than 372 * ~10 iterations are needed, independently of the CPU rate. 373 * Since this value might be dependent on external xtal rate, pll1 374 * rate or even the other emulation clocks rate, use 1000 as a 375 * "super" safe value. 376 */ 377 for (i = 1000; i; i--) { 378 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) 379 return 0; 380 381 cpu_relax(); 382 } 383 384 return -ETIMEDOUT; 385 } 386 387 static const struct clk_ops cpg_z_clk_ops = { 388 .recalc_rate = cpg_z_clk_recalc_rate, 389 .determine_rate = cpg_z_clk_determine_rate, 390 .set_rate = cpg_z_clk_set_rate, 391 }; 392 393 static struct clk * __init cpg_z_clk_register(const char *name, 394 const char *parent_name, 395 void __iomem *reg, 396 unsigned int div, 397 unsigned int offset) 398 { 399 struct clk_init_data init = {}; 400 struct cpg_z_clk *zclk; 401 struct clk *clk; 402 403 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); 404 if (!zclk) 405 return ERR_PTR(-ENOMEM); 406 407 init.name = name; 408 init.ops = &cpg_z_clk_ops; 409 init.flags = CLK_SET_RATE_PARENT; 410 init.parent_names = &parent_name; 411 init.num_parents = 1; 412 413 zclk->reg = reg + CPG_FRQCRC; 414 zclk->kick_reg = reg + CPG_FRQCRB; 415 zclk->hw.init = &init; 416 zclk->mask = GENMASK(offset + 4, offset); 417 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ 418 419 clk = clk_register(NULL, &zclk->hw); 420 if (IS_ERR(clk)) { 421 kfree(zclk); 422 return clk; 423 } 424 425 zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) / 426 zclk->fixed_div; 427 return clk; 428 } 429 430 /* 431 * RPC Clocks 432 */ 433 #define CPG_RPCCKCR 0x874 434 435 static const struct clk_div_table cpg_rpcsrc_div_table[] = { 436 { 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 }, 437 }; 438 439 static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, 440 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 441 struct clk **clks, void __iomem *base, 442 struct raw_notifier_head *notifiers) 443 { 444 const struct clk *parent; 445 unsigned int mult = 1; 446 unsigned int div = 1; 447 u32 value; 448 449 parent = clks[core->parent & 0xffff]; /* some types use high bits */ 450 if (IS_ERR(parent)) 451 return ERR_CAST(parent); 452 453 switch (core->type) { 454 case CLK_TYPE_R8A779A0_MAIN: 455 div = cpg_pll_config->extal_div; 456 break; 457 458 case CLK_TYPE_R8A779A0_PLL1: 459 mult = cpg_pll_config->pll1_mult; 460 div = cpg_pll_config->pll1_div; 461 break; 462 463 case CLK_TYPE_R8A779A0_PLL2X_3X: 464 value = readl(base + core->offset); 465 mult = (((value >> 24) & 0x7f) + 1) * 2; 466 break; 467 468 case CLK_TYPE_R8A779A0_PLL5: 469 mult = cpg_pll_config->pll5_mult; 470 div = cpg_pll_config->pll5_div; 471 break; 472 473 case CLK_TYPE_R8A779A0_Z: 474 return cpg_z_clk_register(core->name, __clk_get_name(parent), 475 base, core->div, core->offset); 476 477 case CLK_TYPE_R8A779A0_SDH: 478 return cpg_sdh_clk_register(core->name, base + core->offset, 479 __clk_get_name(parent), notifiers); 480 481 case CLK_TYPE_R8A779A0_SD: 482 return cpg_sd_clk_register(core->name, base + core->offset, 483 __clk_get_name(parent)); 484 485 case CLK_TYPE_R8A779A0_MDSEL: 486 /* 487 * Clock selectable between two parents and two fixed dividers 488 * using a mode pin 489 */ 490 if (cpg_mode & BIT(core->offset)) { 491 div = core->div & 0xffff; 492 } else { 493 parent = clks[core->parent >> 16]; 494 if (IS_ERR(parent)) 495 return ERR_CAST(parent); 496 div = core->div >> 16; 497 } 498 mult = 1; 499 break; 500 501 case CLK_TYPE_R8A779A0_OSC: 502 /* 503 * Clock combining OSC EXTAL predivider and a fixed divider 504 */ 505 div = cpg_pll_config->osc_prediv * core->div; 506 break; 507 508 case CLK_TYPE_R8A779A0_RPCSRC: 509 return clk_register_divider_table(NULL, core->name, 510 __clk_get_name(parent), 0, 511 base + CPG_RPCCKCR, 3, 2, 0, 512 cpg_rpcsrc_div_table, 513 &cpg_lock); 514 515 case CLK_TYPE_R8A779A0_RPC: 516 return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR, 517 __clk_get_name(parent), notifiers); 518 519 case CLK_TYPE_R8A779A0_RPCD2: 520 return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR, 521 __clk_get_name(parent)); 522 523 default: 524 return ERR_PTR(-EINVAL); 525 } 526 527 return clk_register_fixed_factor(NULL, core->name, 528 __clk_get_name(parent), 0, mult, div); 529 } 530 531 static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { 532 MOD_CLK_ID(907), /* RWDT */ 533 }; 534 535 /* 536 * CPG Clock Data 537 */ 538 /* 539 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC 540 * 14 13 (MHz) 21 31 541 * -------------------------------------------------------- 542 * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 543 * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 544 * 1 0 Prohibited setting 545 * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32 546 */ 547 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 548 (((md) & BIT(13)) >> 13)) 549 550 static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = { 551 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */ 552 { 1, 128, 1, 192, 1, 16, }, 553 { 1, 106, 1, 160, 1, 19, }, 554 { 0, 0, 0, 0, 0, 0, }, 555 { 2, 128, 1, 192, 1, 32, }, 556 }; 557 558 static int __init r8a779a0_cpg_mssr_init(struct device *dev) 559 { 560 int error; 561 562 error = rcar_rst_read_mode_pins(&cpg_mode); 563 if (error) 564 return error; 565 566 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 567 cpg_clk_extalr = CLK_EXTALR; 568 spin_lock_init(&cpg_lock); 569 570 return 0; 571 } 572 573 const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { 574 /* Core Clocks */ 575 .core_clks = r8a779a0_core_clks, 576 .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks), 577 .last_dt_core_clk = LAST_DT_CORE_CLK, 578 .num_total_core_clks = MOD_CLK_BASE, 579 580 /* Module Clocks */ 581 .mod_clks = r8a779a0_mod_clks, 582 .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks), 583 .num_hw_mod_clks = 15 * 32, 584 585 /* Critical Module Clocks */ 586 .crit_mod_clks = r8a779a0_crit_mod_clks, 587 .num_crit_mod_clks = ARRAY_SIZE(r8a779a0_crit_mod_clks), 588 589 /* Callbacks */ 590 .init = r8a779a0_cpg_mssr_init, 591 .cpg_clk_register = rcar_r8a779a0_cpg_clk_register, 592 593 .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, 594 }; 595