117bcc803SYoshihiro Shimoda // SPDX-License-Identifier: GPL-2.0 217bcc803SYoshihiro Shimoda /* 317bcc803SYoshihiro Shimoda * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset 417bcc803SYoshihiro Shimoda * 517bcc803SYoshihiro Shimoda * Copyright (C) 2020 Renesas Electronics Corp. 617bcc803SYoshihiro Shimoda * 717bcc803SYoshihiro Shimoda * Based on r8a7795-cpg-mssr.c 817bcc803SYoshihiro Shimoda * 917bcc803SYoshihiro Shimoda * Copyright (C) 2015 Glider bvba 1017bcc803SYoshihiro Shimoda * Copyright (C) 2015 Renesas Electronics Corp. 1117bcc803SYoshihiro Shimoda */ 1217bcc803SYoshihiro Shimoda 1317bcc803SYoshihiro Shimoda #include <linux/bug.h> 1417bcc803SYoshihiro Shimoda #include <linux/bitfield.h> 1517bcc803SYoshihiro Shimoda #include <linux/clk.h> 1617bcc803SYoshihiro Shimoda #include <linux/clk-provider.h> 1717bcc803SYoshihiro Shimoda #include <linux/device.h> 1817bcc803SYoshihiro Shimoda #include <linux/err.h> 1917bcc803SYoshihiro Shimoda #include <linux/init.h> 2017bcc803SYoshihiro Shimoda #include <linux/io.h> 2117bcc803SYoshihiro Shimoda #include <linux/kernel.h> 2217bcc803SYoshihiro Shimoda #include <linux/pm.h> 2317bcc803SYoshihiro Shimoda #include <linux/slab.h> 2417bcc803SYoshihiro Shimoda #include <linux/soc/renesas/rcar-rst.h> 2517bcc803SYoshihiro Shimoda 2617bcc803SYoshihiro Shimoda #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> 2717bcc803SYoshihiro Shimoda 2817bcc803SYoshihiro Shimoda #include "renesas-cpg-mssr.h" 2917bcc803SYoshihiro Shimoda 3017bcc803SYoshihiro Shimoda enum rcar_r8a779a0_clk_types { 3117bcc803SYoshihiro Shimoda CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM, 3217bcc803SYoshihiro Shimoda CLK_TYPE_R8A779A0_PLL1, 3317bcc803SYoshihiro Shimoda CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ 3417bcc803SYoshihiro Shimoda CLK_TYPE_R8A779A0_PLL5, 3517bcc803SYoshihiro Shimoda CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */ 3617bcc803SYoshihiro Shimoda CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */ 3717bcc803SYoshihiro Shimoda }; 3817bcc803SYoshihiro Shimoda 3917bcc803SYoshihiro Shimoda struct rcar_r8a779a0_cpg_pll_config { 4017bcc803SYoshihiro Shimoda u8 extal_div; 4117bcc803SYoshihiro Shimoda u8 pll1_mult; 4217bcc803SYoshihiro Shimoda u8 pll1_div; 4317bcc803SYoshihiro Shimoda u8 pll5_mult; 4417bcc803SYoshihiro Shimoda u8 pll5_div; 4517bcc803SYoshihiro Shimoda u8 osc_prediv; 4617bcc803SYoshihiro Shimoda }; 4717bcc803SYoshihiro Shimoda 4817bcc803SYoshihiro Shimoda enum clk_ids { 4917bcc803SYoshihiro Shimoda /* Core Clock Outputs exported to DT */ 5017bcc803SYoshihiro Shimoda LAST_DT_CORE_CLK = R8A779A0_CLK_OSC, 5117bcc803SYoshihiro Shimoda 5217bcc803SYoshihiro Shimoda /* External Input Clocks */ 5317bcc803SYoshihiro Shimoda CLK_EXTAL, 5417bcc803SYoshihiro Shimoda CLK_EXTALR, 5517bcc803SYoshihiro Shimoda 5617bcc803SYoshihiro Shimoda /* Internal Core Clocks */ 5717bcc803SYoshihiro Shimoda CLK_MAIN, 5817bcc803SYoshihiro Shimoda CLK_PLL1, 5917bcc803SYoshihiro Shimoda CLK_PLL20, 6017bcc803SYoshihiro Shimoda CLK_PLL21, 6117bcc803SYoshihiro Shimoda CLK_PLL30, 6217bcc803SYoshihiro Shimoda CLK_PLL31, 6317bcc803SYoshihiro Shimoda CLK_PLL5, 6417bcc803SYoshihiro Shimoda CLK_PLL1_DIV2, 6517bcc803SYoshihiro Shimoda CLK_PLL20_DIV2, 6617bcc803SYoshihiro Shimoda CLK_PLL21_DIV2, 6717bcc803SYoshihiro Shimoda CLK_PLL30_DIV2, 6817bcc803SYoshihiro Shimoda CLK_PLL31_DIV2, 6917bcc803SYoshihiro Shimoda CLK_PLL5_DIV2, 7017bcc803SYoshihiro Shimoda CLK_PLL5_DIV4, 7117bcc803SYoshihiro Shimoda CLK_S1, 7217bcc803SYoshihiro Shimoda CLK_S2, 7317bcc803SYoshihiro Shimoda CLK_S3, 7417bcc803SYoshihiro Shimoda CLK_SDSRC, 7517bcc803SYoshihiro Shimoda CLK_RPCSRC, 7617bcc803SYoshihiro Shimoda CLK_OCO, 7717bcc803SYoshihiro Shimoda 7817bcc803SYoshihiro Shimoda /* Module Clocks */ 7917bcc803SYoshihiro Shimoda MOD_CLK_BASE 8017bcc803SYoshihiro Shimoda }; 8117bcc803SYoshihiro Shimoda 8217bcc803SYoshihiro Shimoda #define DEF_PLL(_name, _id, _offset) \ 8317bcc803SYoshihiro Shimoda DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \ 8417bcc803SYoshihiro Shimoda .offset = _offset) 8517bcc803SYoshihiro Shimoda 86*14653942SGeert Uytterhoeven #define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 87*14653942SGeert Uytterhoeven DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \ 88*14653942SGeert Uytterhoeven (_parent0) << 16 | (_parent1), \ 89*14653942SGeert Uytterhoeven .div = (_div0) << 16 | (_div1), .offset = _md) 90*14653942SGeert Uytterhoeven 91*14653942SGeert Uytterhoeven #define DEF_OSC(_name, _id, _parent, _div) \ 92*14653942SGeert Uytterhoeven DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div) 93*14653942SGeert Uytterhoeven 9417bcc803SYoshihiro Shimoda static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 9517bcc803SYoshihiro Shimoda /* External Clock Inputs */ 9617bcc803SYoshihiro Shimoda DEF_INPUT("extal", CLK_EXTAL), 9717bcc803SYoshihiro Shimoda DEF_INPUT("extalr", CLK_EXTALR), 9817bcc803SYoshihiro Shimoda 9917bcc803SYoshihiro Shimoda /* Internal Core Clocks */ 10017bcc803SYoshihiro Shimoda DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL), 10117bcc803SYoshihiro Shimoda DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN), 10217bcc803SYoshihiro Shimoda DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN), 10317bcc803SYoshihiro Shimoda DEF_PLL(".pll20", CLK_PLL20, 0x0834), 10417bcc803SYoshihiro Shimoda DEF_PLL(".pll21", CLK_PLL21, 0x0838), 10517bcc803SYoshihiro Shimoda DEF_PLL(".pll30", CLK_PLL30, 0x083c), 10617bcc803SYoshihiro Shimoda DEF_PLL(".pll31", CLK_PLL31, 0x0840), 10717bcc803SYoshihiro Shimoda 10817bcc803SYoshihiro Shimoda DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 10917bcc803SYoshihiro Shimoda DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1), 11017bcc803SYoshihiro Shimoda DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1), 11117bcc803SYoshihiro Shimoda DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1), 11217bcc803SYoshihiro Shimoda DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1), 11317bcc803SYoshihiro Shimoda DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), 11417bcc803SYoshihiro Shimoda DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), 11517bcc803SYoshihiro Shimoda DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1), 11617bcc803SYoshihiro Shimoda DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1), 11717bcc803SYoshihiro Shimoda DEF_RATE(".oco", CLK_OCO, 32768), 11817bcc803SYoshihiro Shimoda 11917bcc803SYoshihiro Shimoda /* Core Clock Outputs */ 12017bcc803SYoshihiro Shimoda DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1), 12117bcc803SYoshihiro Shimoda DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1), 12217bcc803SYoshihiro Shimoda DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1), 12317bcc803SYoshihiro Shimoda DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1), 12417bcc803SYoshihiro Shimoda DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1), 12517bcc803SYoshihiro Shimoda DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1), 12617bcc803SYoshihiro Shimoda DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1), 12717bcc803SYoshihiro Shimoda DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1), 12817bcc803SYoshihiro Shimoda DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1), 12917bcc803SYoshihiro Shimoda DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1), 13017bcc803SYoshihiro Shimoda DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1), 13117bcc803SYoshihiro Shimoda DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1), 13217bcc803SYoshihiro Shimoda DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1), 13317bcc803SYoshihiro Shimoda DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1), 13417bcc803SYoshihiro Shimoda DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1), 13517bcc803SYoshihiro Shimoda DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1), 13617bcc803SYoshihiro Shimoda DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1), 13717bcc803SYoshihiro Shimoda DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1), 13817bcc803SYoshihiro Shimoda DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1), 13917bcc803SYoshihiro Shimoda DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), 14017bcc803SYoshihiro Shimoda DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_MAIN, 2, 1), 14117bcc803SYoshihiro Shimoda 14217bcc803SYoshihiro Shimoda DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), 14317bcc803SYoshihiro Shimoda DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), 14417bcc803SYoshihiro Shimoda DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), 14517bcc803SYoshihiro Shimoda 146*14653942SGeert Uytterhoeven DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), 147*14653942SGeert Uytterhoeven DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), 14817bcc803SYoshihiro Shimoda }; 14917bcc803SYoshihiro Shimoda 15017bcc803SYoshihiro Shimoda static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 15123378e70SJacopo Mondi DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0), 15223378e70SJacopo Mondi DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0), 15323378e70SJacopo Mondi DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0), 15423378e70SJacopo Mondi DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0), 15517bcc803SYoshihiro Shimoda DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), 15617bcc803SYoshihiro Shimoda DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), 15717bcc803SYoshihiro Shimoda DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8), 15817bcc803SYoshihiro Shimoda DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8), 159874d4eeeSJacopo Mondi DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1), 160874d4eeeSJacopo Mondi DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1), 161874d4eeeSJacopo Mondi DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1), 162874d4eeeSJacopo Mondi DEF_MOD("vin03", 801, R8A779A0_CLK_S1D1), 163874d4eeeSJacopo Mondi DEF_MOD("vin04", 802, R8A779A0_CLK_S1D1), 164874d4eeeSJacopo Mondi DEF_MOD("vin05", 803, R8A779A0_CLK_S1D1), 165874d4eeeSJacopo Mondi DEF_MOD("vin06", 804, R8A779A0_CLK_S1D1), 166874d4eeeSJacopo Mondi DEF_MOD("vin07", 805, R8A779A0_CLK_S1D1), 167874d4eeeSJacopo Mondi DEF_MOD("vin10", 806, R8A779A0_CLK_S1D1), 168874d4eeeSJacopo Mondi DEF_MOD("vin11", 807, R8A779A0_CLK_S1D1), 169874d4eeeSJacopo Mondi DEF_MOD("vin12", 808, R8A779A0_CLK_S1D1), 170874d4eeeSJacopo Mondi DEF_MOD("vin13", 809, R8A779A0_CLK_S1D1), 171874d4eeeSJacopo Mondi DEF_MOD("vin14", 810, R8A779A0_CLK_S1D1), 172874d4eeeSJacopo Mondi DEF_MOD("vin15", 811, R8A779A0_CLK_S1D1), 173874d4eeeSJacopo Mondi DEF_MOD("vin16", 812, R8A779A0_CLK_S1D1), 174874d4eeeSJacopo Mondi DEF_MOD("vin17", 813, R8A779A0_CLK_S1D1), 175874d4eeeSJacopo Mondi DEF_MOD("vin20", 814, R8A779A0_CLK_S1D1), 176874d4eeeSJacopo Mondi DEF_MOD("vin21", 815, R8A779A0_CLK_S1D1), 177874d4eeeSJacopo Mondi DEF_MOD("vin22", 816, R8A779A0_CLK_S1D1), 178874d4eeeSJacopo Mondi DEF_MOD("vin23", 817, R8A779A0_CLK_S1D1), 179874d4eeeSJacopo Mondi DEF_MOD("vin24", 818, R8A779A0_CLK_S1D1), 180874d4eeeSJacopo Mondi DEF_MOD("vin25", 819, R8A779A0_CLK_S1D1), 181874d4eeeSJacopo Mondi DEF_MOD("vin26", 820, R8A779A0_CLK_S1D1), 182874d4eeeSJacopo Mondi DEF_MOD("vin27", 821, R8A779A0_CLK_S1D1), 183874d4eeeSJacopo Mondi DEF_MOD("vin30", 822, R8A779A0_CLK_S1D1), 184874d4eeeSJacopo Mondi DEF_MOD("vin31", 823, R8A779A0_CLK_S1D1), 185874d4eeeSJacopo Mondi DEF_MOD("vin32", 824, R8A779A0_CLK_S1D1), 186874d4eeeSJacopo Mondi DEF_MOD("vin33", 825, R8A779A0_CLK_S1D1), 187874d4eeeSJacopo Mondi DEF_MOD("vin34", 826, R8A779A0_CLK_S1D1), 188874d4eeeSJacopo Mondi DEF_MOD("vin35", 827, R8A779A0_CLK_S1D1), 189874d4eeeSJacopo Mondi DEF_MOD("vin36", 828, R8A779A0_CLK_S1D1), 190874d4eeeSJacopo Mondi DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1), 19117bcc803SYoshihiro Shimoda }; 19217bcc803SYoshihiro Shimoda 19317bcc803SYoshihiro Shimoda static spinlock_t cpg_lock; 19417bcc803SYoshihiro Shimoda 19517bcc803SYoshihiro Shimoda static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata; 19617bcc803SYoshihiro Shimoda static unsigned int cpg_clk_extalr __initdata; 19717bcc803SYoshihiro Shimoda static u32 cpg_mode __initdata; 19817bcc803SYoshihiro Shimoda 1990ca995f5SGeert Uytterhoeven static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, 20017bcc803SYoshihiro Shimoda const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 20117bcc803SYoshihiro Shimoda struct clk **clks, void __iomem *base, 20217bcc803SYoshihiro Shimoda struct raw_notifier_head *notifiers) 20317bcc803SYoshihiro Shimoda { 20417bcc803SYoshihiro Shimoda const struct clk *parent; 20517bcc803SYoshihiro Shimoda unsigned int mult = 1; 20617bcc803SYoshihiro Shimoda unsigned int div = 1; 20717bcc803SYoshihiro Shimoda u32 value; 20817bcc803SYoshihiro Shimoda 20917bcc803SYoshihiro Shimoda parent = clks[core->parent & 0xffff]; /* some types use high bits */ 21017bcc803SYoshihiro Shimoda if (IS_ERR(parent)) 21117bcc803SYoshihiro Shimoda return ERR_CAST(parent); 21217bcc803SYoshihiro Shimoda 21317bcc803SYoshihiro Shimoda switch (core->type) { 21417bcc803SYoshihiro Shimoda case CLK_TYPE_R8A779A0_MAIN: 21517bcc803SYoshihiro Shimoda div = cpg_pll_config->extal_div; 21617bcc803SYoshihiro Shimoda break; 21717bcc803SYoshihiro Shimoda 21817bcc803SYoshihiro Shimoda case CLK_TYPE_R8A779A0_PLL1: 21917bcc803SYoshihiro Shimoda mult = cpg_pll_config->pll1_mult; 22017bcc803SYoshihiro Shimoda div = cpg_pll_config->pll1_div; 22117bcc803SYoshihiro Shimoda break; 22217bcc803SYoshihiro Shimoda 22317bcc803SYoshihiro Shimoda case CLK_TYPE_R8A779A0_PLL2X_3X: 22417bcc803SYoshihiro Shimoda value = readl(base + core->offset); 22517bcc803SYoshihiro Shimoda mult = (((value >> 24) & 0x7f) + 1) * 2; 22617bcc803SYoshihiro Shimoda break; 22717bcc803SYoshihiro Shimoda 22817bcc803SYoshihiro Shimoda case CLK_TYPE_R8A779A0_PLL5: 22917bcc803SYoshihiro Shimoda mult = cpg_pll_config->pll5_mult; 23017bcc803SYoshihiro Shimoda div = cpg_pll_config->pll5_div; 23117bcc803SYoshihiro Shimoda break; 23217bcc803SYoshihiro Shimoda 23317bcc803SYoshihiro Shimoda case CLK_TYPE_R8A779A0_MDSEL: 23417bcc803SYoshihiro Shimoda /* 23517bcc803SYoshihiro Shimoda * Clock selectable between two parents and two fixed dividers 23617bcc803SYoshihiro Shimoda * using a mode pin 23717bcc803SYoshihiro Shimoda */ 23817bcc803SYoshihiro Shimoda if (cpg_mode & BIT(core->offset)) { 23917bcc803SYoshihiro Shimoda div = core->div & 0xffff; 24017bcc803SYoshihiro Shimoda } else { 24117bcc803SYoshihiro Shimoda parent = clks[core->parent >> 16]; 24217bcc803SYoshihiro Shimoda if (IS_ERR(parent)) 24317bcc803SYoshihiro Shimoda return ERR_CAST(parent); 24417bcc803SYoshihiro Shimoda div = core->div >> 16; 24517bcc803SYoshihiro Shimoda } 24617bcc803SYoshihiro Shimoda mult = 1; 24717bcc803SYoshihiro Shimoda break; 24817bcc803SYoshihiro Shimoda 24917bcc803SYoshihiro Shimoda case CLK_TYPE_R8A779A0_OSC: 25017bcc803SYoshihiro Shimoda /* 25117bcc803SYoshihiro Shimoda * Clock combining OSC EXTAL predivider and a fixed divider 25217bcc803SYoshihiro Shimoda */ 25317bcc803SYoshihiro Shimoda div = cpg_pll_config->osc_prediv * core->div; 25417bcc803SYoshihiro Shimoda break; 25517bcc803SYoshihiro Shimoda 25617bcc803SYoshihiro Shimoda default: 25717bcc803SYoshihiro Shimoda return ERR_PTR(-EINVAL); 25817bcc803SYoshihiro Shimoda } 25917bcc803SYoshihiro Shimoda 26017bcc803SYoshihiro Shimoda return clk_register_fixed_factor(NULL, core->name, 26117bcc803SYoshihiro Shimoda __clk_get_name(parent), 0, mult, div); 26217bcc803SYoshihiro Shimoda } 26317bcc803SYoshihiro Shimoda 26417bcc803SYoshihiro Shimoda /* 26517bcc803SYoshihiro Shimoda * CPG Clock Data 26617bcc803SYoshihiro Shimoda */ 26717bcc803SYoshihiro Shimoda /* 26817bcc803SYoshihiro Shimoda * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC 26917bcc803SYoshihiro Shimoda * 14 13 (MHz) 21 31 27017bcc803SYoshihiro Shimoda * -------------------------------------------------------- 27117bcc803SYoshihiro Shimoda * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 27217bcc803SYoshihiro Shimoda * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 27317bcc803SYoshihiro Shimoda * 1 0 Prohibited setting 27417bcc803SYoshihiro Shimoda * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32 27517bcc803SYoshihiro Shimoda */ 27617bcc803SYoshihiro Shimoda #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 27717bcc803SYoshihiro Shimoda (((md) & BIT(13)) >> 13)) 27817bcc803SYoshihiro Shimoda 27917bcc803SYoshihiro Shimoda static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = { 28017bcc803SYoshihiro Shimoda /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */ 28117bcc803SYoshihiro Shimoda { 1, 128, 1, 192, 1, 16, }, 28217bcc803SYoshihiro Shimoda { 1, 106, 1, 160, 1, 19, }, 28317bcc803SYoshihiro Shimoda { 0, 0, 0, 0, 0, 0, }, 28417bcc803SYoshihiro Shimoda { 2, 128, 1, 192, 1, 32, }, 28517bcc803SYoshihiro Shimoda }; 28617bcc803SYoshihiro Shimoda 28717bcc803SYoshihiro Shimoda static int __init r8a779a0_cpg_mssr_init(struct device *dev) 28817bcc803SYoshihiro Shimoda { 28917bcc803SYoshihiro Shimoda int error; 29017bcc803SYoshihiro Shimoda 29117bcc803SYoshihiro Shimoda error = rcar_rst_read_mode_pins(&cpg_mode); 29217bcc803SYoshihiro Shimoda if (error) 29317bcc803SYoshihiro Shimoda return error; 29417bcc803SYoshihiro Shimoda 29517bcc803SYoshihiro Shimoda cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 29617bcc803SYoshihiro Shimoda cpg_clk_extalr = CLK_EXTALR; 29717bcc803SYoshihiro Shimoda spin_lock_init(&cpg_lock); 29817bcc803SYoshihiro Shimoda 29917bcc803SYoshihiro Shimoda return 0; 30017bcc803SYoshihiro Shimoda } 30117bcc803SYoshihiro Shimoda 30217bcc803SYoshihiro Shimoda const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { 30317bcc803SYoshihiro Shimoda /* Core Clocks */ 30417bcc803SYoshihiro Shimoda .core_clks = r8a779a0_core_clks, 30517bcc803SYoshihiro Shimoda .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks), 30617bcc803SYoshihiro Shimoda .last_dt_core_clk = LAST_DT_CORE_CLK, 30717bcc803SYoshihiro Shimoda .num_total_core_clks = MOD_CLK_BASE, 30817bcc803SYoshihiro Shimoda 30917bcc803SYoshihiro Shimoda /* Module Clocks */ 31017bcc803SYoshihiro Shimoda .mod_clks = r8a779a0_mod_clks, 31117bcc803SYoshihiro Shimoda .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks), 31217bcc803SYoshihiro Shimoda .num_hw_mod_clks = 15 * 32, 31317bcc803SYoshihiro Shimoda 31417bcc803SYoshihiro Shimoda /* Callbacks */ 31517bcc803SYoshihiro Shimoda .init = r8a779a0_cpg_mssr_init, 31617bcc803SYoshihiro Shimoda .cpg_clk_register = rcar_r8a779a0_cpg_clk_register, 31717bcc803SYoshihiro Shimoda 31817bcc803SYoshihiro Shimoda .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, 31917bcc803SYoshihiro Shimoda }; 320