1 /* 2 * r8a77995 Clock Pulse Generator / Module Standby and Software Reset 3 * 4 * Copyright (C) 2017 Glider bvba 5 * 6 * Based on r8a7795-cpg-mssr.c 7 * 8 * Copyright (C) 2015 Glider bvba 9 * Copyright (C) 2015 Renesas Electronics Corp. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; version 2 of the License. 14 */ 15 16 #include <linux/device.h> 17 #include <linux/init.h> 18 #include <linux/kernel.h> 19 #include <linux/soc/renesas/rcar-rst.h> 20 21 #include <dt-bindings/clock/r8a77995-cpg-mssr.h> 22 23 #include "renesas-cpg-mssr.h" 24 #include "rcar-gen3-cpg.h" 25 26 enum clk_ids { 27 /* Core Clock Outputs exported to DT */ 28 LAST_DT_CORE_CLK = R8A77995_CLK_CP, 29 30 /* External Input Clocks */ 31 CLK_EXTAL, 32 33 /* Internal Core Clocks */ 34 CLK_MAIN, 35 CLK_PLL0, 36 CLK_PLL1, 37 CLK_PLL3, 38 CLK_PLL0D2, 39 CLK_PLL0D3, 40 CLK_PLL0D5, 41 CLK_PLL1D2, 42 CLK_PE, 43 CLK_S0, 44 CLK_S1, 45 CLK_S2, 46 CLK_S3, 47 CLK_SDSRC, 48 CLK_SSPSRC, 49 50 /* Module Clocks */ 51 MOD_CLK_BASE 52 }; 53 54 static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { 55 /* External Clock Inputs */ 56 DEF_INPUT("extal", CLK_EXTAL), 57 58 /* Internal Core Clocks */ 59 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 60 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 61 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 62 63 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250), 64 DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1), 65 DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1), 66 DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1), 67 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1), 68 DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1), 69 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1), 70 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1), 71 DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), 72 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), 73 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), 74 75 /* Core Clock Outputs */ 76 DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), 77 DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), 78 DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1), 79 DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1), 80 DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1), 81 DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1), 82 DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1), 83 DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1), 84 DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1), 85 DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1), 86 DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1), 87 DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1), 88 DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1), 89 DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1), 90 91 DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1), 92 DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1), 93 DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1), 94 DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1), 95 96 DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2), 97 DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), 98 DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), 99 DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), 100 101 DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268), 102 103 DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244), 104 DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014), 105 }; 106 107 static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { 108 DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C), 109 DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C), 110 DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C), 111 DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C), 112 DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C), 113 DEF_MOD("msiof3", 208, R8A77995_CLK_MSO), 114 DEF_MOD("msiof2", 209, R8A77995_CLK_MSO), 115 DEF_MOD("msiof1", 210, R8A77995_CLK_MSO), 116 DEF_MOD("msiof0", 211, R8A77995_CLK_MSO), 117 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1), 118 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1), 119 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1), 120 DEF_MOD("cmt3", 300, R8A77995_CLK_R), 121 DEF_MOD("cmt2", 301, R8A77995_CLK_R), 122 DEF_MOD("cmt1", 302, R8A77995_CLK_R), 123 DEF_MOD("cmt0", 303, R8A77995_CLK_R), 124 DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C), 125 DEF_MOD("emmc0", 312, R8A77995_CLK_SD0), 126 DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1), 127 DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1), 128 DEF_MOD("rwdt", 402, R8A77995_CLK_R), 129 DEF_MOD("intc-ex", 407, R8A77995_CLK_CP), 130 DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1), 131 DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1), 132 DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C), 133 DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C), 134 DEF_MOD("thermal", 522, R8A77995_CLK_CP), 135 DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C), 136 DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2), 137 DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2), 138 DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1), 139 DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2), 140 DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2), 141 DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1), 142 DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2), 143 DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2), 144 DEF_MOD("du1", 723, R8A77995_CLK_S2D1), 145 DEF_MOD("du0", 724, R8A77995_CLK_S2D1), 146 DEF_MOD("lvds", 727, R8A77995_CLK_S2D1), 147 DEF_MOD("vin7", 804, R8A77995_CLK_S1D2), 148 DEF_MOD("vin6", 805, R8A77995_CLK_S1D2), 149 DEF_MOD("vin5", 806, R8A77995_CLK_S1D2), 150 DEF_MOD("vin4", 807, R8A77995_CLK_S1D2), 151 DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2), 152 DEF_MOD("imr0", 823, R8A77995_CLK_S1D2), 153 DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4), 154 DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4), 155 DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4), 156 DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4), 157 DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4), 158 DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4), 159 DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4), 160 DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2), 161 DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4), 162 DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4), 163 DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2), 164 DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2), 165 DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2), 166 DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2), 167 DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4), 168 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 169 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 170 DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4), 171 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 172 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 173 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 174 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 175 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 176 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 177 }; 178 179 static const unsigned int r8a77995_crit_mod_clks[] __initconst = { 180 MOD_CLK_ID(408), /* INTC-AP (GIC) */ 181 }; 182 183 184 /* 185 * CPG Clock Data 186 */ 187 188 /* 189 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 190 *-------------------------------------------------------------------- 191 * 0 48 x 1 x250/4 x100/3 x100/3 192 * 1 48 x 1 x250/4 x100/3 x116/6 193 */ 194 #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) 195 196 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = { 197 /* EXTAL div PLL1 mult/div PLL3 mult/div */ 198 { 1, 100, 3, 100, 3, }, 199 { 1, 100, 3, 116, 6, }, 200 }; 201 202 static int __init r8a77995_cpg_mssr_init(struct device *dev) 203 { 204 const struct rcar_gen3_cpg_pll_config *cpg_pll_config; 205 u32 cpg_mode; 206 int error; 207 208 error = rcar_rst_read_mode_pins(&cpg_mode); 209 if (error) 210 return error; 211 212 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 213 214 return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode); 215 } 216 217 const struct cpg_mssr_info r8a77995_cpg_mssr_info __initconst = { 218 /* Core Clocks */ 219 .core_clks = r8a77995_core_clks, 220 .num_core_clks = ARRAY_SIZE(r8a77995_core_clks), 221 .last_dt_core_clk = LAST_DT_CORE_CLK, 222 .num_total_core_clks = MOD_CLK_BASE, 223 224 /* Module Clocks */ 225 .mod_clks = r8a77995_mod_clks, 226 .num_mod_clks = ARRAY_SIZE(r8a77995_mod_clks), 227 .num_hw_mod_clks = 12 * 32, 228 229 /* Critical Module Clocks */ 230 .crit_mod_clks = r8a77995_crit_mod_clks, 231 .num_crit_mod_clks = ARRAY_SIZE(r8a77995_crit_mod_clks), 232 233 /* Callbacks */ 234 .init = r8a77995_cpg_mssr_init, 235 .cpg_clk_register = rcar_gen3_cpg_clk_register, 236 }; 237