1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2015 Glider bvba 6 * Copyright (C) 2018-2019 Renesas Electronics Corp. 7 * 8 * Based on clk-rcar-gen3.c 9 * 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/device.h> 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/soc/renesas/rcar-rst.h> 17 #include <linux/sys_soc.h> 18 19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 20 21 #include "renesas-cpg-mssr.h" 22 #include "rcar-gen3-cpg.h" 23 24 enum clk_ids { 25 /* Core Clock Outputs exported to DT */ 26 LAST_DT_CORE_CLK = R8A7795_CLK_S0D12, 27 28 /* External Input Clocks */ 29 CLK_EXTAL, 30 CLK_EXTALR, 31 32 /* Internal Core Clocks */ 33 CLK_MAIN, 34 CLK_PLL0, 35 CLK_PLL1, 36 CLK_PLL2, 37 CLK_PLL3, 38 CLK_PLL4, 39 CLK_PLL1_DIV2, 40 CLK_PLL1_DIV4, 41 CLK_S0, 42 CLK_S1, 43 CLK_S2, 44 CLK_S3, 45 CLK_SDSRC, 46 CLK_SSPSRC, 47 CLK_RPCSRC, 48 CLK_RINT, 49 50 /* Module Clocks */ 51 MOD_CLK_BASE 52 }; 53 54 static struct cpg_core_clk r8a7795_core_clks[] __initdata = { 55 /* External Clock Inputs */ 56 DEF_INPUT("extal", CLK_EXTAL), 57 DEF_INPUT("extalr", CLK_EXTALR), 58 59 /* Internal Core Clocks */ 60 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 61 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 62 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 63 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 64 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 65 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), 66 67 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 68 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 69 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 70 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), 71 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), 72 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 73 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 74 75 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), 76 77 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), 78 79 /* Core Clock Outputs */ 80 DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), 81 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 82 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 83 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 84 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 85 DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1), 86 DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1), 87 DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1), 88 DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1), 89 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1), 90 DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1), 91 DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1), 92 DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1), 93 DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1), 94 DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1), 95 DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1), 96 DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1), 97 DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1), 98 DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1), 99 DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1), 100 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), 101 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), 102 103 DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074), 104 DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078), 105 DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268), 106 DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c), 107 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074), 108 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078), 109 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268), 110 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c), 111 112 DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), 113 DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7795_CLK_RPC), 114 115 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), 116 DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1), 117 DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), 118 DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1), 119 120 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 121 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), 122 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), 123 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), 124 125 DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8), 126 127 DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 128 }; 129 130 static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 131 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */ 132 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), 133 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), 134 DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6), 135 DEF_MOD("tmu3", 122, R8A7795_CLK_S3D2), 136 DEF_MOD("tmu2", 123, R8A7795_CLK_S3D2), 137 DEF_MOD("tmu1", 124, R8A7795_CLK_S3D2), 138 DEF_MOD("tmu0", 125, R8A7795_CLK_CP), 139 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), 140 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), 141 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), 142 DEF_MOD("scif1", 206, R8A7795_CLK_S3D4), 143 DEF_MOD("scif0", 207, R8A7795_CLK_S3D4), 144 DEF_MOD("msiof3", 208, R8A7795_CLK_MSO), 145 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), 146 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), 147 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), 148 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1), 149 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1), 150 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3), 151 DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR), 152 DEF_MOD("cmt3", 300, R8A7795_CLK_R), 153 DEF_MOD("cmt2", 301, R8A7795_CLK_R), 154 DEF_MOD("cmt1", 302, R8A7795_CLK_R), 155 DEF_MOD("cmt0", 303, R8A7795_CLK_R), 156 DEF_MOD("tpu0", 304, R8A7795_CLK_S3D4), 157 DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), 158 DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), 159 DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), 160 DEF_MOD("sdif1", 313, R8A7795_CLK_SD1), 161 DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), 162 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), 163 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), 164 DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1), 165 DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */ 166 DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), 167 DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1), 168 DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), 169 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), 170 DEF_MOD("rwdt", 402, R8A7795_CLK_R), 171 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), 172 DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3), 173 DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2), 174 DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2), 175 DEF_MOD("drif31", 508, R8A7795_CLK_S3D2), 176 DEF_MOD("drif30", 509, R8A7795_CLK_S3D2), 177 DEF_MOD("drif21", 510, R8A7795_CLK_S3D2), 178 DEF_MOD("drif20", 511, R8A7795_CLK_S3D2), 179 DEF_MOD("drif11", 512, R8A7795_CLK_S3D2), 180 DEF_MOD("drif10", 513, R8A7795_CLK_S3D2), 181 DEF_MOD("drif01", 514, R8A7795_CLK_S3D2), 182 DEF_MOD("drif00", 515, R8A7795_CLK_S3D2), 183 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), 184 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), 185 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), 186 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), 187 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), 188 DEF_MOD("thermal", 522, R8A7795_CLK_CP), 189 DEF_MOD("pwm", 523, R8A7795_CLK_S0D12), 190 DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */ 191 DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2), 192 DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2), 193 DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2), 194 DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1), 195 DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1), 196 DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */ 197 DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1), 198 DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1), 199 DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */ 200 DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1), 201 DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1), 202 DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */ 203 DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */ 204 DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1), 205 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */ 206 DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2), 207 DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2), 208 DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2), 209 DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1), 210 DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1), 211 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ 212 DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), 213 DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), 214 DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2), 215 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2), 216 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2), 217 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2), 218 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2), 219 DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2), 220 DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1), 221 DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1), 222 DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1), 223 DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1), 224 DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ 225 DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), 226 DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), 227 DEF_MOD("csi40", 716, R8A7795_CLK_CSI0), 228 DEF_MOD("du3", 721, R8A7795_CLK_S2D1), 229 DEF_MOD("du2", 722, R8A7795_CLK_S2D1), 230 DEF_MOD("du1", 723, R8A7795_CLK_S2D1), 231 DEF_MOD("du0", 724, R8A7795_CLK_S2D1), 232 DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), 233 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), 234 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), 235 DEF_MOD("mlp", 802, R8A7795_CLK_S2D1), 236 DEF_MOD("vin7", 804, R8A7795_CLK_S0D2), 237 DEF_MOD("vin6", 805, R8A7795_CLK_S0D2), 238 DEF_MOD("vin5", 806, R8A7795_CLK_S0D2), 239 DEF_MOD("vin4", 807, R8A7795_CLK_S0D2), 240 DEF_MOD("vin3", 808, R8A7795_CLK_S0D2), 241 DEF_MOD("vin2", 809, R8A7795_CLK_S0D2), 242 DEF_MOD("vin1", 810, R8A7795_CLK_S0D2), 243 DEF_MOD("vin0", 811, R8A7795_CLK_S0D2), 244 DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6), 245 DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), 246 DEF_MOD("imr3", 820, R8A7795_CLK_S0D2), 247 DEF_MOD("imr2", 821, R8A7795_CLK_S0D2), 248 DEF_MOD("imr1", 822, R8A7795_CLK_S0D2), 249 DEF_MOD("imr0", 823, R8A7795_CLK_S0D2), 250 DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4), 251 DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4), 252 DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4), 253 DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4), 254 DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4), 255 DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4), 256 DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4), 257 DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4), 258 DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), 259 DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), 260 DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), 261 DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2), 262 DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6), 263 DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6), 264 DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP), 265 DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6), 266 DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6), 267 DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2), 268 DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2), 269 DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2), 270 DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4), 271 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 272 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 273 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 274 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 275 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 276 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 277 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 278 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 279 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 280 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 281 DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4), 282 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 283 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 284 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 285 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 286 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 287 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 288 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 289 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 290 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 291 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 292 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 293 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 294 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 295 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 296 }; 297 298 static const unsigned int r8a7795_crit_mod_clks[] __initconst = { 299 MOD_CLK_ID(402), /* RWDT */ 300 MOD_CLK_ID(408), /* INTC-AP (GIC) */ 301 }; 302 303 /* 304 * CPG Clock Data 305 */ 306 307 /* 308 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC 309 * 14 13 19 17 (MHz) 310 *------------------------------------------------------------------------- 311 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16 312 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16 313 * 0 0 1 0 Prohibited setting 314 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16 315 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19 316 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19 317 * 0 1 1 0 Prohibited setting 318 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19 319 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24 320 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24 321 * 1 0 1 0 Prohibited setting 322 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24 323 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32 324 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32 325 * 1 1 1 0 Prohibited setting 326 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32 327 */ 328 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ 329 (((md) & BIT(13)) >> 11) | \ 330 (((md) & BIT(19)) >> 18) | \ 331 (((md) & BIT(17)) >> 17)) 332 333 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { 334 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ 335 { 1, 192, 1, 192, 1, 16, }, 336 { 1, 192, 1, 128, 1, 16, }, 337 { 0, /* Prohibited setting */ }, 338 { 1, 192, 1, 192, 1, 16, }, 339 { 1, 160, 1, 160, 1, 19, }, 340 { 1, 160, 1, 106, 1, 19, }, 341 { 0, /* Prohibited setting */ }, 342 { 1, 160, 1, 160, 1, 19, }, 343 { 1, 128, 1, 128, 1, 24, }, 344 { 1, 128, 1, 84, 1, 24, }, 345 { 0, /* Prohibited setting */ }, 346 { 1, 128, 1, 128, 1, 24, }, 347 { 2, 192, 1, 192, 1, 32, }, 348 { 2, 192, 1, 128, 1, 32, }, 349 { 0, /* Prohibited setting */ }, 350 { 2, 192, 1, 192, 1, 32, }, 351 }; 352 353 static const struct soc_device_attribute r8a7795es1[] __initconst = { 354 { .soc_id = "r8a7795", .revision = "ES1.*" }, 355 { /* sentinel */ } 356 }; 357 358 359 /* 360 * Fixups for R-Car H3 ES1.x 361 */ 362 363 static const unsigned int r8a7795es1_mod_nullify[] __initconst = { 364 MOD_CLK_ID(326), /* USB-DMAC3-0 */ 365 MOD_CLK_ID(329), /* USB-DMAC3-1 */ 366 MOD_CLK_ID(700), /* EHCI/OHCI3 */ 367 MOD_CLK_ID(705), /* HS-USB-IF3 */ 368 369 }; 370 371 static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = { 372 { MOD_CLK_ID(118), R8A7795_CLK_S2D1 }, /* FDP1-1 */ 373 { MOD_CLK_ID(119), R8A7795_CLK_S2D1 }, /* FDP1-0 */ 374 { MOD_CLK_ID(121), R8A7795_CLK_S3D2 }, /* TMU4 */ 375 { MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */ 376 { MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */ 377 { MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */ 378 { MOD_CLK_ID(408), R8A7795_CLK_S3D1 }, /* INTC-AP */ 379 { MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */ 380 { MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */ 381 { MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */ 382 { MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */ 383 { MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */ 384 { MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */ 385 { MOD_CLK_ID(606), R8A7795_CLK_S2D1 }, /* FCPVB1 */ 386 { MOD_CLK_ID(607), R8A7795_CLK_S2D1 }, /* FCPVB0 */ 387 { MOD_CLK_ID(610), R8A7795_CLK_S2D1 }, /* FCPVI1 */ 388 { MOD_CLK_ID(611), R8A7795_CLK_S2D1 }, /* FCPVI0 */ 389 { MOD_CLK_ID(614), R8A7795_CLK_S2D1 }, /* FCPF1 */ 390 { MOD_CLK_ID(615), R8A7795_CLK_S2D1 }, /* FCPF0 */ 391 { MOD_CLK_ID(619), R8A7795_CLK_S2D1 }, /* FCPCS */ 392 { MOD_CLK_ID(621), R8A7795_CLK_S2D1 }, /* VSPD2 */ 393 { MOD_CLK_ID(622), R8A7795_CLK_S2D1 }, /* VSPD1 */ 394 { MOD_CLK_ID(623), R8A7795_CLK_S2D1 }, /* VSPD0 */ 395 { MOD_CLK_ID(624), R8A7795_CLK_S2D1 }, /* VSPBC */ 396 { MOD_CLK_ID(626), R8A7795_CLK_S2D1 }, /* VSPBD */ 397 { MOD_CLK_ID(630), R8A7795_CLK_S2D1 }, /* VSPI1 */ 398 { MOD_CLK_ID(631), R8A7795_CLK_S2D1 }, /* VSPI0 */ 399 { MOD_CLK_ID(804), R8A7795_CLK_S2D1 }, /* VIN7 */ 400 { MOD_CLK_ID(805), R8A7795_CLK_S2D1 }, /* VIN6 */ 401 { MOD_CLK_ID(806), R8A7795_CLK_S2D1 }, /* VIN5 */ 402 { MOD_CLK_ID(807), R8A7795_CLK_S2D1 }, /* VIN4 */ 403 { MOD_CLK_ID(808), R8A7795_CLK_S2D1 }, /* VIN3 */ 404 { MOD_CLK_ID(809), R8A7795_CLK_S2D1 }, /* VIN2 */ 405 { MOD_CLK_ID(810), R8A7795_CLK_S2D1 }, /* VIN1 */ 406 { MOD_CLK_ID(811), R8A7795_CLK_S2D1 }, /* VIN0 */ 407 { MOD_CLK_ID(812), R8A7795_CLK_S3D2 }, /* EAVB-IF */ 408 { MOD_CLK_ID(820), R8A7795_CLK_S2D1 }, /* IMR3 */ 409 { MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */ 410 { MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */ 411 { MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */ 412 { MOD_CLK_ID(905), R8A7795_CLK_CP }, /* GPIO7 */ 413 { MOD_CLK_ID(906), R8A7795_CLK_CP }, /* GPIO6 */ 414 { MOD_CLK_ID(907), R8A7795_CLK_CP }, /* GPIO5 */ 415 { MOD_CLK_ID(908), R8A7795_CLK_CP }, /* GPIO4 */ 416 { MOD_CLK_ID(909), R8A7795_CLK_CP }, /* GPIO3 */ 417 { MOD_CLK_ID(910), R8A7795_CLK_CP }, /* GPIO2 */ 418 { MOD_CLK_ID(911), R8A7795_CLK_CP }, /* GPIO1 */ 419 { MOD_CLK_ID(912), R8A7795_CLK_CP }, /* GPIO0 */ 420 { MOD_CLK_ID(918), R8A7795_CLK_S3D2 }, /* I2C6 */ 421 { MOD_CLK_ID(919), R8A7795_CLK_S3D2 }, /* I2C5 */ 422 { MOD_CLK_ID(927), R8A7795_CLK_S3D2 }, /* I2C4 */ 423 { MOD_CLK_ID(928), R8A7795_CLK_S3D2 }, /* I2C3 */ 424 }; 425 426 427 /* 428 * Fixups for R-Car H3 ES2.x 429 */ 430 431 static const unsigned int r8a7795es2_mod_nullify[] __initconst = { 432 MOD_CLK_ID(117), /* FDP1-2 */ 433 MOD_CLK_ID(327), /* USB3-IF1 */ 434 MOD_CLK_ID(600), /* FCPVD3 */ 435 MOD_CLK_ID(609), /* FCPVI2 */ 436 MOD_CLK_ID(613), /* FCPF2 */ 437 MOD_CLK_ID(616), /* FCPCI1 */ 438 MOD_CLK_ID(617), /* FCPCI0 */ 439 MOD_CLK_ID(620), /* VSPD3 */ 440 MOD_CLK_ID(629), /* VSPI2 */ 441 MOD_CLK_ID(713), /* CSI21 */ 442 }; 443 444 static int __init r8a7795_cpg_mssr_init(struct device *dev) 445 { 446 const struct rcar_gen3_cpg_pll_config *cpg_pll_config; 447 u32 cpg_mode; 448 int error; 449 450 error = rcar_rst_read_mode_pins(&cpg_mode); 451 if (error) 452 return error; 453 454 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 455 if (!cpg_pll_config->extal_div) { 456 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); 457 return -EINVAL; 458 } 459 460 if (soc_device_match(r8a7795es1)) { 461 cpg_core_nullify_range(r8a7795_core_clks, 462 ARRAY_SIZE(r8a7795_core_clks), 463 R8A7795_CLK_S0D2, R8A7795_CLK_S0D12); 464 mssr_mod_nullify(r8a7795_mod_clks, 465 ARRAY_SIZE(r8a7795_mod_clks), 466 r8a7795es1_mod_nullify, 467 ARRAY_SIZE(r8a7795es1_mod_nullify)); 468 mssr_mod_reparent(r8a7795_mod_clks, 469 ARRAY_SIZE(r8a7795_mod_clks), 470 r8a7795es1_mod_reparent, 471 ARRAY_SIZE(r8a7795es1_mod_reparent)); 472 } else { 473 mssr_mod_nullify(r8a7795_mod_clks, 474 ARRAY_SIZE(r8a7795_mod_clks), 475 r8a7795es2_mod_nullify, 476 ARRAY_SIZE(r8a7795es2_mod_nullify)); 477 } 478 479 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); 480 } 481 482 const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = { 483 /* Core Clocks */ 484 .core_clks = r8a7795_core_clks, 485 .num_core_clks = ARRAY_SIZE(r8a7795_core_clks), 486 .last_dt_core_clk = LAST_DT_CORE_CLK, 487 .num_total_core_clks = MOD_CLK_BASE, 488 489 /* Module Clocks */ 490 .mod_clks = r8a7795_mod_clks, 491 .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks), 492 .num_hw_mod_clks = 12 * 32, 493 494 /* Critical Module Clocks */ 495 .crit_mod_clks = r8a7795_crit_mod_clks, 496 .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks), 497 498 /* Callbacks */ 499 .init = r8a7795_cpg_mssr_init, 500 .cpg_clk_register = rcar_gen3_cpg_clk_register, 501 }; 502