1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2015 Glider bvba 6 * Copyright (C) 2018-2019 Renesas Electronics Corp. 7 * 8 * Based on clk-rcar-gen3.c 9 * 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/device.h> 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/soc/renesas/rcar-rst.h> 17 #include <linux/sys_soc.h> 18 19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 20 21 #include "renesas-cpg-mssr.h" 22 #include "rcar-gen3-cpg.h" 23 24 enum clk_ids { 25 /* Core Clock Outputs exported to DT */ 26 LAST_DT_CORE_CLK = R8A7795_CLK_S0D12, 27 28 /* External Input Clocks */ 29 CLK_EXTAL, 30 CLK_EXTALR, 31 32 /* Internal Core Clocks */ 33 CLK_MAIN, 34 CLK_PLL0, 35 CLK_PLL1, 36 CLK_PLL2, 37 CLK_PLL3, 38 CLK_PLL4, 39 CLK_PLL1_DIV2, 40 CLK_PLL1_DIV4, 41 CLK_S0, 42 CLK_S1, 43 CLK_S2, 44 CLK_S3, 45 CLK_SDSRC, 46 CLK_SSPSRC, 47 CLK_RINT, 48 49 /* Module Clocks */ 50 MOD_CLK_BASE 51 }; 52 53 static struct cpg_core_clk r8a7795_core_clks[] __initdata = { 54 /* External Clock Inputs */ 55 DEF_INPUT("extal", CLK_EXTAL), 56 DEF_INPUT("extalr", CLK_EXTALR), 57 58 /* Internal Core Clocks */ 59 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 60 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 62 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 63 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 64 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), 65 66 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 67 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 68 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 69 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), 70 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), 71 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 72 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 73 74 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), 75 76 /* Core Clock Outputs */ 77 DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), 78 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 79 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 80 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 81 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 82 DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1), 83 DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1), 84 DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1), 85 DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1), 86 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1), 87 DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1), 88 DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1), 89 DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1), 90 DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1), 91 DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1), 92 DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1), 93 DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1), 94 DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1), 95 DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1), 96 DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1), 97 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), 98 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), 99 100 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074), 101 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078), 102 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268), 103 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c), 104 105 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), 106 DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1), 107 DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), 108 DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1), 109 110 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 111 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), 112 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), 113 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), 114 115 DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8), 116 117 DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 118 }; 119 120 static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 121 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */ 122 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), 123 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), 124 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), 125 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), 126 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), 127 DEF_MOD("scif1", 206, R8A7795_CLK_S3D4), 128 DEF_MOD("scif0", 207, R8A7795_CLK_S3D4), 129 DEF_MOD("msiof3", 208, R8A7795_CLK_MSO), 130 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), 131 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), 132 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), 133 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1), 134 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1), 135 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3), 136 DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR), 137 DEF_MOD("cmt3", 300, R8A7795_CLK_R), 138 DEF_MOD("cmt2", 301, R8A7795_CLK_R), 139 DEF_MOD("cmt1", 302, R8A7795_CLK_R), 140 DEF_MOD("cmt0", 303, R8A7795_CLK_R), 141 DEF_MOD("tpu0", 304, R8A7795_CLK_S3D4), 142 DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), 143 DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), 144 DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), 145 DEF_MOD("sdif1", 313, R8A7795_CLK_SD1), 146 DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), 147 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), 148 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), 149 DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1), 150 DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */ 151 DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), 152 DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1), 153 DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), 154 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), 155 DEF_MOD("rwdt", 402, R8A7795_CLK_R), 156 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), 157 DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3), 158 DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2), 159 DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2), 160 DEF_MOD("drif31", 508, R8A7795_CLK_S3D2), 161 DEF_MOD("drif30", 509, R8A7795_CLK_S3D2), 162 DEF_MOD("drif21", 510, R8A7795_CLK_S3D2), 163 DEF_MOD("drif20", 511, R8A7795_CLK_S3D2), 164 DEF_MOD("drif11", 512, R8A7795_CLK_S3D2), 165 DEF_MOD("drif10", 513, R8A7795_CLK_S3D2), 166 DEF_MOD("drif01", 514, R8A7795_CLK_S3D2), 167 DEF_MOD("drif00", 515, R8A7795_CLK_S3D2), 168 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), 169 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), 170 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), 171 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), 172 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), 173 DEF_MOD("thermal", 522, R8A7795_CLK_CP), 174 DEF_MOD("pwm", 523, R8A7795_CLK_S0D12), 175 DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */ 176 DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2), 177 DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2), 178 DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2), 179 DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1), 180 DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1), 181 DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */ 182 DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1), 183 DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1), 184 DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */ 185 DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1), 186 DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1), 187 DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */ 188 DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */ 189 DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1), 190 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */ 191 DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2), 192 DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2), 193 DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2), 194 DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1), 195 DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1), 196 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ 197 DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), 198 DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), 199 DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2), 200 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2), 201 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2), 202 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2), 203 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2), 204 DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2), 205 DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1), 206 DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1), 207 DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1), 208 DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1), 209 DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ 210 DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), 211 DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), 212 DEF_MOD("csi40", 716, R8A7795_CLK_CSI0), 213 DEF_MOD("du3", 721, R8A7795_CLK_S2D1), 214 DEF_MOD("du2", 722, R8A7795_CLK_S2D1), 215 DEF_MOD("du1", 723, R8A7795_CLK_S2D1), 216 DEF_MOD("du0", 724, R8A7795_CLK_S2D1), 217 DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), 218 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), 219 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), 220 DEF_MOD("vin7", 804, R8A7795_CLK_S0D2), 221 DEF_MOD("vin6", 805, R8A7795_CLK_S0D2), 222 DEF_MOD("vin5", 806, R8A7795_CLK_S0D2), 223 DEF_MOD("vin4", 807, R8A7795_CLK_S0D2), 224 DEF_MOD("vin3", 808, R8A7795_CLK_S0D2), 225 DEF_MOD("vin2", 809, R8A7795_CLK_S0D2), 226 DEF_MOD("vin1", 810, R8A7795_CLK_S0D2), 227 DEF_MOD("vin0", 811, R8A7795_CLK_S0D2), 228 DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6), 229 DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), 230 DEF_MOD("imr3", 820, R8A7795_CLK_S0D2), 231 DEF_MOD("imr2", 821, R8A7795_CLK_S0D2), 232 DEF_MOD("imr1", 822, R8A7795_CLK_S0D2), 233 DEF_MOD("imr0", 823, R8A7795_CLK_S0D2), 234 DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4), 235 DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4), 236 DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4), 237 DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4), 238 DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4), 239 DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4), 240 DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4), 241 DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4), 242 DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), 243 DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), 244 DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), 245 DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6), 246 DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6), 247 DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP), 248 DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6), 249 DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6), 250 DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2), 251 DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2), 252 DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2), 253 DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4), 254 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 255 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 256 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 257 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 258 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 259 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 260 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 261 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 262 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 263 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 264 DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4), 265 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 266 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 267 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 268 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 269 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 270 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 271 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 272 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 273 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 274 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 275 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 276 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 277 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 278 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 279 }; 280 281 static const unsigned int r8a7795_crit_mod_clks[] __initconst = { 282 MOD_CLK_ID(408), /* INTC-AP (GIC) */ 283 }; 284 285 286 /* 287 * CPG Clock Data 288 */ 289 290 /* 291 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC 292 * 14 13 19 17 (MHz) 293 *------------------------------------------------------------------------- 294 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16 295 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16 296 * 0 0 1 0 Prohibited setting 297 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16 298 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19 299 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19 300 * 0 1 1 0 Prohibited setting 301 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19 302 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24 303 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24 304 * 1 0 1 0 Prohibited setting 305 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24 306 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32 307 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32 308 * 1 1 1 0 Prohibited setting 309 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32 310 */ 311 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ 312 (((md) & BIT(13)) >> 11) | \ 313 (((md) & BIT(19)) >> 18) | \ 314 (((md) & BIT(17)) >> 17)) 315 316 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { 317 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ 318 { 1, 192, 1, 192, 1, 16, }, 319 { 1, 192, 1, 128, 1, 16, }, 320 { 0, /* Prohibited setting */ }, 321 { 1, 192, 1, 192, 1, 16, }, 322 { 1, 160, 1, 160, 1, 19, }, 323 { 1, 160, 1, 106, 1, 19, }, 324 { 0, /* Prohibited setting */ }, 325 { 1, 160, 1, 160, 1, 19, }, 326 { 1, 128, 1, 128, 1, 24, }, 327 { 1, 128, 1, 84, 1, 24, }, 328 { 0, /* Prohibited setting */ }, 329 { 1, 128, 1, 128, 1, 24, }, 330 { 2, 192, 1, 192, 1, 32, }, 331 { 2, 192, 1, 128, 1, 32, }, 332 { 0, /* Prohibited setting */ }, 333 { 2, 192, 1, 192, 1, 32, }, 334 }; 335 336 static const struct soc_device_attribute r8a7795es1[] __initconst = { 337 { .soc_id = "r8a7795", .revision = "ES1.*" }, 338 { /* sentinel */ } 339 }; 340 341 342 /* 343 * Fixups for R-Car H3 ES1.x 344 */ 345 346 static const unsigned int r8a7795es1_mod_nullify[] __initconst = { 347 MOD_CLK_ID(326), /* USB-DMAC3-0 */ 348 MOD_CLK_ID(329), /* USB-DMAC3-1 */ 349 MOD_CLK_ID(700), /* EHCI/OHCI3 */ 350 MOD_CLK_ID(705), /* HS-USB-IF3 */ 351 352 }; 353 354 static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = { 355 { MOD_CLK_ID(118), R8A7795_CLK_S2D1 }, /* FDP1-1 */ 356 { MOD_CLK_ID(119), R8A7795_CLK_S2D1 }, /* FDP1-0 */ 357 { MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */ 358 { MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */ 359 { MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */ 360 { MOD_CLK_ID(408), R8A7795_CLK_S3D1 }, /* INTC-AP */ 361 { MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */ 362 { MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */ 363 { MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */ 364 { MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */ 365 { MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */ 366 { MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */ 367 { MOD_CLK_ID(606), R8A7795_CLK_S2D1 }, /* FCPVB1 */ 368 { MOD_CLK_ID(607), R8A7795_CLK_S2D1 }, /* FCPVB0 */ 369 { MOD_CLK_ID(610), R8A7795_CLK_S2D1 }, /* FCPVI1 */ 370 { MOD_CLK_ID(611), R8A7795_CLK_S2D1 }, /* FCPVI0 */ 371 { MOD_CLK_ID(614), R8A7795_CLK_S2D1 }, /* FCPF1 */ 372 { MOD_CLK_ID(615), R8A7795_CLK_S2D1 }, /* FCPF0 */ 373 { MOD_CLK_ID(619), R8A7795_CLK_S2D1 }, /* FCPCS */ 374 { MOD_CLK_ID(621), R8A7795_CLK_S2D1 }, /* VSPD2 */ 375 { MOD_CLK_ID(622), R8A7795_CLK_S2D1 }, /* VSPD1 */ 376 { MOD_CLK_ID(623), R8A7795_CLK_S2D1 }, /* VSPD0 */ 377 { MOD_CLK_ID(624), R8A7795_CLK_S2D1 }, /* VSPBC */ 378 { MOD_CLK_ID(626), R8A7795_CLK_S2D1 }, /* VSPBD */ 379 { MOD_CLK_ID(630), R8A7795_CLK_S2D1 }, /* VSPI1 */ 380 { MOD_CLK_ID(631), R8A7795_CLK_S2D1 }, /* VSPI0 */ 381 { MOD_CLK_ID(804), R8A7795_CLK_S2D1 }, /* VIN7 */ 382 { MOD_CLK_ID(805), R8A7795_CLK_S2D1 }, /* VIN6 */ 383 { MOD_CLK_ID(806), R8A7795_CLK_S2D1 }, /* VIN5 */ 384 { MOD_CLK_ID(807), R8A7795_CLK_S2D1 }, /* VIN4 */ 385 { MOD_CLK_ID(808), R8A7795_CLK_S2D1 }, /* VIN3 */ 386 { MOD_CLK_ID(809), R8A7795_CLK_S2D1 }, /* VIN2 */ 387 { MOD_CLK_ID(810), R8A7795_CLK_S2D1 }, /* VIN1 */ 388 { MOD_CLK_ID(811), R8A7795_CLK_S2D1 }, /* VIN0 */ 389 { MOD_CLK_ID(812), R8A7795_CLK_S3D2 }, /* EAVB-IF */ 390 { MOD_CLK_ID(820), R8A7795_CLK_S2D1 }, /* IMR3 */ 391 { MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */ 392 { MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */ 393 { MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */ 394 { MOD_CLK_ID(905), R8A7795_CLK_CP }, /* GPIO7 */ 395 { MOD_CLK_ID(906), R8A7795_CLK_CP }, /* GPIO6 */ 396 { MOD_CLK_ID(907), R8A7795_CLK_CP }, /* GPIO5 */ 397 { MOD_CLK_ID(908), R8A7795_CLK_CP }, /* GPIO4 */ 398 { MOD_CLK_ID(909), R8A7795_CLK_CP }, /* GPIO3 */ 399 { MOD_CLK_ID(910), R8A7795_CLK_CP }, /* GPIO2 */ 400 { MOD_CLK_ID(911), R8A7795_CLK_CP }, /* GPIO1 */ 401 { MOD_CLK_ID(912), R8A7795_CLK_CP }, /* GPIO0 */ 402 { MOD_CLK_ID(918), R8A7795_CLK_S3D2 }, /* I2C6 */ 403 { MOD_CLK_ID(919), R8A7795_CLK_S3D2 }, /* I2C5 */ 404 { MOD_CLK_ID(927), R8A7795_CLK_S3D2 }, /* I2C4 */ 405 { MOD_CLK_ID(928), R8A7795_CLK_S3D2 }, /* I2C3 */ 406 }; 407 408 409 /* 410 * Fixups for R-Car H3 ES2.x 411 */ 412 413 static const unsigned int r8a7795es2_mod_nullify[] __initconst = { 414 MOD_CLK_ID(117), /* FDP1-2 */ 415 MOD_CLK_ID(327), /* USB3-IF1 */ 416 MOD_CLK_ID(600), /* FCPVD3 */ 417 MOD_CLK_ID(609), /* FCPVI2 */ 418 MOD_CLK_ID(613), /* FCPF2 */ 419 MOD_CLK_ID(616), /* FCPCI1 */ 420 MOD_CLK_ID(617), /* FCPCI0 */ 421 MOD_CLK_ID(620), /* VSPD3 */ 422 MOD_CLK_ID(629), /* VSPI2 */ 423 MOD_CLK_ID(713), /* CSI21 */ 424 }; 425 426 static int __init r8a7795_cpg_mssr_init(struct device *dev) 427 { 428 const struct rcar_gen3_cpg_pll_config *cpg_pll_config; 429 u32 cpg_mode; 430 int error; 431 432 error = rcar_rst_read_mode_pins(&cpg_mode); 433 if (error) 434 return error; 435 436 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 437 if (!cpg_pll_config->extal_div) { 438 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); 439 return -EINVAL; 440 } 441 442 if (soc_device_match(r8a7795es1)) { 443 cpg_core_nullify_range(r8a7795_core_clks, 444 ARRAY_SIZE(r8a7795_core_clks), 445 R8A7795_CLK_S0D2, R8A7795_CLK_S0D12); 446 mssr_mod_nullify(r8a7795_mod_clks, 447 ARRAY_SIZE(r8a7795_mod_clks), 448 r8a7795es1_mod_nullify, 449 ARRAY_SIZE(r8a7795es1_mod_nullify)); 450 mssr_mod_reparent(r8a7795_mod_clks, 451 ARRAY_SIZE(r8a7795_mod_clks), 452 r8a7795es1_mod_reparent, 453 ARRAY_SIZE(r8a7795es1_mod_reparent)); 454 } else { 455 mssr_mod_nullify(r8a7795_mod_clks, 456 ARRAY_SIZE(r8a7795_mod_clks), 457 r8a7795es2_mod_nullify, 458 ARRAY_SIZE(r8a7795es2_mod_nullify)); 459 } 460 461 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); 462 } 463 464 const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = { 465 /* Core Clocks */ 466 .core_clks = r8a7795_core_clks, 467 .num_core_clks = ARRAY_SIZE(r8a7795_core_clks), 468 .last_dt_core_clk = LAST_DT_CORE_CLK, 469 .num_total_core_clks = MOD_CLK_BASE, 470 471 /* Module Clocks */ 472 .mod_clks = r8a7795_mod_clks, 473 .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks), 474 .num_hw_mod_clks = 12 * 32, 475 476 /* Critical Module Clocks */ 477 .crit_mod_clks = r8a7795_crit_mod_clks, 478 .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks), 479 480 /* Callbacks */ 481 .init = r8a7795_cpg_mssr_init, 482 .cpg_clk_register = rcar_gen3_cpg_clk_register, 483 }; 484