1 /* 2 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset 3 * 4 * Copyright (C) 2015 Glider bvba 5 * 6 * Based on clk-rcar-gen3.c 7 * 8 * Copyright (C) 2015 Renesas Electronics Corp. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; version 2 of the License. 13 */ 14 15 #include <linux/device.h> 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/soc/renesas/rcar-rst.h> 19 20 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 21 22 #include "renesas-cpg-mssr.h" 23 #include "rcar-gen3-cpg.h" 24 25 enum clk_ids { 26 /* Core Clock Outputs exported to DT */ 27 LAST_DT_CORE_CLK = R8A7795_CLK_OSC, 28 29 /* External Input Clocks */ 30 CLK_EXTAL, 31 CLK_EXTALR, 32 33 /* Internal Core Clocks */ 34 CLK_MAIN, 35 CLK_PLL0, 36 CLK_PLL1, 37 CLK_PLL2, 38 CLK_PLL3, 39 CLK_PLL4, 40 CLK_PLL1_DIV2, 41 CLK_PLL1_DIV4, 42 CLK_S0, 43 CLK_S1, 44 CLK_S2, 45 CLK_S3, 46 CLK_SDSRC, 47 CLK_SSPSRC, 48 CLK_RINT, 49 50 /* Module Clocks */ 51 MOD_CLK_BASE 52 }; 53 54 static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { 55 /* External Clock Inputs */ 56 DEF_INPUT("extal", CLK_EXTAL), 57 DEF_INPUT("extalr", CLK_EXTALR), 58 59 /* Internal Core Clocks */ 60 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 61 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 62 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 63 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 64 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 65 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), 66 67 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 68 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 69 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 70 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), 71 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), 72 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 73 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 74 75 /* Core Clock Outputs */ 76 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 77 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 78 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 79 DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1), 80 DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1), 81 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1), 82 DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1), 83 DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1), 84 DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1), 85 DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1), 86 DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1), 87 DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1), 88 DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1), 89 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), 90 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), 91 92 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x0074), 93 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x0078), 94 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x0268), 95 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x026c), 96 97 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), 98 DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), 99 100 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), 101 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), 102 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 103 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), 104 105 DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), 106 DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), 107 108 DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 109 }; 110 111 static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { 112 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), 113 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S2D1), 114 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S2D1), 115 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), 116 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), 117 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), 118 DEF_MOD("scif1", 206, R8A7795_CLK_S3D4), 119 DEF_MOD("scif0", 207, R8A7795_CLK_S3D4), 120 DEF_MOD("msiof3", 208, R8A7795_CLK_MSO), 121 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), 122 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), 123 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), 124 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1), 125 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1), 126 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1), 127 DEF_MOD("cmt3", 300, R8A7795_CLK_R), 128 DEF_MOD("cmt2", 301, R8A7795_CLK_R), 129 DEF_MOD("cmt1", 302, R8A7795_CLK_R), 130 DEF_MOD("cmt0", 303, R8A7795_CLK_R), 131 DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), 132 DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), 133 DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), 134 DEF_MOD("sdif1", 313, R8A7795_CLK_SD1), 135 DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), 136 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), 137 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), 138 DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), 139 DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), 140 DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), 141 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), 142 DEF_MOD("rwdt0", 402, R8A7795_CLK_R), 143 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), 144 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), 145 DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4), 146 DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4), 147 DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), 148 DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), 149 DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), 150 DEF_MOD("drif4", 511, R8A7795_CLK_S3D2), 151 DEF_MOD("drif3", 512, R8A7795_CLK_S3D2), 152 DEF_MOD("drif2", 513, R8A7795_CLK_S3D2), 153 DEF_MOD("drif1", 514, R8A7795_CLK_S3D2), 154 DEF_MOD("drif0", 515, R8A7795_CLK_S3D2), 155 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), 156 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), 157 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), 158 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), 159 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), 160 DEF_MOD("thermal", 522, R8A7795_CLK_CP), 161 DEF_MOD("pwm", 523, R8A7795_CLK_S3D4), 162 DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), 163 DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1), 164 DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1), 165 DEF_MOD("fcpvd0", 603, R8A7795_CLK_S2D1), 166 DEF_MOD("fcpvb1", 606, R8A7795_CLK_S2D1), 167 DEF_MOD("fcpvb0", 607, R8A7795_CLK_S2D1), 168 DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), 169 DEF_MOD("fcpvi1", 610, R8A7795_CLK_S2D1), 170 DEF_MOD("fcpvi0", 611, R8A7795_CLK_S2D1), 171 DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), 172 DEF_MOD("fcpf1", 614, R8A7795_CLK_S2D1), 173 DEF_MOD("fcpf0", 615, R8A7795_CLK_S2D1), 174 DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), 175 DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), 176 DEF_MOD("fcpcs", 619, R8A7795_CLK_S2D1), 177 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), 178 DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1), 179 DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1), 180 DEF_MOD("vspd0", 623, R8A7795_CLK_S2D1), 181 DEF_MOD("vspbc", 624, R8A7795_CLK_S2D1), 182 DEF_MOD("vspbd", 626, R8A7795_CLK_S2D1), 183 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), 184 DEF_MOD("vspi1", 630, R8A7795_CLK_S2D1), 185 DEF_MOD("vspi0", 631, R8A7795_CLK_S2D1), 186 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), 187 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), 188 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), 189 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), 190 DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), 191 DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), 192 DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), 193 DEF_MOD("csi40", 716, R8A7795_CLK_CSI0), 194 DEF_MOD("du3", 721, R8A7795_CLK_S2D1), 195 DEF_MOD("du2", 722, R8A7795_CLK_S2D1), 196 DEF_MOD("du1", 723, R8A7795_CLK_S2D1), 197 DEF_MOD("du0", 724, R8A7795_CLK_S2D1), 198 DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), 199 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), 200 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), 201 DEF_MOD("vin7", 804, R8A7795_CLK_S2D1), 202 DEF_MOD("vin6", 805, R8A7795_CLK_S2D1), 203 DEF_MOD("vin5", 806, R8A7795_CLK_S2D1), 204 DEF_MOD("vin4", 807, R8A7795_CLK_S2D1), 205 DEF_MOD("vin3", 808, R8A7795_CLK_S2D1), 206 DEF_MOD("vin2", 809, R8A7795_CLK_S2D1), 207 DEF_MOD("vin1", 810, R8A7795_CLK_S2D1), 208 DEF_MOD("vin0", 811, R8A7795_CLK_S2D1), 209 DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2), 210 DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), 211 DEF_MOD("gpio7", 905, R8A7795_CLK_CP), 212 DEF_MOD("gpio6", 906, R8A7795_CLK_CP), 213 DEF_MOD("gpio5", 907, R8A7795_CLK_CP), 214 DEF_MOD("gpio4", 908, R8A7795_CLK_CP), 215 DEF_MOD("gpio3", 909, R8A7795_CLK_CP), 216 DEF_MOD("gpio2", 910, R8A7795_CLK_CP), 217 DEF_MOD("gpio1", 911, R8A7795_CLK_CP), 218 DEF_MOD("gpio0", 912, R8A7795_CLK_CP), 219 DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), 220 DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), 221 DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), 222 DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2), 223 DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2), 224 DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2), 225 DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2), 226 DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2), 227 DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2), 228 DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2), 229 DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4), 230 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 231 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 232 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 233 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 234 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 235 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 236 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 237 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 238 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 239 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 240 DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4), 241 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 242 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 243 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 244 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 245 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 246 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 247 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 248 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 249 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 250 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 251 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 252 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 253 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 254 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 255 }; 256 257 static const unsigned int r8a7795_crit_mod_clks[] __initconst = { 258 MOD_CLK_ID(408), /* INTC-AP (GIC) */ 259 }; 260 261 262 /* 263 * CPG Clock Data 264 */ 265 266 /* 267 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 268 * 14 13 19 17 (MHz) 269 *------------------------------------------------------------------- 270 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 271 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 272 * 0 0 1 0 Prohibited setting 273 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 274 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 275 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 276 * 0 1 1 0 Prohibited setting 277 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 278 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 279 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 280 * 1 0 1 0 Prohibited setting 281 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 282 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 283 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 284 * 1 1 1 0 Prohibited setting 285 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 286 */ 287 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ 288 (((md) & BIT(13)) >> 11) | \ 289 (((md) & BIT(19)) >> 18) | \ 290 (((md) & BIT(17)) >> 17)) 291 292 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { 293 /* EXTAL div PLL1 mult PLL3 mult */ 294 { 1, 192, 192, }, 295 { 1, 192, 128, }, 296 { 0, /* Prohibited setting */ }, 297 { 1, 192, 192, }, 298 { 1, 160, 160, }, 299 { 1, 160, 106, }, 300 { 0, /* Prohibited setting */ }, 301 { 1, 160, 160, }, 302 { 1, 128, 128, }, 303 { 1, 128, 84, }, 304 { 0, /* Prohibited setting */ }, 305 { 1, 128, 128, }, 306 { 2, 192, 192, }, 307 { 2, 192, 128, }, 308 { 0, /* Prohibited setting */ }, 309 { 2, 192, 192, }, 310 }; 311 312 static int __init r8a7795_cpg_mssr_init(struct device *dev) 313 { 314 const struct rcar_gen3_cpg_pll_config *cpg_pll_config; 315 u32 cpg_mode; 316 int error; 317 318 error = rcar_rst_read_mode_pins(&cpg_mode); 319 if (error) 320 return error; 321 322 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 323 if (!cpg_pll_config->extal_div) { 324 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); 325 return -EINVAL; 326 } 327 328 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR); 329 } 330 331 const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = { 332 /* Core Clocks */ 333 .core_clks = r8a7795_core_clks, 334 .num_core_clks = ARRAY_SIZE(r8a7795_core_clks), 335 .last_dt_core_clk = LAST_DT_CORE_CLK, 336 .num_total_core_clks = MOD_CLK_BASE, 337 338 /* Module Clocks */ 339 .mod_clks = r8a7795_mod_clks, 340 .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks), 341 .num_hw_mod_clks = 12 * 32, 342 343 /* Critical Module Clocks */ 344 .crit_mod_clks = r8a7795_crit_mod_clks, 345 .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks), 346 347 /* Callbacks */ 348 .init = r8a7795_cpg_mssr_init, 349 .cpg_clk_register = rcar_gen3_cpg_clk_register, 350 }; 351