1906e0a4aSFabrizio Castro // SPDX-License-Identifier: GPL-2.0 2906e0a4aSFabrizio Castro /* 3906e0a4aSFabrizio Castro * r8a774c0 Clock Pulse Generator / Module Standby and Software Reset 4906e0a4aSFabrizio Castro * 5906e0a4aSFabrizio Castro * Copyright (C) 2018 Renesas Electronics Corp. 6906e0a4aSFabrizio Castro * 7906e0a4aSFabrizio Castro * Based on r8a77990-cpg-mssr.c 8906e0a4aSFabrizio Castro * 9906e0a4aSFabrizio Castro * Copyright (C) 2015 Glider bvba 10906e0a4aSFabrizio Castro * Copyright (C) 2015 Renesas Electronics Corp. 11906e0a4aSFabrizio Castro */ 12906e0a4aSFabrizio Castro 13906e0a4aSFabrizio Castro #include <linux/device.h> 14906e0a4aSFabrizio Castro #include <linux/init.h> 15906e0a4aSFabrizio Castro #include <linux/kernel.h> 16906e0a4aSFabrizio Castro #include <linux/soc/renesas/rcar-rst.h> 17906e0a4aSFabrizio Castro 18906e0a4aSFabrizio Castro #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> 19906e0a4aSFabrizio Castro 20906e0a4aSFabrizio Castro #include "renesas-cpg-mssr.h" 21906e0a4aSFabrizio Castro #include "rcar-gen3-cpg.h" 22906e0a4aSFabrizio Castro 23906e0a4aSFabrizio Castro enum clk_ids { 24906e0a4aSFabrizio Castro /* Core Clock Outputs exported to DT */ 25e61b30bbSFabrizio Castro LAST_DT_CORE_CLK = R8A774C0_CLK_CANFD, 26906e0a4aSFabrizio Castro 27906e0a4aSFabrizio Castro /* External Input Clocks */ 28906e0a4aSFabrizio Castro CLK_EXTAL, 29906e0a4aSFabrizio Castro 30906e0a4aSFabrizio Castro /* Internal Core Clocks */ 31906e0a4aSFabrizio Castro CLK_MAIN, 32906e0a4aSFabrizio Castro CLK_PLL0, 33906e0a4aSFabrizio Castro CLK_PLL1, 34906e0a4aSFabrizio Castro CLK_PLL3, 35906e0a4aSFabrizio Castro CLK_PLL0D4, 362a6efbc6SFabrizio Castro CLK_PLL0D6, 37906e0a4aSFabrizio Castro CLK_PLL0D8, 38906e0a4aSFabrizio Castro CLK_PLL0D20, 39906e0a4aSFabrizio Castro CLK_PLL0D24, 40906e0a4aSFabrizio Castro CLK_PLL1D2, 41906e0a4aSFabrizio Castro CLK_PE, 42906e0a4aSFabrizio Castro CLK_S0, 43906e0a4aSFabrizio Castro CLK_S1, 44906e0a4aSFabrizio Castro CLK_S2, 45906e0a4aSFabrizio Castro CLK_S3, 46906e0a4aSFabrizio Castro CLK_SDSRC, 47906e0a4aSFabrizio Castro CLK_RINT, 48906e0a4aSFabrizio Castro CLK_OCO, 49906e0a4aSFabrizio Castro 50906e0a4aSFabrizio Castro /* Module Clocks */ 51906e0a4aSFabrizio Castro MOD_CLK_BASE 52906e0a4aSFabrizio Castro }; 53906e0a4aSFabrizio Castro 54906e0a4aSFabrizio Castro static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { 55906e0a4aSFabrizio Castro /* External Clock Inputs */ 56906e0a4aSFabrizio Castro DEF_INPUT("extal", CLK_EXTAL), 57906e0a4aSFabrizio Castro 58906e0a4aSFabrizio Castro /* Internal Core Clocks */ 59906e0a4aSFabrizio Castro DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 60906e0a4aSFabrizio Castro DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 61906e0a4aSFabrizio Castro DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 62906e0a4aSFabrizio Castro 63906e0a4aSFabrizio Castro DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100), 64906e0a4aSFabrizio Castro DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1), 652a6efbc6SFabrizio Castro DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1), 66906e0a4aSFabrizio Castro DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1), 67906e0a4aSFabrizio Castro DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1), 68906e0a4aSFabrizio Castro DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1), 69906e0a4aSFabrizio Castro DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1), 70906e0a4aSFabrizio Castro DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1), 71906e0a4aSFabrizio Castro DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1), 72906e0a4aSFabrizio Castro DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1), 73906e0a4aSFabrizio Castro DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), 74906e0a4aSFabrizio Castro DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), 75906e0a4aSFabrizio Castro DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), 76906e0a4aSFabrizio Castro 77906e0a4aSFabrizio Castro DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), 78906e0a4aSFabrizio Castro 79906e0a4aSFabrizio Castro DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), 80906e0a4aSFabrizio Castro 81906e0a4aSFabrizio Castro /* Core Clock Outputs */ 82906e0a4aSFabrizio Castro DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1), 83906e0a4aSFabrizio Castro DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1), 844aeed945SSimon Horman DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8), 85906e0a4aSFabrizio Castro DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1), 86906e0a4aSFabrizio Castro DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1), 87906e0a4aSFabrizio Castro DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1), 88906e0a4aSFabrizio Castro DEF_FIXED("s0d1", R8A774C0_CLK_S0D1, CLK_S0, 1, 1), 89906e0a4aSFabrizio Castro DEF_FIXED("s0d3", R8A774C0_CLK_S0D3, CLK_S0, 3, 1), 90906e0a4aSFabrizio Castro DEF_FIXED("s0d6", R8A774C0_CLK_S0D6, CLK_S0, 6, 1), 91906e0a4aSFabrizio Castro DEF_FIXED("s0d12", R8A774C0_CLK_S0D12, CLK_S0, 12, 1), 92906e0a4aSFabrizio Castro DEF_FIXED("s0d24", R8A774C0_CLK_S0D24, CLK_S0, 24, 1), 93906e0a4aSFabrizio Castro DEF_FIXED("s1d1", R8A774C0_CLK_S1D1, CLK_S1, 1, 1), 94906e0a4aSFabrizio Castro DEF_FIXED("s1d2", R8A774C0_CLK_S1D2, CLK_S1, 2, 1), 95906e0a4aSFabrizio Castro DEF_FIXED("s1d4", R8A774C0_CLK_S1D4, CLK_S1, 4, 1), 96906e0a4aSFabrizio Castro DEF_FIXED("s2d1", R8A774C0_CLK_S2D1, CLK_S2, 1, 1), 97906e0a4aSFabrizio Castro DEF_FIXED("s2d2", R8A774C0_CLK_S2D2, CLK_S2, 2, 1), 98906e0a4aSFabrizio Castro DEF_FIXED("s2d4", R8A774C0_CLK_S2D4, CLK_S2, 4, 1), 99906e0a4aSFabrizio Castro DEF_FIXED("s3d1", R8A774C0_CLK_S3D1, CLK_S3, 1, 1), 100906e0a4aSFabrizio Castro DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1), 101906e0a4aSFabrizio Castro DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1), 102906e0a4aSFabrizio Castro 103906e0a4aSFabrizio Castro DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, CLK_SDSRC, 0x0074), 104906e0a4aSFabrizio Castro DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, CLK_SDSRC, 0x0078), 105906e0a4aSFabrizio Castro DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, CLK_SDSRC, 0x026c), 106906e0a4aSFabrizio Castro 107906e0a4aSFabrizio Castro DEF_FIXED("cl", R8A774C0_CLK_CL, CLK_PLL1, 48, 1), 108906e0a4aSFabrizio Castro DEF_FIXED("cp", R8A774C0_CLK_CP, CLK_EXTAL, 2, 1), 109906e0a4aSFabrizio Castro DEF_FIXED("cpex", R8A774C0_CLK_CPEX, CLK_EXTAL, 4, 1), 110906e0a4aSFabrizio Castro 111906e0a4aSFabrizio Castro DEF_DIV6_RO("osc", R8A774C0_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), 112906e0a4aSFabrizio Castro 113906e0a4aSFabrizio Castro DEF_GEN3_PE("s0d6c", R8A774C0_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2), 114906e0a4aSFabrizio Castro DEF_GEN3_PE("s3d1c", R8A774C0_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), 115906e0a4aSFabrizio Castro DEF_GEN3_PE("s3d2c", R8A774C0_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), 116906e0a4aSFabrizio Castro DEF_GEN3_PE("s3d4c", R8A774C0_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), 117906e0a4aSFabrizio Castro 1182a6efbc6SFabrizio Castro DEF_DIV6P1("canfd", R8A774C0_CLK_CANFD, CLK_PLL0D6, 0x244), 119906e0a4aSFabrizio Castro DEF_DIV6P1("csi0", R8A774C0_CLK_CSI0, CLK_PLL1D2, 0x00c), 120906e0a4aSFabrizio Castro DEF_DIV6P1("mso", R8A774C0_CLK_MSO, CLK_PLL1D2, 0x014), 121906e0a4aSFabrizio Castro 122906e0a4aSFabrizio Castro DEF_GEN3_RCKSEL("r", R8A774C0_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4), 123906e0a4aSFabrizio Castro }; 124906e0a4aSFabrizio Castro 125906e0a4aSFabrizio Castro static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { 126d1de227dSBiju Das DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6C), 127d1de227dSBiju Das DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2C), 128d1de227dSBiju Das DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2C), 129d1de227dSBiju Das DEF_MOD("tmu1", 124, R8A774C0_CLK_S3D2C), 130d1de227dSBiju Das DEF_MOD("tmu0", 125, R8A774C0_CLK_CP), 131906e0a4aSFabrizio Castro DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C), 132906e0a4aSFabrizio Castro DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C), 133906e0a4aSFabrizio Castro DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C), 134906e0a4aSFabrizio Castro DEF_MOD("scif1", 206, R8A774C0_CLK_S3D4C), 135906e0a4aSFabrizio Castro DEF_MOD("scif0", 207, R8A774C0_CLK_S3D4C), 136906e0a4aSFabrizio Castro DEF_MOD("msiof3", 208, R8A774C0_CLK_MSO), 137906e0a4aSFabrizio Castro DEF_MOD("msiof2", 209, R8A774C0_CLK_MSO), 138906e0a4aSFabrizio Castro DEF_MOD("msiof1", 210, R8A774C0_CLK_MSO), 139906e0a4aSFabrizio Castro DEF_MOD("msiof0", 211, R8A774C0_CLK_MSO), 140906e0a4aSFabrizio Castro DEF_MOD("sys-dmac2", 217, R8A774C0_CLK_S3D1), 141906e0a4aSFabrizio Castro DEF_MOD("sys-dmac1", 218, R8A774C0_CLK_S3D1), 142906e0a4aSFabrizio Castro DEF_MOD("sys-dmac0", 219, R8A774C0_CLK_S3D1), 143906e0a4aSFabrizio Castro 144906e0a4aSFabrizio Castro DEF_MOD("cmt3", 300, R8A774C0_CLK_R), 145906e0a4aSFabrizio Castro DEF_MOD("cmt2", 301, R8A774C0_CLK_R), 146906e0a4aSFabrizio Castro DEF_MOD("cmt1", 302, R8A774C0_CLK_R), 147906e0a4aSFabrizio Castro DEF_MOD("cmt0", 303, R8A774C0_CLK_R), 148906e0a4aSFabrizio Castro DEF_MOD("scif2", 310, R8A774C0_CLK_S3D4C), 149906e0a4aSFabrizio Castro DEF_MOD("sdif3", 311, R8A774C0_CLK_SD3), 150906e0a4aSFabrizio Castro DEF_MOD("sdif1", 313, R8A774C0_CLK_SD1), 151906e0a4aSFabrizio Castro DEF_MOD("sdif0", 314, R8A774C0_CLK_SD0), 152906e0a4aSFabrizio Castro DEF_MOD("pcie0", 319, R8A774C0_CLK_S3D1), 153906e0a4aSFabrizio Castro DEF_MOD("usb3-if0", 328, R8A774C0_CLK_S3D1), 154906e0a4aSFabrizio Castro DEF_MOD("usb-dmac0", 330, R8A774C0_CLK_S3D1), 155906e0a4aSFabrizio Castro DEF_MOD("usb-dmac1", 331, R8A774C0_CLK_S3D1), 156906e0a4aSFabrizio Castro 157906e0a4aSFabrizio Castro DEF_MOD("rwdt", 402, R8A774C0_CLK_R), 158906e0a4aSFabrizio Castro DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP), 159906e0a4aSFabrizio Castro DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3), 160906e0a4aSFabrizio Castro 161906e0a4aSFabrizio Castro DEF_MOD("audmac0", 502, R8A774C0_CLK_S3D4), 162906e0a4aSFabrizio Castro DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C), 163906e0a4aSFabrizio Castro DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C), 164906e0a4aSFabrizio Castro DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C), 165906e0a4aSFabrizio Castro DEF_MOD("hscif1", 519, R8A774C0_CLK_S3D1C), 166906e0a4aSFabrizio Castro DEF_MOD("hscif0", 520, R8A774C0_CLK_S3D1C), 167906e0a4aSFabrizio Castro DEF_MOD("thermal", 522, R8A774C0_CLK_CP), 168906e0a4aSFabrizio Castro DEF_MOD("pwm", 523, R8A774C0_CLK_S3D4C), 169906e0a4aSFabrizio Castro 170906e0a4aSFabrizio Castro DEF_MOD("fcpvd1", 602, R8A774C0_CLK_S1D2), 171906e0a4aSFabrizio Castro DEF_MOD("fcpvd0", 603, R8A774C0_CLK_S1D2), 172906e0a4aSFabrizio Castro DEF_MOD("fcpvb0", 607, R8A774C0_CLK_S0D1), 173906e0a4aSFabrizio Castro DEF_MOD("fcpvi0", 611, R8A774C0_CLK_S0D1), 174906e0a4aSFabrizio Castro DEF_MOD("fcpf0", 615, R8A774C0_CLK_S0D1), 175906e0a4aSFabrizio Castro DEF_MOD("fcpcs", 619, R8A774C0_CLK_S0D1), 176906e0a4aSFabrizio Castro DEF_MOD("vspd1", 622, R8A774C0_CLK_S1D2), 177906e0a4aSFabrizio Castro DEF_MOD("vspd0", 623, R8A774C0_CLK_S1D2), 178906e0a4aSFabrizio Castro DEF_MOD("vspb", 626, R8A774C0_CLK_S0D1), 179906e0a4aSFabrizio Castro DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1), 180906e0a4aSFabrizio Castro 1818d36fdccSKazuya Mizuguchi DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D2), 182906e0a4aSFabrizio Castro DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D4), 183906e0a4aSFabrizio Castro DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0), 184d9286d97SGeert Uytterhoeven DEF_MOD("du1", 723, R8A774C0_CLK_S1D1), 185d9286d97SGeert Uytterhoeven DEF_MOD("du0", 724, R8A774C0_CLK_S1D1), 186906e0a4aSFabrizio Castro DEF_MOD("lvds", 727, R8A774C0_CLK_S2D1), 187906e0a4aSFabrizio Castro 188906e0a4aSFabrizio Castro DEF_MOD("vin5", 806, R8A774C0_CLK_S1D2), 189906e0a4aSFabrizio Castro DEF_MOD("vin4", 807, R8A774C0_CLK_S1D2), 190906e0a4aSFabrizio Castro DEF_MOD("etheravb", 812, R8A774C0_CLK_S3D2), 191906e0a4aSFabrizio Castro 192906e0a4aSFabrizio Castro DEF_MOD("gpio6", 906, R8A774C0_CLK_S3D4), 193906e0a4aSFabrizio Castro DEF_MOD("gpio5", 907, R8A774C0_CLK_S3D4), 194906e0a4aSFabrizio Castro DEF_MOD("gpio4", 908, R8A774C0_CLK_S3D4), 195906e0a4aSFabrizio Castro DEF_MOD("gpio3", 909, R8A774C0_CLK_S3D4), 196906e0a4aSFabrizio Castro DEF_MOD("gpio2", 910, R8A774C0_CLK_S3D4), 197906e0a4aSFabrizio Castro DEF_MOD("gpio1", 911, R8A774C0_CLK_S3D4), 198906e0a4aSFabrizio Castro DEF_MOD("gpio0", 912, R8A774C0_CLK_S3D4), 1992a6efbc6SFabrizio Castro DEF_MOD("can-fd", 914, R8A774C0_CLK_S3D2), 200906e0a4aSFabrizio Castro DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4), 201906e0a4aSFabrizio Castro DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4), 202906e0a4aSFabrizio Castro DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2), 203906e0a4aSFabrizio Castro DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2), 204906e0a4aSFabrizio Castro DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP), 205906e0a4aSFabrizio Castro DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2), 206906e0a4aSFabrizio Castro DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2), 207906e0a4aSFabrizio Castro DEF_MOD("i2c2", 929, R8A774C0_CLK_S3D2), 208906e0a4aSFabrizio Castro DEF_MOD("i2c1", 930, R8A774C0_CLK_S3D2), 209906e0a4aSFabrizio Castro DEF_MOD("i2c0", 931, R8A774C0_CLK_S3D2), 210906e0a4aSFabrizio Castro 211906e0a4aSFabrizio Castro DEF_MOD("i2c7", 1003, R8A774C0_CLK_S3D2), 212906e0a4aSFabrizio Castro DEF_MOD("ssi-all", 1005, R8A774C0_CLK_S3D4), 213906e0a4aSFabrizio Castro DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 214906e0a4aSFabrizio Castro DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 215906e0a4aSFabrizio Castro DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 216906e0a4aSFabrizio Castro DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 217906e0a4aSFabrizio Castro DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 218906e0a4aSFabrizio Castro DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 219906e0a4aSFabrizio Castro DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 220906e0a4aSFabrizio Castro DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 221906e0a4aSFabrizio Castro DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 222906e0a4aSFabrizio Castro DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 223906e0a4aSFabrizio Castro DEF_MOD("scu-all", 1017, R8A774C0_CLK_S3D4), 224906e0a4aSFabrizio Castro DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 225906e0a4aSFabrizio Castro DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 226906e0a4aSFabrizio Castro DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 227906e0a4aSFabrizio Castro DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 228906e0a4aSFabrizio Castro DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 229906e0a4aSFabrizio Castro DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 230906e0a4aSFabrizio Castro DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 231906e0a4aSFabrizio Castro DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 232906e0a4aSFabrizio Castro DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 233906e0a4aSFabrizio Castro DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 234906e0a4aSFabrizio Castro DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 235906e0a4aSFabrizio Castro DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 236906e0a4aSFabrizio Castro DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 237906e0a4aSFabrizio Castro DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 238906e0a4aSFabrizio Castro }; 239906e0a4aSFabrizio Castro 240906e0a4aSFabrizio Castro static const unsigned int r8a774c0_crit_mod_clks[] __initconst = { 241906e0a4aSFabrizio Castro MOD_CLK_ID(408), /* INTC-AP (GIC) */ 242906e0a4aSFabrizio Castro }; 243906e0a4aSFabrizio Castro 244906e0a4aSFabrizio Castro /* 245906e0a4aSFabrizio Castro * CPG Clock Data 246906e0a4aSFabrizio Castro */ 247906e0a4aSFabrizio Castro 248906e0a4aSFabrizio Castro /* 249906e0a4aSFabrizio Castro * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 250906e0a4aSFabrizio Castro *-------------------------------------------------------------------- 251906e0a4aSFabrizio Castro * 0 48 x 1 x100/1 x100/3 x100/3 252906e0a4aSFabrizio Castro * 1 48 x 1 x100/1 x100/3 x58/3 253906e0a4aSFabrizio Castro */ 254906e0a4aSFabrizio Castro #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) 255906e0a4aSFabrizio Castro 256906e0a4aSFabrizio Castro static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = { 257906e0a4aSFabrizio Castro /* EXTAL div PLL1 mult/div PLL3 mult/div */ 258906e0a4aSFabrizio Castro { 1, 100, 3, 100, 3, }, 259906e0a4aSFabrizio Castro { 1, 100, 3, 58, 3, }, 260906e0a4aSFabrizio Castro }; 261906e0a4aSFabrizio Castro 262906e0a4aSFabrizio Castro static int __init r8a774c0_cpg_mssr_init(struct device *dev) 263906e0a4aSFabrizio Castro { 264906e0a4aSFabrizio Castro const struct rcar_gen3_cpg_pll_config *cpg_pll_config; 265906e0a4aSFabrizio Castro u32 cpg_mode; 266906e0a4aSFabrizio Castro int error; 267906e0a4aSFabrizio Castro 268906e0a4aSFabrizio Castro error = rcar_rst_read_mode_pins(&cpg_mode); 269906e0a4aSFabrizio Castro if (error) 270906e0a4aSFabrizio Castro return error; 271906e0a4aSFabrizio Castro 272906e0a4aSFabrizio Castro cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 273906e0a4aSFabrizio Castro 274906e0a4aSFabrizio Castro return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode); 275906e0a4aSFabrizio Castro } 276906e0a4aSFabrizio Castro 277906e0a4aSFabrizio Castro const struct cpg_mssr_info r8a774c0_cpg_mssr_info __initconst = { 278906e0a4aSFabrizio Castro /* Core Clocks */ 279906e0a4aSFabrizio Castro .core_clks = r8a774c0_core_clks, 280906e0a4aSFabrizio Castro .num_core_clks = ARRAY_SIZE(r8a774c0_core_clks), 281906e0a4aSFabrizio Castro .last_dt_core_clk = LAST_DT_CORE_CLK, 282906e0a4aSFabrizio Castro .num_total_core_clks = MOD_CLK_BASE, 283906e0a4aSFabrizio Castro 284906e0a4aSFabrizio Castro /* Module Clocks */ 285906e0a4aSFabrizio Castro .mod_clks = r8a774c0_mod_clks, 286906e0a4aSFabrizio Castro .num_mod_clks = ARRAY_SIZE(r8a774c0_mod_clks), 287906e0a4aSFabrizio Castro .num_hw_mod_clks = 12 * 32, 288906e0a4aSFabrizio Castro 289906e0a4aSFabrizio Castro /* Critical Module Clocks */ 290906e0a4aSFabrizio Castro .crit_mod_clks = r8a774c0_crit_mod_clks, 291906e0a4aSFabrizio Castro .num_crit_mod_clks = ARRAY_SIZE(r8a774c0_crit_mod_clks), 292906e0a4aSFabrizio Castro 293906e0a4aSFabrizio Castro /* Callbacks */ 294906e0a4aSFabrizio Castro .init = r8a774c0_cpg_mssr_init, 295906e0a4aSFabrizio Castro .cpg_clk_register = rcar_gen3_cpg_clk_register, 296906e0a4aSFabrizio Castro }; 297