1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a774b1 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2019 Renesas Electronics Corp. 6 * 7 * Based on r8a7796-cpg-mssr.c 8 * 9 * Copyright (C) 2016 Glider bvba 10 */ 11 12 #include <linux/device.h> 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <linux/soc/renesas/rcar-rst.h> 16 17 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h> 18 19 #include "renesas-cpg-mssr.h" 20 #include "rcar-gen3-cpg.h" 21 22 enum clk_ids { 23 /* Core Clock Outputs exported to DT */ 24 LAST_DT_CORE_CLK = R8A774B1_CLK_CANFD, 25 26 /* External Input Clocks */ 27 CLK_EXTAL, 28 CLK_EXTALR, 29 30 /* Internal Core Clocks */ 31 CLK_MAIN, 32 CLK_PLL0, 33 CLK_PLL1, 34 CLK_PLL3, 35 CLK_PLL4, 36 CLK_PLL1_DIV2, 37 CLK_PLL1_DIV4, 38 CLK_S0, 39 CLK_S1, 40 CLK_S2, 41 CLK_S3, 42 CLK_SDSRC, 43 CLK_RPCSRC, 44 CLK_RINT, 45 46 /* Module Clocks */ 47 MOD_CLK_BASE 48 }; 49 50 static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { 51 /* External Clock Inputs */ 52 DEF_INPUT("extal", CLK_EXTAL), 53 DEF_INPUT("extalr", CLK_EXTALR), 54 55 /* Internal Core Clocks */ 56 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 57 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 59 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 60 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), 61 62 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 63 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 64 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 65 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), 66 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), 67 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 68 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 69 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), 70 71 DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, 72 CLK_RPCSRC), 73 DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, 74 R8A774B1_CLK_RPC), 75 76 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), 77 78 /* Core Clock Outputs */ 79 DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), 80 DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 81 DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 82 DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 83 DEF_FIXED("zx", R8A774B1_CLK_ZX, CLK_PLL1_DIV2, 2, 1), 84 DEF_FIXED("s0d1", R8A774B1_CLK_S0D1, CLK_S0, 1, 1), 85 DEF_FIXED("s0d2", R8A774B1_CLK_S0D2, CLK_S0, 2, 1), 86 DEF_FIXED("s0d3", R8A774B1_CLK_S0D3, CLK_S0, 3, 1), 87 DEF_FIXED("s0d4", R8A774B1_CLK_S0D4, CLK_S0, 4, 1), 88 DEF_FIXED("s0d6", R8A774B1_CLK_S0D6, CLK_S0, 6, 1), 89 DEF_FIXED("s0d8", R8A774B1_CLK_S0D8, CLK_S0, 8, 1), 90 DEF_FIXED("s0d12", R8A774B1_CLK_S0D12, CLK_S0, 12, 1), 91 DEF_FIXED("s1d2", R8A774B1_CLK_S1D2, CLK_S1, 2, 1), 92 DEF_FIXED("s1d4", R8A774B1_CLK_S1D4, CLK_S1, 4, 1), 93 DEF_FIXED("s2d1", R8A774B1_CLK_S2D1, CLK_S2, 1, 1), 94 DEF_FIXED("s2d2", R8A774B1_CLK_S2D2, CLK_S2, 2, 1), 95 DEF_FIXED("s2d4", R8A774B1_CLK_S2D4, CLK_S2, 4, 1), 96 DEF_FIXED("s3d1", R8A774B1_CLK_S3D1, CLK_S3, 1, 1), 97 DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1), 98 DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1), 99 100 DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074), 101 DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078), 102 DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268), 103 DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c), 104 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074), 105 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078), 106 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268), 107 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c), 108 109 DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1), 110 DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1), 111 DEF_FIXED("cpex", R8A774B1_CLK_CPEX, CLK_EXTAL, 2, 1), 112 113 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 114 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), 115 DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014), 116 DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250), 117 118 DEF_GEN3_OSC("osc", R8A774B1_CLK_OSC, CLK_EXTAL, 8), 119 120 DEF_BASE("r", R8A774B1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 121 }; 122 123 static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = { 124 DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6), 125 DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2), 126 DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2), 127 DEF_MOD("tmu1", 124, R8A774B1_CLK_S3D2), 128 DEF_MOD("tmu0", 125, R8A774B1_CLK_CP), 129 DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1), 130 DEF_MOD("scif5", 202, R8A774B1_CLK_S3D4), 131 DEF_MOD("scif4", 203, R8A774B1_CLK_S3D4), 132 DEF_MOD("scif3", 204, R8A774B1_CLK_S3D4), 133 DEF_MOD("scif1", 206, R8A774B1_CLK_S3D4), 134 DEF_MOD("scif0", 207, R8A774B1_CLK_S3D4), 135 DEF_MOD("msiof3", 208, R8A774B1_CLK_MSO), 136 DEF_MOD("msiof2", 209, R8A774B1_CLK_MSO), 137 DEF_MOD("msiof1", 210, R8A774B1_CLK_MSO), 138 DEF_MOD("msiof0", 211, R8A774B1_CLK_MSO), 139 DEF_MOD("sys-dmac2", 217, R8A774B1_CLK_S3D1), 140 DEF_MOD("sys-dmac1", 218, R8A774B1_CLK_S3D1), 141 DEF_MOD("sys-dmac0", 219, R8A774B1_CLK_S0D3), 142 DEF_MOD("cmt3", 300, R8A774B1_CLK_R), 143 DEF_MOD("cmt2", 301, R8A774B1_CLK_R), 144 DEF_MOD("cmt1", 302, R8A774B1_CLK_R), 145 DEF_MOD("cmt0", 303, R8A774B1_CLK_R), 146 DEF_MOD("tpu0", 304, R8A774B1_CLK_S3D4), 147 DEF_MOD("scif2", 310, R8A774B1_CLK_S3D4), 148 DEF_MOD("sdif3", 311, R8A774B1_CLK_SD3), 149 DEF_MOD("sdif2", 312, R8A774B1_CLK_SD2), 150 DEF_MOD("sdif1", 313, R8A774B1_CLK_SD1), 151 DEF_MOD("sdif0", 314, R8A774B1_CLK_SD0), 152 DEF_MOD("pcie1", 318, R8A774B1_CLK_S3D1), 153 DEF_MOD("pcie0", 319, R8A774B1_CLK_S3D1), 154 DEF_MOD("usb3-if0", 328, R8A774B1_CLK_S3D1), 155 DEF_MOD("usb-dmac0", 330, R8A774B1_CLK_S3D1), 156 DEF_MOD("usb-dmac1", 331, R8A774B1_CLK_S3D1), 157 DEF_MOD("rwdt", 402, R8A774B1_CLK_R), 158 DEF_MOD("intc-ex", 407, R8A774B1_CLK_CP), 159 DEF_MOD("intc-ap", 408, R8A774B1_CLK_S0D3), 160 DEF_MOD("audmac1", 501, R8A774B1_CLK_S1D2), 161 DEF_MOD("audmac0", 502, R8A774B1_CLK_S1D2), 162 DEF_MOD("hscif4", 516, R8A774B1_CLK_S3D1), 163 DEF_MOD("hscif3", 517, R8A774B1_CLK_S3D1), 164 DEF_MOD("hscif2", 518, R8A774B1_CLK_S3D1), 165 DEF_MOD("hscif1", 519, R8A774B1_CLK_S3D1), 166 DEF_MOD("hscif0", 520, R8A774B1_CLK_S3D1), 167 DEF_MOD("thermal", 522, R8A774B1_CLK_CP), 168 DEF_MOD("pwm", 523, R8A774B1_CLK_S0D12), 169 DEF_MOD("fcpvd1", 602, R8A774B1_CLK_S0D2), 170 DEF_MOD("fcpvd0", 603, R8A774B1_CLK_S0D2), 171 DEF_MOD("fcpvb0", 607, R8A774B1_CLK_S0D1), 172 DEF_MOD("fcpvi0", 611, R8A774B1_CLK_S0D1), 173 DEF_MOD("fcpf0", 615, R8A774B1_CLK_S0D1), 174 DEF_MOD("fcpcs", 619, R8A774B1_CLK_S0D2), 175 DEF_MOD("vspd1", 622, R8A774B1_CLK_S0D2), 176 DEF_MOD("vspd0", 623, R8A774B1_CLK_S0D2), 177 DEF_MOD("vspb", 626, R8A774B1_CLK_S0D1), 178 DEF_MOD("vspi0", 631, R8A774B1_CLK_S0D1), 179 DEF_MOD("ehci1", 702, R8A774B1_CLK_S3D2), 180 DEF_MOD("ehci0", 703, R8A774B1_CLK_S3D2), 181 DEF_MOD("hsusb", 704, R8A774B1_CLK_S3D2), 182 DEF_MOD("csi20", 714, R8A774B1_CLK_CSI0), 183 DEF_MOD("csi40", 716, R8A774B1_CLK_CSI0), 184 DEF_MOD("du3", 721, R8A774B1_CLK_S2D1), 185 DEF_MOD("du1", 723, R8A774B1_CLK_S2D1), 186 DEF_MOD("du0", 724, R8A774B1_CLK_S2D1), 187 DEF_MOD("lvds", 727, R8A774B1_CLK_S2D1), 188 DEF_MOD("hdmi0", 729, R8A774B1_CLK_HDMI), 189 DEF_MOD("vin7", 804, R8A774B1_CLK_S0D2), 190 DEF_MOD("vin6", 805, R8A774B1_CLK_S0D2), 191 DEF_MOD("vin5", 806, R8A774B1_CLK_S0D2), 192 DEF_MOD("vin4", 807, R8A774B1_CLK_S0D2), 193 DEF_MOD("vin3", 808, R8A774B1_CLK_S0D2), 194 DEF_MOD("vin2", 809, R8A774B1_CLK_S0D2), 195 DEF_MOD("vin1", 810, R8A774B1_CLK_S0D2), 196 DEF_MOD("vin0", 811, R8A774B1_CLK_S0D2), 197 DEF_MOD("etheravb", 812, R8A774B1_CLK_S0D6), 198 DEF_MOD("sata0", 815, R8A774B1_CLK_S3D2), 199 DEF_MOD("gpio7", 905, R8A774B1_CLK_S3D4), 200 DEF_MOD("gpio6", 906, R8A774B1_CLK_S3D4), 201 DEF_MOD("gpio5", 907, R8A774B1_CLK_S3D4), 202 DEF_MOD("gpio4", 908, R8A774B1_CLK_S3D4), 203 DEF_MOD("gpio3", 909, R8A774B1_CLK_S3D4), 204 DEF_MOD("gpio2", 910, R8A774B1_CLK_S3D4), 205 DEF_MOD("gpio1", 911, R8A774B1_CLK_S3D4), 206 DEF_MOD("gpio0", 912, R8A774B1_CLK_S3D4), 207 DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2), 208 DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4), 209 DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4), 210 DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2), 211 DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6), 212 DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6), 213 DEF_MOD("iic-pmic", 926, R8A774B1_CLK_CP), 214 DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6), 215 DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6), 216 DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2), 217 DEF_MOD("i2c1", 930, R8A774B1_CLK_S3D2), 218 DEF_MOD("i2c0", 931, R8A774B1_CLK_S3D2), 219 DEF_MOD("ssi-all", 1005, R8A774B1_CLK_S3D4), 220 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 221 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 222 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 223 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 224 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 225 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 226 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 227 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 228 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 229 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 230 DEF_MOD("scu-all", 1017, R8A774B1_CLK_S3D4), 231 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 232 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 233 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 234 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 235 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 236 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 237 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 238 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 239 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 240 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 241 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 242 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 243 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 244 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 245 }; 246 247 static const unsigned int r8a774b1_crit_mod_clks[] __initconst = { 248 MOD_CLK_ID(402), /* RWDT */ 249 MOD_CLK_ID(408), /* INTC-AP (GIC) */ 250 }; 251 252 /* 253 * CPG Clock Data 254 */ 255 256 /* 257 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC 258 * 14 13 19 17 (MHz) 259 *----------------------------------------------------------------- 260 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16 261 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16 262 * 0 0 1 0 Prohibited setting 263 * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16 264 * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19 265 * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19 266 * 0 1 1 0 Prohibited setting 267 * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19 268 * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24 269 * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24 270 * 1 0 1 0 Prohibited setting 271 * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24 272 * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32 273 * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32 274 * 1 1 1 0 Prohibited setting 275 * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32 276 */ 277 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ 278 (((md) & BIT(13)) >> 11) | \ 279 (((md) & BIT(19)) >> 18) | \ 280 (((md) & BIT(17)) >> 17)) 281 282 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { 283 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ 284 { 1, 192, 1, 192, 1, 16, }, 285 { 1, 192, 1, 128, 1, 16, }, 286 { 0, /* Prohibited setting */ }, 287 { 1, 192, 1, 192, 1, 16, }, 288 { 1, 160, 1, 160, 1, 19, }, 289 { 1, 160, 1, 106, 1, 19, }, 290 { 0, /* Prohibited setting */ }, 291 { 1, 160, 1, 160, 1, 19, }, 292 { 1, 128, 1, 128, 1, 24, }, 293 { 1, 128, 1, 84, 1, 24, }, 294 { 0, /* Prohibited setting */ }, 295 { 1, 128, 1, 128, 1, 24, }, 296 { 2, 192, 1, 192, 1, 32, }, 297 { 2, 192, 1, 128, 1, 32, }, 298 { 0, /* Prohibited setting */ }, 299 { 2, 192, 1, 192, 1, 32, }, 300 }; 301 302 static int __init r8a774b1_cpg_mssr_init(struct device *dev) 303 { 304 const struct rcar_gen3_cpg_pll_config *cpg_pll_config; 305 u32 cpg_mode; 306 int error; 307 308 error = rcar_rst_read_mode_pins(&cpg_mode); 309 if (error) 310 return error; 311 312 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 313 if (!cpg_pll_config->extal_div) { 314 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); 315 return -EINVAL; 316 } 317 318 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); 319 } 320 321 const struct cpg_mssr_info r8a774b1_cpg_mssr_info __initconst = { 322 /* Core Clocks */ 323 .core_clks = r8a774b1_core_clks, 324 .num_core_clks = ARRAY_SIZE(r8a774b1_core_clks), 325 .last_dt_core_clk = LAST_DT_CORE_CLK, 326 .num_total_core_clks = MOD_CLK_BASE, 327 328 /* Module Clocks */ 329 .mod_clks = r8a774b1_mod_clks, 330 .num_mod_clks = ARRAY_SIZE(r8a774b1_mod_clks), 331 .num_hw_mod_clks = 12 * 32, 332 333 /* Critical Module Clocks */ 334 .crit_mod_clks = r8a774b1_crit_mod_clks, 335 .num_crit_mod_clks = ARRAY_SIZE(r8a774b1_crit_mod_clks), 336 337 /* Callbacks */ 338 .init = r8a774b1_cpg_mssr_init, 339 .cpg_clk_register = rcar_gen3_cpg_clk_register, 340 }; 341