19e288cefSKuninori Morimoto // SPDX-License-Identifier: GPL-2.0 2b3a33077SSimon Horman /* 3b3a33077SSimon Horman * sh73a0 Core CPG Clocks 4b3a33077SSimon Horman * 5b3a33077SSimon Horman * Copyright (C) 2014 Ulrich Hecht 6b3a33077SSimon Horman */ 7b3a33077SSimon Horman 8b3a33077SSimon Horman #include <linux/clk-provider.h> 909c32427SSimon Horman #include <linux/clk/renesas.h> 10b3a33077SSimon Horman #include <linux/init.h> 1162e59c4eSStephen Boyd #include <linux/io.h> 12b3a33077SSimon Horman #include <linux/kernel.h> 13b3a33077SSimon Horman #include <linux/of.h> 14b3a33077SSimon Horman #include <linux/of_address.h> 15b3a33077SSimon Horman #include <linux/slab.h> 16b3a33077SSimon Horman #include <linux/spinlock.h> 17b3a33077SSimon Horman 18b3a33077SSimon Horman struct sh73a0_cpg { 19b3a33077SSimon Horman struct clk_onecell_data data; 20b3a33077SSimon Horman spinlock_t lock; 21b3a33077SSimon Horman void __iomem *reg; 22b3a33077SSimon Horman }; 23b3a33077SSimon Horman 24b3a33077SSimon Horman #define CPG_FRQCRA 0x00 25b3a33077SSimon Horman #define CPG_FRQCRB 0x04 26b3a33077SSimon Horman #define CPG_SD0CKCR 0x74 27b3a33077SSimon Horman #define CPG_SD1CKCR 0x78 28b3a33077SSimon Horman #define CPG_SD2CKCR 0x7c 29b3a33077SSimon Horman #define CPG_PLLECR 0xd0 30b3a33077SSimon Horman #define CPG_PLL0CR 0xd8 31b3a33077SSimon Horman #define CPG_PLL1CR 0x28 32b3a33077SSimon Horman #define CPG_PLL2CR 0x2c 33b3a33077SSimon Horman #define CPG_PLL3CR 0xdc 34b3a33077SSimon Horman #define CPG_CKSCR 0xc0 35b3a33077SSimon Horman #define CPG_DSI0PHYCR 0x6c 36b3a33077SSimon Horman #define CPG_DSI1PHYCR 0x70 37b3a33077SSimon Horman 38b3a33077SSimon Horman #define CLK_ENABLE_ON_INIT BIT(0) 39b3a33077SSimon Horman 40b3a33077SSimon Horman struct div4_clk { 41b3a33077SSimon Horman const char *name; 42b3a33077SSimon Horman const char *parent; 43b3a33077SSimon Horman unsigned int reg; 44b3a33077SSimon Horman unsigned int shift; 45b3a33077SSimon Horman }; 46b3a33077SSimon Horman 47ce33f284SArnd Bergmann static const struct div4_clk div4_clks[] = { 48b3a33077SSimon Horman { "zg", "pll0", CPG_FRQCRA, 16 }, 49b3a33077SSimon Horman { "m3", "pll1", CPG_FRQCRA, 12 }, 50b3a33077SSimon Horman { "b", "pll1", CPG_FRQCRA, 8 }, 51b3a33077SSimon Horman { "m1", "pll1", CPG_FRQCRA, 4 }, 52b3a33077SSimon Horman { "m2", "pll1", CPG_FRQCRA, 0 }, 53b3a33077SSimon Horman { "zx", "pll1", CPG_FRQCRB, 12 }, 54b3a33077SSimon Horman { "hp", "pll1", CPG_FRQCRB, 4 }, 55b3a33077SSimon Horman { NULL, NULL, 0, 0 }, 56b3a33077SSimon Horman }; 57b3a33077SSimon Horman 58b3a33077SSimon Horman static const struct clk_div_table div4_div_table[] = { 59b3a33077SSimon Horman { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, 60b3a33077SSimon Horman { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, 61b3a33077SSimon Horman { 12, 7 }, { 0, 0 } 62b3a33077SSimon Horman }; 63b3a33077SSimon Horman 64b3a33077SSimon Horman static const struct clk_div_table z_div_table[] = { 65b3a33077SSimon Horman /* ZSEL == 0 */ 66b3a33077SSimon Horman { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 }, 67b3a33077SSimon Horman { 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 }, 68b3a33077SSimon Horman { 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 }, 69b3a33077SSimon Horman /* ZSEL == 1 */ 70b3a33077SSimon Horman { 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 }, 71b3a33077SSimon Horman { 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 } 72b3a33077SSimon Horman }; 73b3a33077SSimon Horman 74b3a33077SSimon Horman static struct clk * __init 75b3a33077SSimon Horman sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, 76b3a33077SSimon Horman const char *name) 77b3a33077SSimon Horman { 78b3a33077SSimon Horman const struct clk_div_table *table = NULL; 79b3a33077SSimon Horman unsigned int shift, reg, width; 80ce33f284SArnd Bergmann const char *parent_name = NULL; 81b3a33077SSimon Horman unsigned int mult = 1; 82b3a33077SSimon Horman unsigned int div = 1; 83b3a33077SSimon Horman 84b3a33077SSimon Horman if (!strcmp(name, "main")) { 85b3a33077SSimon Horman /* extal1, extal1_div2, extal2, extal2_div2 */ 86f046d6a6SGeert Uytterhoeven u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3; 87b3a33077SSimon Horman 88b3a33077SSimon Horman parent_name = of_clk_get_parent_name(np, parent_idx >> 1); 89b3a33077SSimon Horman div = (parent_idx & 1) + 1; 90b3a33077SSimon Horman } else if (!strncmp(name, "pll", 3)) { 91b3a33077SSimon Horman void __iomem *enable_reg = cpg->reg; 92b3a33077SSimon Horman u32 enable_bit = name[3] - '0'; 93b3a33077SSimon Horman 94b3a33077SSimon Horman parent_name = "main"; 95b3a33077SSimon Horman switch (enable_bit) { 96b3a33077SSimon Horman case 0: 97b3a33077SSimon Horman enable_reg += CPG_PLL0CR; 98b3a33077SSimon Horman break; 99b3a33077SSimon Horman case 1: 100b3a33077SSimon Horman enable_reg += CPG_PLL1CR; 101b3a33077SSimon Horman break; 102b3a33077SSimon Horman case 2: 103b3a33077SSimon Horman enable_reg += CPG_PLL2CR; 104b3a33077SSimon Horman break; 105b3a33077SSimon Horman case 3: 106b3a33077SSimon Horman enable_reg += CPG_PLL3CR; 107b3a33077SSimon Horman break; 108b3a33077SSimon Horman default: 109b3a33077SSimon Horman return ERR_PTR(-EINVAL); 110b3a33077SSimon Horman } 111f046d6a6SGeert Uytterhoeven if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { 112f046d6a6SGeert Uytterhoeven mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; 113b3a33077SSimon Horman /* handle CFG bit for PLL1 and PLL2 */ 114b3a33077SSimon Horman if (enable_bit == 1 || enable_bit == 2) 115f046d6a6SGeert Uytterhoeven if (readl(enable_reg) & BIT(20)) 116b3a33077SSimon Horman mult *= 2; 117b3a33077SSimon Horman } 118b3a33077SSimon Horman } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) { 119b3a33077SSimon Horman u32 phy_no = name[3] - '0'; 120b3a33077SSimon Horman void __iomem *dsi_reg = cpg->reg + 121b3a33077SSimon Horman (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR); 122b3a33077SSimon Horman 123b3a33077SSimon Horman parent_name = phy_no ? "dsi1pck" : "dsi0pck"; 124*fd0d8ed7SGeert Uytterhoeven mult = readl(dsi_reg); 125b3a33077SSimon Horman if (!(mult & 0x8000)) 126b3a33077SSimon Horman mult = 1; 127b3a33077SSimon Horman else 128b3a33077SSimon Horman mult = (mult & 0x3f) + 1; 129b3a33077SSimon Horman } else if (!strcmp(name, "z")) { 130b3a33077SSimon Horman parent_name = "pll0"; 131b3a33077SSimon Horman table = z_div_table; 132b3a33077SSimon Horman reg = CPG_FRQCRB; 133b3a33077SSimon Horman shift = 24; 134b3a33077SSimon Horman width = 5; 135b3a33077SSimon Horman } else { 136ce33f284SArnd Bergmann const struct div4_clk *c; 137b3a33077SSimon Horman 138b3a33077SSimon Horman for (c = div4_clks; c->name; c++) { 139b3a33077SSimon Horman if (!strcmp(name, c->name)) { 140b3a33077SSimon Horman parent_name = c->parent; 141b3a33077SSimon Horman table = div4_div_table; 142b3a33077SSimon Horman reg = c->reg; 143b3a33077SSimon Horman shift = c->shift; 144b3a33077SSimon Horman width = 4; 145b3a33077SSimon Horman break; 146b3a33077SSimon Horman } 147b3a33077SSimon Horman } 148b3a33077SSimon Horman if (!c->name) 149b3a33077SSimon Horman return ERR_PTR(-EINVAL); 150b3a33077SSimon Horman } 151b3a33077SSimon Horman 152b3a33077SSimon Horman if (!table) { 153b3a33077SSimon Horman return clk_register_fixed_factor(NULL, name, parent_name, 0, 154b3a33077SSimon Horman mult, div); 155b3a33077SSimon Horman } else { 156b3a33077SSimon Horman return clk_register_divider_table(NULL, name, parent_name, 0, 157b3a33077SSimon Horman cpg->reg + reg, shift, width, 0, 158b3a33077SSimon Horman table, &cpg->lock); 159b3a33077SSimon Horman } 160b3a33077SSimon Horman } 161b3a33077SSimon Horman 162b3a33077SSimon Horman static void __init sh73a0_cpg_clocks_init(struct device_node *np) 163b3a33077SSimon Horman { 164b3a33077SSimon Horman struct sh73a0_cpg *cpg; 165b3a33077SSimon Horman struct clk **clks; 166b3a33077SSimon Horman unsigned int i; 167b3a33077SSimon Horman int num_clks; 168b3a33077SSimon Horman 169b3a33077SSimon Horman num_clks = of_property_count_strings(np, "clock-output-names"); 170b3a33077SSimon Horman if (num_clks < 0) { 171b3a33077SSimon Horman pr_err("%s: failed to count clocks\n", __func__); 172b3a33077SSimon Horman return; 173b3a33077SSimon Horman } 174b3a33077SSimon Horman 175b3a33077SSimon Horman cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); 176b3a33077SSimon Horman clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); 177b3a33077SSimon Horman if (cpg == NULL || clks == NULL) { 178b3a33077SSimon Horman /* We're leaking memory on purpose, there's no point in cleaning 179b3a33077SSimon Horman * up as the system won't boot anyway. 180b3a33077SSimon Horman */ 181b3a33077SSimon Horman return; 182b3a33077SSimon Horman } 183b3a33077SSimon Horman 184b3a33077SSimon Horman spin_lock_init(&cpg->lock); 185b3a33077SSimon Horman 186b3a33077SSimon Horman cpg->data.clks = clks; 187b3a33077SSimon Horman cpg->data.clk_num = num_clks; 188b3a33077SSimon Horman 189b3a33077SSimon Horman cpg->reg = of_iomap(np, 0); 190b3a33077SSimon Horman if (WARN_ON(cpg->reg == NULL)) 191b3a33077SSimon Horman return; 192b3a33077SSimon Horman 193b3a33077SSimon Horman /* Set SDHI clocks to a known state */ 194f046d6a6SGeert Uytterhoeven writel(0x108, cpg->reg + CPG_SD0CKCR); 195f046d6a6SGeert Uytterhoeven writel(0x108, cpg->reg + CPG_SD1CKCR); 196f046d6a6SGeert Uytterhoeven writel(0x108, cpg->reg + CPG_SD2CKCR); 197b3a33077SSimon Horman 198b3a33077SSimon Horman for (i = 0; i < num_clks; ++i) { 199b3a33077SSimon Horman const char *name; 200b3a33077SSimon Horman struct clk *clk; 201b3a33077SSimon Horman 202b3a33077SSimon Horman of_property_read_string_index(np, "clock-output-names", i, 203b3a33077SSimon Horman &name); 204b3a33077SSimon Horman 205b3a33077SSimon Horman clk = sh73a0_cpg_register_clock(np, cpg, name); 206b3a33077SSimon Horman if (IS_ERR(clk)) 207e665f029SRob Herring pr_err("%s: failed to register %pOFn %s clock (%ld)\n", 208e665f029SRob Herring __func__, np, name, PTR_ERR(clk)); 209b3a33077SSimon Horman else 210b3a33077SSimon Horman cpg->data.clks[i] = clk; 211b3a33077SSimon Horman } 212b3a33077SSimon Horman 213b3a33077SSimon Horman of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); 214b3a33077SSimon Horman } 215b3a33077SSimon Horman CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks", 216b3a33077SSimon Horman sh73a0_cpg_clocks_init); 217