1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/A1 Core CPG Clocks 4 * 5 * Copyright (C) 2013 Ideas On Board SPRL 6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/clk/renesas.h> 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/slab.h> 16 17 struct rz_cpg { 18 struct clk_onecell_data data; 19 void __iomem *reg; 20 }; 21 22 #define CPG_FRQCR 0x10 23 #define CPG_FRQCR2 0x14 24 25 #define PPR0 0xFCFE3200 26 #define PIBC0 0xFCFE7000 27 28 #define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */ 29 30 /* ----------------------------------------------------------------------------- 31 * Initialization 32 */ 33 34 static u16 __init rz_cpg_read_mode_pins(void) 35 { 36 void __iomem *ppr0, *pibc0; 37 u16 modes; 38 39 ppr0 = ioremap_nocache(PPR0, 2); 40 pibc0 = ioremap_nocache(PIBC0, 2); 41 BUG_ON(!ppr0 || !pibc0); 42 iowrite16(4, pibc0); /* enable input buffer */ 43 modes = ioread16(ppr0); 44 iounmap(ppr0); 45 iounmap(pibc0); 46 47 return modes; 48 } 49 50 static struct clk * __init 51 rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name) 52 { 53 u32 val; 54 unsigned mult; 55 static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 }; 56 57 if (strcmp(name, "pll") == 0) { 58 unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins()); 59 const char *parent_name = of_clk_get_parent_name(np, cpg_mode); 60 61 mult = cpg_mode ? (32 / 4) : 30; 62 63 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1); 64 } 65 66 /* If mapping regs failed, skip non-pll clocks. System will boot anyhow */ 67 if (!cpg->reg) 68 return ERR_PTR(-ENXIO); 69 70 /* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3) 71 * and the constraint that always g <= i. To get the rz platform started, 72 * let them run at fixed current speed and implement the details later. 73 */ 74 if (strcmp(name, "i") == 0) 75 val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3; 76 else if (strcmp(name, "g") == 0) 77 val = readl(cpg->reg + CPG_FRQCR2) & 3; 78 else 79 return ERR_PTR(-EINVAL); 80 81 mult = frqcr_tab[val]; 82 return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3); 83 } 84 85 static void __init rz_cpg_clocks_init(struct device_node *np) 86 { 87 struct rz_cpg *cpg; 88 struct clk **clks; 89 unsigned i; 90 int num_clks; 91 92 num_clks = of_property_count_strings(np, "clock-output-names"); 93 if (WARN(num_clks <= 0, "can't count CPG clocks\n")) 94 return; 95 96 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); 97 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); 98 BUG_ON(!cpg || !clks); 99 100 cpg->data.clks = clks; 101 cpg->data.clk_num = num_clks; 102 103 cpg->reg = of_iomap(np, 0); 104 105 for (i = 0; i < num_clks; ++i) { 106 const char *name; 107 struct clk *clk; 108 109 of_property_read_string_index(np, "clock-output-names", i, &name); 110 111 clk = rz_cpg_register_clock(np, cpg, name); 112 if (IS_ERR(clk)) 113 pr_err("%s: failed to register %pOFn %s clock (%ld)\n", 114 __func__, np, name, PTR_ERR(clk)); 115 else 116 cpg->data.clks[i] = clk; 117 } 118 119 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); 120 121 cpg_mstp_add_clk_domain(np); 122 } 123 CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init); 124