1 /* 2 * rz Core CPG Clocks 3 * 4 * Copyright (C) 2013 Ideas On Board SPRL 5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/clk/renesas.h> 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/slab.h> 19 20 struct rz_cpg { 21 struct clk_onecell_data data; 22 void __iomem *reg; 23 }; 24 25 #define CPG_FRQCR 0x10 26 #define CPG_FRQCR2 0x14 27 28 /* ----------------------------------------------------------------------------- 29 * Initialization 30 */ 31 32 static struct clk * __init 33 rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name) 34 { 35 u32 val; 36 unsigned mult; 37 static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 }; 38 39 if (strcmp(name, "pll") == 0) { 40 /* FIXME: cpg_mode should be read from GPIO. But no GPIO support yet */ 41 unsigned cpg_mode = 0; /* hardcoded to EXTAL for now */ 42 const char *parent_name = of_clk_get_parent_name(np, cpg_mode); 43 44 mult = cpg_mode ? (32 / 4) : 30; 45 46 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1); 47 } 48 49 /* If mapping regs failed, skip non-pll clocks. System will boot anyhow */ 50 if (!cpg->reg) 51 return ERR_PTR(-ENXIO); 52 53 /* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3) 54 * and the constraint that always g <= i. To get the rz platform started, 55 * let them run at fixed current speed and implement the details later. 56 */ 57 if (strcmp(name, "i") == 0) 58 val = (clk_readl(cpg->reg + CPG_FRQCR) >> 8) & 3; 59 else if (strcmp(name, "g") == 0) 60 val = clk_readl(cpg->reg + CPG_FRQCR2) & 3; 61 else 62 return ERR_PTR(-EINVAL); 63 64 mult = frqcr_tab[val]; 65 return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3); 66 } 67 68 static void __init rz_cpg_clocks_init(struct device_node *np) 69 { 70 struct rz_cpg *cpg; 71 struct clk **clks; 72 unsigned i; 73 int num_clks; 74 75 num_clks = of_property_count_strings(np, "clock-output-names"); 76 if (WARN(num_clks <= 0, "can't count CPG clocks\n")) 77 return; 78 79 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); 80 clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL); 81 BUG_ON(!cpg || !clks); 82 83 cpg->data.clks = clks; 84 cpg->data.clk_num = num_clks; 85 86 cpg->reg = of_iomap(np, 0); 87 88 for (i = 0; i < num_clks; ++i) { 89 const char *name; 90 struct clk *clk; 91 92 of_property_read_string_index(np, "clock-output-names", i, &name); 93 94 clk = rz_cpg_register_clock(np, cpg, name); 95 if (IS_ERR(clk)) 96 pr_err("%s: failed to register %s %s clock (%ld)\n", 97 __func__, np->name, name, PTR_ERR(clk)); 98 else 99 cpg->data.clks[i] = clk; 100 } 101 102 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); 103 104 cpg_mstp_add_clk_domain(np); 105 } 106 CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init); 107