19e288cefSKuninori Morimoto // SPDX-License-Identifier: GPL-2.0
2b3a33077SSimon Horman /*
3d454ceccSGeert Uytterhoeven * RZ/A1 Core CPG Clocks
4b3a33077SSimon Horman *
5b3a33077SSimon Horman * Copyright (C) 2013 Ideas On Board SPRL
6b3a33077SSimon Horman * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
7b3a33077SSimon Horman */
8b3a33077SSimon Horman
9b3a33077SSimon Horman #include <linux/clk-provider.h>
1009c32427SSimon Horman #include <linux/clk/renesas.h>
11b3a33077SSimon Horman #include <linux/init.h>
1262e59c4eSStephen Boyd #include <linux/io.h>
13b3a33077SSimon Horman #include <linux/kernel.h>
14b3a33077SSimon Horman #include <linux/of.h>
15b3a33077SSimon Horman #include <linux/of_address.h>
16b3a33077SSimon Horman #include <linux/slab.h>
17b3a33077SSimon Horman
18b3a33077SSimon Horman #define CPG_FRQCR 0x10
19b3a33077SSimon Horman #define CPG_FRQCR2 0x14
20b3a33077SSimon Horman
21b452dfe9SChris Brandt #define PPR0 0xFCFE3200
22b452dfe9SChris Brandt #define PIBC0 0xFCFE7000
23b452dfe9SChris Brandt
24b452dfe9SChris Brandt #define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */
25b452dfe9SChris Brandt
26b3a33077SSimon Horman /* -----------------------------------------------------------------------------
27b3a33077SSimon Horman * Initialization
28b3a33077SSimon Horman */
29b3a33077SSimon Horman
rz_cpg_read_mode_pins(void)30b452dfe9SChris Brandt static u16 __init rz_cpg_read_mode_pins(void)
31b452dfe9SChris Brandt {
32b452dfe9SChris Brandt void __iomem *ppr0, *pibc0;
33b452dfe9SChris Brandt u16 modes;
34b452dfe9SChris Brandt
354bdc0d67SChristoph Hellwig ppr0 = ioremap(PPR0, 2);
364bdc0d67SChristoph Hellwig pibc0 = ioremap(PIBC0, 2);
37b452dfe9SChris Brandt BUG_ON(!ppr0 || !pibc0);
38b452dfe9SChris Brandt iowrite16(4, pibc0); /* enable input buffer */
39b452dfe9SChris Brandt modes = ioread16(ppr0);
40b452dfe9SChris Brandt iounmap(ppr0);
41b452dfe9SChris Brandt iounmap(pibc0);
42b452dfe9SChris Brandt
43b452dfe9SChris Brandt return modes;
44b452dfe9SChris Brandt }
45b452dfe9SChris Brandt
46b3a33077SSimon Horman static struct clk * __init
rz_cpg_register_clock(struct device_node * np,void __iomem * base,const char * name)47*980bcaf3SGeert Uytterhoeven rz_cpg_register_clock(struct device_node *np, void __iomem *base,
48*980bcaf3SGeert Uytterhoeven const char *name)
49b3a33077SSimon Horman {
50b3a33077SSimon Horman u32 val;
51b3a33077SSimon Horman unsigned mult;
52b3a33077SSimon Horman static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
53b3a33077SSimon Horman
54b3a33077SSimon Horman if (strcmp(name, "pll") == 0) {
55b452dfe9SChris Brandt unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
56b3a33077SSimon Horman const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
57b3a33077SSimon Horman
58b3a33077SSimon Horman mult = cpg_mode ? (32 / 4) : 30;
59b3a33077SSimon Horman
60b3a33077SSimon Horman return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
61b3a33077SSimon Horman }
62b3a33077SSimon Horman
63b3a33077SSimon Horman /* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
64*980bcaf3SGeert Uytterhoeven if (!base)
65b3a33077SSimon Horman return ERR_PTR(-ENXIO);
66b3a33077SSimon Horman
67b3a33077SSimon Horman /* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
68b3a33077SSimon Horman * and the constraint that always g <= i. To get the rz platform started,
69b3a33077SSimon Horman * let them run at fixed current speed and implement the details later.
70b3a33077SSimon Horman */
71b3a33077SSimon Horman if (strcmp(name, "i") == 0)
72*980bcaf3SGeert Uytterhoeven val = (readl(base + CPG_FRQCR) >> 8) & 3;
73b3a33077SSimon Horman else if (strcmp(name, "g") == 0)
74*980bcaf3SGeert Uytterhoeven val = readl(base + CPG_FRQCR2) & 3;
75b3a33077SSimon Horman else
76b3a33077SSimon Horman return ERR_PTR(-EINVAL);
77b3a33077SSimon Horman
78b3a33077SSimon Horman mult = frqcr_tab[val];
79b3a33077SSimon Horman return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
80b3a33077SSimon Horman }
81b3a33077SSimon Horman
rz_cpg_clocks_init(struct device_node * np)82b3a33077SSimon Horman static void __init rz_cpg_clocks_init(struct device_node *np)
83b3a33077SSimon Horman {
84*980bcaf3SGeert Uytterhoeven struct clk_onecell_data *data;
85b3a33077SSimon Horman struct clk **clks;
86*980bcaf3SGeert Uytterhoeven void __iomem *base;
87b3a33077SSimon Horman unsigned i;
88b3a33077SSimon Horman int num_clks;
89b3a33077SSimon Horman
90b3a33077SSimon Horman num_clks = of_property_count_strings(np, "clock-output-names");
91b3a33077SSimon Horman if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
92b3a33077SSimon Horman return;
93b3a33077SSimon Horman
94*980bcaf3SGeert Uytterhoeven data = kzalloc(sizeof(*data), GFP_KERNEL);
956396bb22SKees Cook clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
96*980bcaf3SGeert Uytterhoeven BUG_ON(!data || !clks);
97b3a33077SSimon Horman
98*980bcaf3SGeert Uytterhoeven data->clks = clks;
99*980bcaf3SGeert Uytterhoeven data->clk_num = num_clks;
100b3a33077SSimon Horman
101*980bcaf3SGeert Uytterhoeven base = of_iomap(np, 0);
102b3a33077SSimon Horman
103b3a33077SSimon Horman for (i = 0; i < num_clks; ++i) {
104b3a33077SSimon Horman const char *name;
105b3a33077SSimon Horman struct clk *clk;
106b3a33077SSimon Horman
107b3a33077SSimon Horman of_property_read_string_index(np, "clock-output-names", i, &name);
108b3a33077SSimon Horman
109*980bcaf3SGeert Uytterhoeven clk = rz_cpg_register_clock(np, base, name);
110b3a33077SSimon Horman if (IS_ERR(clk))
111e665f029SRob Herring pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
112e665f029SRob Herring __func__, np, name, PTR_ERR(clk));
113b3a33077SSimon Horman else
114*980bcaf3SGeert Uytterhoeven data->clks[i] = clk;
115b3a33077SSimon Horman }
116b3a33077SSimon Horman
117*980bcaf3SGeert Uytterhoeven of_clk_add_provider(np, of_clk_src_onecell_get, data);
118b3a33077SSimon Horman
119b3a33077SSimon Horman cpg_mstp_add_clk_domain(np);
120b3a33077SSimon Horman }
121b3a33077SSimon Horman CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
122