1 /* 2 * r8a7779 Core CPG Clocks 3 * 4 * Copyright (C) 2013, 2014 Horms Solutions Ltd. 5 * 6 * Contact: Simon Horman <horms@verge.net.au> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 */ 12 13 #include <linux/clk-provider.h> 14 #include <linux/clk/renesas.h> 15 #include <linux/init.h> 16 #include <linux/kernel.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/slab.h> 20 #include <linux/spinlock.h> 21 #include <linux/soc/renesas/rcar-rst.h> 22 23 #include <dt-bindings/clock/r8a7779-clock.h> 24 25 #define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1) 26 27 struct r8a7779_cpg { 28 struct clk_onecell_data data; 29 spinlock_t lock; 30 void __iomem *reg; 31 }; 32 33 /* ----------------------------------------------------------------------------- 34 * CPG Clock Data 35 */ 36 37 /* 38 * MD1 = 1 MD1 = 0 39 * (PLLA = 1500) (PLLA = 1600) 40 * (MHz) (MHz) 41 *------------------------------------------------+-------------------- 42 * clkz 1000 (2/3) 800 (1/2) 43 * clkzs 250 (1/6) 200 (1/8) 44 * clki 750 (1/2) 800 (1/2) 45 * clks 250 (1/6) 200 (1/8) 46 * clks1 125 (1/12) 100 (1/16) 47 * clks3 187.5 (1/8) 200 (1/8) 48 * clks4 93.7 (1/16) 100 (1/16) 49 * clkp 62.5 (1/24) 50 (1/32) 50 * clkg 62.5 (1/24) 66.6 (1/24) 51 * clkb, CLKOUT 52 * (MD2 = 0) 62.5 (1/24) 66.6 (1/24) 53 * (MD2 = 1) 41.6 (1/36) 50 (1/32) 54 */ 55 56 #define CPG_CLK_CONFIG_INDEX(md) (((md) & (BIT(2)|BIT(1))) >> 1) 57 58 struct cpg_clk_config { 59 unsigned int z_mult; 60 unsigned int z_div; 61 unsigned int zs_and_s_div; 62 unsigned int s1_div; 63 unsigned int p_div; 64 unsigned int b_and_out_div; 65 }; 66 67 static const struct cpg_clk_config cpg_clk_configs[4] __initconst = { 68 { 1, 2, 8, 16, 32, 24 }, 69 { 2, 3, 6, 12, 24, 24 }, 70 { 1, 2, 8, 16, 32, 32 }, 71 { 2, 3, 6, 12, 24, 36 }, 72 }; 73 74 /* 75 * MD PLLA Ratio 76 * 12 11 77 *------------------------ 78 * 0 0 x42 79 * 0 1 x48 80 * 1 0 x56 81 * 1 1 x64 82 */ 83 84 #define CPG_PLLA_MULT_INDEX(md) (((md) & (BIT(12)|BIT(11))) >> 11) 85 86 static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 }; 87 88 /* ----------------------------------------------------------------------------- 89 * Initialization 90 */ 91 92 static struct clk * __init 93 r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, 94 const struct cpg_clk_config *config, 95 unsigned int plla_mult, const char *name) 96 { 97 const char *parent_name = "plla"; 98 unsigned int mult = 1; 99 unsigned int div = 1; 100 101 if (!strcmp(name, "plla")) { 102 parent_name = of_clk_get_parent_name(np, 0); 103 mult = plla_mult; 104 } else if (!strcmp(name, "z")) { 105 div = config->z_div; 106 mult = config->z_mult; 107 } else if (!strcmp(name, "zs") || !strcmp(name, "s")) { 108 div = config->zs_and_s_div; 109 } else if (!strcmp(name, "s1")) { 110 div = config->s1_div; 111 } else if (!strcmp(name, "p")) { 112 div = config->p_div; 113 } else if (!strcmp(name, "b") || !strcmp(name, "out")) { 114 div = config->b_and_out_div; 115 } else { 116 return ERR_PTR(-EINVAL); 117 } 118 119 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); 120 } 121 122 static void __init r8a7779_cpg_clocks_init(struct device_node *np) 123 { 124 const struct cpg_clk_config *config; 125 struct r8a7779_cpg *cpg; 126 struct clk **clks; 127 unsigned int i, plla_mult; 128 int num_clks; 129 u32 mode; 130 131 if (rcar_rst_read_mode_pins(&mode)) 132 return; 133 134 num_clks = of_property_count_strings(np, "clock-output-names"); 135 if (num_clks < 0) { 136 pr_err("%s: failed to count clocks\n", __func__); 137 return; 138 } 139 140 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); 141 clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL); 142 if (cpg == NULL || clks == NULL) { 143 /* We're leaking memory on purpose, there's no point in cleaning 144 * up as the system won't boot anyway. 145 */ 146 return; 147 } 148 149 spin_lock_init(&cpg->lock); 150 151 cpg->data.clks = clks; 152 cpg->data.clk_num = num_clks; 153 154 config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)]; 155 plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)]; 156 157 for (i = 0; i < num_clks; ++i) { 158 const char *name; 159 struct clk *clk; 160 161 of_property_read_string_index(np, "clock-output-names", i, 162 &name); 163 164 clk = r8a7779_cpg_register_clock(np, cpg, config, 165 plla_mult, name); 166 if (IS_ERR(clk)) 167 pr_err("%s: failed to register %s %s clock (%ld)\n", 168 __func__, np->name, name, PTR_ERR(clk)); 169 else 170 cpg->data.clks[i] = clk; 171 } 172 173 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); 174 175 cpg_mstp_add_clk_domain(np); 176 } 177 CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks", 178 r8a7779_cpg_clocks_init); 179