1 /* 2 * r8a7778 Core CPG Clocks 3 * 4 * Copyright (C) 2014 Ulrich Hecht 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/clk/renesas.h> 13 #include <linux/of_address.h> 14 #include <linux/slab.h> 15 #include <linux/soc/renesas/rcar-rst.h> 16 17 struct r8a7778_cpg { 18 struct clk_onecell_data data; 19 spinlock_t lock; 20 void __iomem *reg; 21 }; 22 23 /* PLL multipliers per bits 11, 12, and 18 of MODEMR */ 24 static const struct { 25 unsigned long plla_mult; 26 unsigned long pllb_mult; 27 } r8a7778_rates[] __initconst = { 28 [0] = { 21, 21 }, 29 [1] = { 24, 24 }, 30 [2] = { 28, 28 }, 31 [3] = { 32, 32 }, 32 [5] = { 24, 21 }, 33 [6] = { 28, 21 }, 34 [7] = { 32, 24 }, 35 }; 36 37 /* Clock dividers per bits 1 and 2 of MODEMR */ 38 static const struct { 39 const char *name; 40 unsigned int div[4]; 41 } r8a7778_divs[6] __initconst = { 42 { "b", { 12, 12, 16, 18 } }, 43 { "out", { 12, 12, 16, 18 } }, 44 { "p", { 16, 12, 16, 12 } }, 45 { "s", { 4, 3, 4, 3 } }, 46 { "s1", { 8, 6, 8, 6 } }, 47 }; 48 49 static u32 cpg_mode_rates __initdata; 50 static u32 cpg_mode_divs __initdata; 51 52 static struct clk * __init 53 r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg, 54 const char *name) 55 { 56 if (!strcmp(name, "plla")) { 57 return clk_register_fixed_factor(NULL, "plla", 58 of_clk_get_parent_name(np, 0), 0, 59 r8a7778_rates[cpg_mode_rates].plla_mult, 1); 60 } else if (!strcmp(name, "pllb")) { 61 return clk_register_fixed_factor(NULL, "pllb", 62 of_clk_get_parent_name(np, 0), 0, 63 r8a7778_rates[cpg_mode_rates].pllb_mult, 1); 64 } else { 65 unsigned int i; 66 67 for (i = 0; i < ARRAY_SIZE(r8a7778_divs); i++) { 68 if (!strcmp(name, r8a7778_divs[i].name)) { 69 return clk_register_fixed_factor(NULL, 70 r8a7778_divs[i].name, 71 "plla", 0, 1, 72 r8a7778_divs[i].div[cpg_mode_divs]); 73 } 74 } 75 } 76 77 return ERR_PTR(-EINVAL); 78 } 79 80 81 static void __init r8a7778_cpg_clocks_init(struct device_node *np) 82 { 83 struct r8a7778_cpg *cpg; 84 struct clk **clks; 85 unsigned int i; 86 int num_clks; 87 u32 mode; 88 89 if (rcar_rst_read_mode_pins(&mode)) 90 return; 91 92 BUG_ON(!(mode & BIT(19))); 93 94 cpg_mode_rates = (!!(mode & BIT(18)) << 2) | 95 (!!(mode & BIT(12)) << 1) | 96 (!!(mode & BIT(11))); 97 cpg_mode_divs = (!!(mode & BIT(2)) << 1) | 98 (!!(mode & BIT(1))); 99 100 num_clks = of_property_count_strings(np, "clock-output-names"); 101 if (num_clks < 0) { 102 pr_err("%s: failed to count clocks\n", __func__); 103 return; 104 } 105 106 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); 107 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); 108 if (cpg == NULL || clks == NULL) { 109 /* We're leaking memory on purpose, there's no point in cleaning 110 * up as the system won't boot anyway. 111 */ 112 return; 113 } 114 115 spin_lock_init(&cpg->lock); 116 117 cpg->data.clks = clks; 118 cpg->data.clk_num = num_clks; 119 120 cpg->reg = of_iomap(np, 0); 121 if (WARN_ON(cpg->reg == NULL)) 122 return; 123 124 for (i = 0; i < num_clks; ++i) { 125 const char *name; 126 struct clk *clk; 127 128 of_property_read_string_index(np, "clock-output-names", i, 129 &name); 130 131 clk = r8a7778_cpg_register_clock(np, cpg, name); 132 if (IS_ERR(clk)) 133 pr_err("%s: failed to register %s %s clock (%ld)\n", 134 __func__, np->name, name, PTR_ERR(clk)); 135 else 136 cpg->data.clks[i] = clk; 137 } 138 139 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); 140 141 cpg_mstp_add_clk_domain(np); 142 } 143 144 CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks", 145 r8a7778_cpg_clocks_init); 146