1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * r8a7778 Core CPG Clocks
4  *
5  * Copyright (C) 2014  Ulrich Hecht
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/clk/renesas.h>
10 #include <linux/of_address.h>
11 #include <linux/slab.h>
12 #include <linux/soc/renesas/rcar-rst.h>
13 
14 struct r8a7778_cpg {
15 	struct clk_onecell_data data;
16 	spinlock_t lock;
17 	void __iomem *reg;
18 };
19 
20 /* PLL multipliers per bits 11, 12, and 18 of MODEMR */
21 static const struct {
22 	unsigned long plla_mult;
23 	unsigned long pllb_mult;
24 } r8a7778_rates[] __initconst = {
25 	[0] = { 21, 21 },
26 	[1] = { 24, 24 },
27 	[2] = { 28, 28 },
28 	[3] = { 32, 32 },
29 	[5] = { 24, 21 },
30 	[6] = { 28, 21 },
31 	[7] = { 32, 24 },
32 };
33 
34 /* Clock dividers per bits 1 and 2 of MODEMR */
35 static const struct {
36 	const char *name;
37 	unsigned int div[4];
38 } r8a7778_divs[6] __initconst = {
39 	{ "b",   { 12, 12, 16, 18 } },
40 	{ "out", { 12, 12, 16, 18 } },
41 	{ "p",   { 16, 12, 16, 12 } },
42 	{ "s",   { 4,  3,  4,  3  } },
43 	{ "s1",  { 8,  6,  8,  6  } },
44 };
45 
46 static u32 cpg_mode_rates __initdata;
47 static u32 cpg_mode_divs __initdata;
48 
49 static struct clk * __init
50 r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
51 			     const char *name)
52 {
53 	if (!strcmp(name, "plla")) {
54 		return clk_register_fixed_factor(NULL, "plla",
55 			of_clk_get_parent_name(np, 0), 0,
56 			r8a7778_rates[cpg_mode_rates].plla_mult, 1);
57 	} else if (!strcmp(name, "pllb")) {
58 		return clk_register_fixed_factor(NULL, "pllb",
59 			of_clk_get_parent_name(np, 0), 0,
60 			r8a7778_rates[cpg_mode_rates].pllb_mult, 1);
61 	} else {
62 		unsigned int i;
63 
64 		for (i = 0; i < ARRAY_SIZE(r8a7778_divs); i++) {
65 			if (!strcmp(name, r8a7778_divs[i].name)) {
66 				return clk_register_fixed_factor(NULL,
67 					r8a7778_divs[i].name,
68 					"plla", 0, 1,
69 					r8a7778_divs[i].div[cpg_mode_divs]);
70 			}
71 		}
72 	}
73 
74 	return ERR_PTR(-EINVAL);
75 }
76 
77 
78 static void __init r8a7778_cpg_clocks_init(struct device_node *np)
79 {
80 	struct r8a7778_cpg *cpg;
81 	struct clk **clks;
82 	unsigned int i;
83 	int num_clks;
84 	u32 mode;
85 
86 	if (rcar_rst_read_mode_pins(&mode))
87 		return;
88 
89 	BUG_ON(!(mode & BIT(19)));
90 
91 	cpg_mode_rates = (!!(mode & BIT(18)) << 2) |
92 			 (!!(mode & BIT(12)) << 1) |
93 			 (!!(mode & BIT(11)));
94 	cpg_mode_divs = (!!(mode & BIT(2)) << 1) |
95 			(!!(mode & BIT(1)));
96 
97 	num_clks = of_property_count_strings(np, "clock-output-names");
98 	if (num_clks < 0) {
99 		pr_err("%s: failed to count clocks\n", __func__);
100 		return;
101 	}
102 
103 	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
104 	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
105 	if (cpg == NULL || clks == NULL) {
106 		/* We're leaking memory on purpose, there's no point in cleaning
107 		 * up as the system won't boot anyway.
108 		 */
109 		return;
110 	}
111 
112 	spin_lock_init(&cpg->lock);
113 
114 	cpg->data.clks = clks;
115 	cpg->data.clk_num = num_clks;
116 
117 	cpg->reg = of_iomap(np, 0);
118 	if (WARN_ON(cpg->reg == NULL))
119 		return;
120 
121 	for (i = 0; i < num_clks; ++i) {
122 		const char *name;
123 		struct clk *clk;
124 
125 		of_property_read_string_index(np, "clock-output-names", i,
126 					      &name);
127 
128 		clk = r8a7778_cpg_register_clock(np, cpg, name);
129 		if (IS_ERR(clk))
130 			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
131 			       __func__, np, name, PTR_ERR(clk));
132 		else
133 			cpg->data.clks[i] = clk;
134 	}
135 
136 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
137 
138 	cpg_mstp_add_clk_domain(np);
139 }
140 
141 CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
142 	       r8a7778_cpg_clocks_init);
143