1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a7740 Core CPG Clocks 4 * 5 * Copyright (C) 2014 Ulrich Hecht 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/clk/renesas.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/slab.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/spinlock.h> 17 18 struct r8a7740_cpg { 19 struct clk_onecell_data data; 20 spinlock_t lock; 21 void __iomem *reg; 22 }; 23 24 #define CPG_FRQCRA 0x00 25 #define CPG_FRQCRB 0x04 26 #define CPG_PLLC2CR 0x2c 27 #define CPG_USBCKCR 0x8c 28 #define CPG_FRQCRC 0xe0 29 30 #define CLK_ENABLE_ON_INIT BIT(0) 31 32 struct div4_clk { 33 const char *name; 34 unsigned int reg; 35 unsigned int shift; 36 int flags; 37 }; 38 39 static struct div4_clk div4_clks[] = { 40 { "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT }, 41 { "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT }, 42 { "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT }, 43 { "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT }, 44 { "hp", CPG_FRQCRB, 4, 0 }, 45 { "hpp", CPG_FRQCRC, 20, 0 }, 46 { "usbp", CPG_FRQCRC, 16, 0 }, 47 { "s", CPG_FRQCRC, 12, 0 }, 48 { "zb", CPG_FRQCRC, 8, 0 }, 49 { "m3", CPG_FRQCRC, 4, 0 }, 50 { "cp", CPG_FRQCRC, 0, 0 }, 51 { NULL, 0, 0, 0 }, 52 }; 53 54 static const struct clk_div_table div4_div_table[] = { 55 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, 56 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 9, 32 }, { 10, 36 }, { 11, 48 }, 57 { 13, 72 }, { 14, 96 }, { 0, 0 } 58 }; 59 60 static u32 cpg_mode __initdata; 61 62 static struct clk * __init 63 r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, 64 const char *name) 65 { 66 const struct clk_div_table *table = NULL; 67 const char *parent_name; 68 unsigned int shift, reg; 69 unsigned int mult = 1; 70 unsigned int div = 1; 71 72 if (!strcmp(name, "r")) { 73 switch (cpg_mode & (BIT(2) | BIT(1))) { 74 case BIT(1) | BIT(2): 75 /* extal1 */ 76 parent_name = of_clk_get_parent_name(np, 0); 77 div = 2048; 78 break; 79 case BIT(2): 80 /* extal1 */ 81 parent_name = of_clk_get_parent_name(np, 0); 82 div = 1024; 83 break; 84 default: 85 /* extalr */ 86 parent_name = of_clk_get_parent_name(np, 2); 87 break; 88 } 89 } else if (!strcmp(name, "system")) { 90 parent_name = of_clk_get_parent_name(np, 0); 91 if (cpg_mode & BIT(1)) 92 div = 2; 93 } else if (!strcmp(name, "pllc0")) { 94 /* PLLC0/1 are configurable multiplier clocks. Register them as 95 * fixed factor clocks for now as there's no generic multiplier 96 * clock implementation and we currently have no need to change 97 * the multiplier value. 98 */ 99 u32 value = readl(cpg->reg + CPG_FRQCRC); 100 parent_name = "system"; 101 mult = ((value >> 24) & 0x7f) + 1; 102 } else if (!strcmp(name, "pllc1")) { 103 u32 value = readl(cpg->reg + CPG_FRQCRA); 104 parent_name = "system"; 105 mult = ((value >> 24) & 0x7f) + 1; 106 div = 2; 107 } else if (!strcmp(name, "pllc2")) { 108 u32 value = readl(cpg->reg + CPG_PLLC2CR); 109 parent_name = "system"; 110 mult = ((value >> 24) & 0x3f) + 1; 111 } else if (!strcmp(name, "usb24s")) { 112 u32 value = readl(cpg->reg + CPG_USBCKCR); 113 if (value & BIT(7)) 114 /* extal2 */ 115 parent_name = of_clk_get_parent_name(np, 1); 116 else 117 parent_name = "system"; 118 if (!(value & BIT(6))) 119 div = 2; 120 } else { 121 struct div4_clk *c; 122 for (c = div4_clks; c->name; c++) { 123 if (!strcmp(name, c->name)) { 124 parent_name = "pllc1"; 125 table = div4_div_table; 126 reg = c->reg; 127 shift = c->shift; 128 break; 129 } 130 } 131 if (!c->name) 132 return ERR_PTR(-EINVAL); 133 } 134 135 if (!table) { 136 return clk_register_fixed_factor(NULL, name, parent_name, 0, 137 mult, div); 138 } else { 139 return clk_register_divider_table(NULL, name, parent_name, 0, 140 cpg->reg + reg, shift, 4, 0, 141 table, &cpg->lock); 142 } 143 } 144 145 static void __init r8a7740_cpg_clocks_init(struct device_node *np) 146 { 147 struct r8a7740_cpg *cpg; 148 struct clk **clks; 149 unsigned int i; 150 int num_clks; 151 152 if (of_property_read_u32(np, "renesas,mode", &cpg_mode)) 153 pr_warn("%s: missing renesas,mode property\n", __func__); 154 155 num_clks = of_property_count_strings(np, "clock-output-names"); 156 if (num_clks < 0) { 157 pr_err("%s: failed to count clocks\n", __func__); 158 return; 159 } 160 161 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); 162 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); 163 if (cpg == NULL || clks == NULL) { 164 /* We're leaking memory on purpose, there's no point in cleaning 165 * up as the system won't boot anyway. 166 */ 167 return; 168 } 169 170 spin_lock_init(&cpg->lock); 171 172 cpg->data.clks = clks; 173 cpg->data.clk_num = num_clks; 174 175 cpg->reg = of_iomap(np, 0); 176 if (WARN_ON(cpg->reg == NULL)) 177 return; 178 179 for (i = 0; i < num_clks; ++i) { 180 const char *name; 181 struct clk *clk; 182 183 of_property_read_string_index(np, "clock-output-names", i, 184 &name); 185 186 clk = r8a7740_cpg_register_clock(np, cpg, name); 187 if (IS_ERR(clk)) 188 pr_err("%s: failed to register %pOFn %s clock (%ld)\n", 189 __func__, np, name, PTR_ERR(clk)); 190 else 191 cpg->data.clks[i] = clk; 192 } 193 194 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); 195 } 196 CLK_OF_DECLARE(r8a7740_cpg_clks, "renesas,r8a7740-cpg-clocks", 197 r8a7740_cpg_clocks_init); 198