1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a7790 Common Clock Framework support 4 * 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 * 7 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 8 */ 9 10 #include <linux/clk-provider.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/notifier.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/pm.h> 18 #include <linux/slab.h> 19 20 #include "clk-div6.h" 21 22 #define CPG_DIV6_CKSTP BIT(8) 23 #define CPG_DIV6_DIV(d) ((d) & 0x3f) 24 #define CPG_DIV6_DIV_MASK 0x3f 25 26 /** 27 * struct div6_clock - CPG 6 bit divider clock 28 * @hw: handle between common and hardware-specific interfaces 29 * @reg: IO-remapped register 30 * @div: divisor value (1-64) 31 * @src_shift: Shift to access the register bits to select the parent clock 32 * @src_width: Number of register bits to select the parent clock (may be 0) 33 * @parents: Array to map from valid parent clocks indices to hardware indices 34 * @nb: Notifier block to save/restore clock state for system resume 35 */ 36 struct div6_clock { 37 struct clk_hw hw; 38 void __iomem *reg; 39 unsigned int div; 40 u32 src_shift; 41 u32 src_width; 42 u8 *parents; 43 struct notifier_block nb; 44 }; 45 46 #define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw) 47 48 static int cpg_div6_clock_enable(struct clk_hw *hw) 49 { 50 struct div6_clock *clock = to_div6_clock(hw); 51 u32 val; 52 53 val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) 54 | CPG_DIV6_DIV(clock->div - 1); 55 writel(val, clock->reg); 56 57 return 0; 58 } 59 60 static void cpg_div6_clock_disable(struct clk_hw *hw) 61 { 62 struct div6_clock *clock = to_div6_clock(hw); 63 u32 val; 64 65 val = readl(clock->reg); 66 val |= CPG_DIV6_CKSTP; 67 /* 68 * DIV6 clocks require the divisor field to be non-zero when stopping 69 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be 70 * re-enabled later if the divisor field is changed when stopping the 71 * clock 72 */ 73 if (!(val & CPG_DIV6_DIV_MASK)) 74 val |= CPG_DIV6_DIV_MASK; 75 writel(val, clock->reg); 76 } 77 78 static int cpg_div6_clock_is_enabled(struct clk_hw *hw) 79 { 80 struct div6_clock *clock = to_div6_clock(hw); 81 82 return !(readl(clock->reg) & CPG_DIV6_CKSTP); 83 } 84 85 static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw, 86 unsigned long parent_rate) 87 { 88 struct div6_clock *clock = to_div6_clock(hw); 89 90 return parent_rate / clock->div; 91 } 92 93 static unsigned int cpg_div6_clock_calc_div(unsigned long rate, 94 unsigned long parent_rate) 95 { 96 unsigned int div; 97 98 if (!rate) 99 rate = 1; 100 101 div = DIV_ROUND_CLOSEST(parent_rate, rate); 102 return clamp_t(unsigned int, div, 1, 64); 103 } 104 105 static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate, 106 unsigned long *parent_rate) 107 { 108 unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate); 109 110 return *parent_rate / div; 111 } 112 113 static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate, 114 unsigned long parent_rate) 115 { 116 struct div6_clock *clock = to_div6_clock(hw); 117 unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate); 118 u32 val; 119 120 clock->div = div; 121 122 val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK; 123 /* Only program the new divisor if the clock isn't stopped. */ 124 if (!(val & CPG_DIV6_CKSTP)) 125 writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg); 126 127 return 0; 128 } 129 130 static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) 131 { 132 struct div6_clock *clock = to_div6_clock(hw); 133 unsigned int i; 134 u8 hw_index; 135 136 if (clock->src_width == 0) 137 return 0; 138 139 hw_index = (readl(clock->reg) >> clock->src_shift) & 140 (BIT(clock->src_width) - 1); 141 for (i = 0; i < clk_hw_get_num_parents(hw); i++) { 142 if (clock->parents[i] == hw_index) 143 return i; 144 } 145 146 pr_err("%s: %s DIV6 clock set to invalid parent %u\n", 147 __func__, clk_hw_get_name(hw), hw_index); 148 return 0; 149 } 150 151 static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) 152 { 153 struct div6_clock *clock = to_div6_clock(hw); 154 u8 hw_index; 155 u32 mask; 156 157 if (index >= clk_hw_get_num_parents(hw)) 158 return -EINVAL; 159 160 mask = ~((BIT(clock->src_width) - 1) << clock->src_shift); 161 hw_index = clock->parents[index]; 162 163 writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift), 164 clock->reg); 165 166 return 0; 167 } 168 169 static const struct clk_ops cpg_div6_clock_ops = { 170 .enable = cpg_div6_clock_enable, 171 .disable = cpg_div6_clock_disable, 172 .is_enabled = cpg_div6_clock_is_enabled, 173 .get_parent = cpg_div6_clock_get_parent, 174 .set_parent = cpg_div6_clock_set_parent, 175 .recalc_rate = cpg_div6_clock_recalc_rate, 176 .round_rate = cpg_div6_clock_round_rate, 177 .set_rate = cpg_div6_clock_set_rate, 178 }; 179 180 static int cpg_div6_clock_notifier_call(struct notifier_block *nb, 181 unsigned long action, void *data) 182 { 183 struct div6_clock *clock = container_of(nb, struct div6_clock, nb); 184 185 switch (action) { 186 case PM_EVENT_RESUME: 187 /* 188 * TODO: This does not yet support DIV6 clocks with multiple 189 * parents, as the parent selection bits are not restored. 190 * Fortunately so far such DIV6 clocks are found only on 191 * R/SH-Mobile SoCs, while the resume functionality is only 192 * needed on R-Car Gen3. 193 */ 194 if (__clk_get_enable_count(clock->hw.clk)) 195 cpg_div6_clock_enable(&clock->hw); 196 else 197 cpg_div6_clock_disable(&clock->hw); 198 return NOTIFY_OK; 199 } 200 201 return NOTIFY_DONE; 202 } 203 204 /** 205 * cpg_div6_register - Register a DIV6 clock 206 * @name: Name of the DIV6 clock 207 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8) 208 * @parent_names: Array containing the names of the parent clocks 209 * @reg: Mapped register used to control the DIV6 clock 210 * @notifiers: Optional notifier chain to save/restore state for system resume 211 */ 212 struct clk * __init cpg_div6_register(const char *name, 213 unsigned int num_parents, 214 const char **parent_names, 215 void __iomem *reg, 216 struct raw_notifier_head *notifiers) 217 { 218 unsigned int valid_parents; 219 struct clk_init_data init; 220 struct div6_clock *clock; 221 struct clk *clk; 222 unsigned int i; 223 224 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 225 if (!clock) 226 return ERR_PTR(-ENOMEM); 227 228 clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents), 229 GFP_KERNEL); 230 if (!clock->parents) { 231 clk = ERR_PTR(-ENOMEM); 232 goto free_clock; 233 } 234 235 clock->reg = reg; 236 237 /* 238 * Read the divisor. Disabling the clock overwrites the divisor, so we 239 * need to cache its value for the enable operation. 240 */ 241 clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; 242 243 switch (num_parents) { 244 case 1: 245 /* fixed parent clock */ 246 clock->src_shift = clock->src_width = 0; 247 break; 248 case 4: 249 /* clock with EXSRC bits 6-7 */ 250 clock->src_shift = 6; 251 clock->src_width = 2; 252 break; 253 case 8: 254 /* VCLK with EXSRC bits 12-14 */ 255 clock->src_shift = 12; 256 clock->src_width = 3; 257 break; 258 default: 259 pr_err("%s: invalid number of parents for DIV6 clock %s\n", 260 __func__, name); 261 clk = ERR_PTR(-EINVAL); 262 goto free_parents; 263 } 264 265 /* Filter out invalid parents */ 266 for (i = 0, valid_parents = 0; i < num_parents; i++) { 267 if (parent_names[i]) { 268 parent_names[valid_parents] = parent_names[i]; 269 clock->parents[valid_parents] = i; 270 valid_parents++; 271 } 272 } 273 274 /* Register the clock. */ 275 init.name = name; 276 init.ops = &cpg_div6_clock_ops; 277 init.flags = CLK_IS_BASIC; 278 init.parent_names = parent_names; 279 init.num_parents = valid_parents; 280 281 clock->hw.init = &init; 282 283 clk = clk_register(NULL, &clock->hw); 284 if (IS_ERR(clk)) 285 goto free_parents; 286 287 if (notifiers) { 288 clock->nb.notifier_call = cpg_div6_clock_notifier_call; 289 raw_notifier_chain_register(notifiers, &clock->nb); 290 } 291 292 return clk; 293 294 free_parents: 295 kfree(clock->parents); 296 free_clock: 297 kfree(clock); 298 return clk; 299 } 300 301 static void __init cpg_div6_clock_init(struct device_node *np) 302 { 303 unsigned int num_parents; 304 const char **parent_names; 305 const char *clk_name = np->name; 306 void __iomem *reg; 307 struct clk *clk; 308 unsigned int i; 309 310 num_parents = of_clk_get_parent_count(np); 311 if (num_parents < 1) { 312 pr_err("%s: no parent found for %pOFn DIV6 clock\n", 313 __func__, np); 314 return; 315 } 316 317 parent_names = kmalloc_array(num_parents, sizeof(*parent_names), 318 GFP_KERNEL); 319 if (!parent_names) 320 return; 321 322 reg = of_iomap(np, 0); 323 if (reg == NULL) { 324 pr_err("%s: failed to map %pOFn DIV6 clock register\n", 325 __func__, np); 326 goto error; 327 } 328 329 /* Parse the DT properties. */ 330 of_property_read_string(np, "clock-output-names", &clk_name); 331 332 for (i = 0; i < num_parents; i++) 333 parent_names[i] = of_clk_get_parent_name(np, i); 334 335 clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL); 336 if (IS_ERR(clk)) { 337 pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n", 338 __func__, np, PTR_ERR(clk)); 339 goto error; 340 } 341 342 of_clk_add_provider(np, of_clk_src_simple_get, clk); 343 344 kfree(parent_names); 345 return; 346 347 error: 348 if (reg) 349 iounmap(reg); 350 kfree(parent_names); 351 } 352 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init); 353