1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MTMIPS SoCs Clock Driver 4 * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com> 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/clk-provider.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/reset-controller.h> 13 #include <linux/slab.h> 14 15 /* Configuration registers */ 16 #define SYSC_REG_SYSTEM_CONFIG 0x10 17 #define SYSC_REG_CLKCFG0 0x2c 18 #define SYSC_REG_RESET_CTRL 0x34 19 #define SYSC_REG_CPU_SYS_CLKCFG 0x3c 20 #define SYSC_REG_CPLL_CONFIG0 0x54 21 #define SYSC_REG_CPLL_CONFIG1 0x58 22 23 /* RT2880 SoC */ 24 #define RT2880_CONFIG_CPUCLK_SHIFT 20 25 #define RT2880_CONFIG_CPUCLK_MASK 0x3 26 #define RT2880_CONFIG_CPUCLK_250 0x0 27 #define RT2880_CONFIG_CPUCLK_266 0x1 28 #define RT2880_CONFIG_CPUCLK_280 0x2 29 #define RT2880_CONFIG_CPUCLK_300 0x3 30 31 /* RT305X SoC */ 32 #define RT305X_SYSCFG_CPUCLK_SHIFT 18 33 #define RT305X_SYSCFG_CPUCLK_MASK 0x1 34 #define RT305X_SYSCFG_CPUCLK_LOW 0x0 35 #define RT305X_SYSCFG_CPUCLK_HIGH 0x1 36 37 /* RT3352 SoC */ 38 #define RT3352_SYSCFG0_CPUCLK_SHIFT 8 39 #define RT3352_SYSCFG0_CPUCLK_MASK 0x1 40 #define RT3352_SYSCFG0_CPUCLK_LOW 0x0 41 #define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 42 43 /* RT3383 SoC */ 44 #define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17) 45 #define RT3883_SYSCFG0_CPUCLK_SHIFT 8 46 #define RT3883_SYSCFG0_CPUCLK_MASK 0x3 47 #define RT3883_SYSCFG0_CPUCLK_250 0x0 48 #define RT3883_SYSCFG0_CPUCLK_384 0x1 49 #define RT3883_SYSCFG0_CPUCLK_480 0x2 50 #define RT3883_SYSCFG0_CPUCLK_500 0x3 51 52 /* RT5350 SoC */ 53 #define RT5350_CLKCFG0_XTAL_SEL BIT(20) 54 #define RT5350_SYSCFG0_CPUCLK_SHIFT 8 55 #define RT5350_SYSCFG0_CPUCLK_MASK 0x3 56 #define RT5350_SYSCFG0_CPUCLK_360 0x0 57 #define RT5350_SYSCFG0_CPUCLK_320 0x2 58 #define RT5350_SYSCFG0_CPUCLK_300 0x3 59 60 /* MT7620 and MT76x8 SoCs */ 61 #define MT7620_XTAL_FREQ_SEL BIT(6) 62 #define CPLL_CFG0_SW_CFG BIT(31) 63 #define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16 64 #define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7 65 #define CPLL_CFG0_LC_CURFCK BIT(15) 66 #define CPLL_CFG0_BYPASS_REF_CLK BIT(14) 67 #define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10 68 #define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3 69 #define CPLL_CFG1_CPU_AUX1 BIT(25) 70 #define CPLL_CFG1_CPU_AUX0 BIT(24) 71 #define CLKCFG0_PERI_CLK_SEL BIT(4) 72 #define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16 73 #define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf 74 #define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */ 75 #define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */ 76 #define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */ 77 #define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */ 78 #define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */ 79 #define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */ 80 #define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */ 81 #define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */ 82 #define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */ 83 #define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8 84 #define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f 85 #define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0 86 #define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f 87 88 /* clock scaling */ 89 #define CLKCFG_FDIV_MASK 0x1f00 90 #define CLKCFG_FDIV_USB_VAL 0x0300 91 #define CLKCFG_FFRAC_MASK 0x001f 92 #define CLKCFG_FFRAC_USB_VAL 0x0003 93 94 struct mtmips_clk; 95 struct mtmips_clk_fixed; 96 struct mtmips_clk_factor; 97 98 struct mtmips_clk_data { 99 struct mtmips_clk *clk_base; 100 size_t num_clk_base; 101 struct mtmips_clk_fixed *clk_fixed; 102 size_t num_clk_fixed; 103 struct mtmips_clk_factor *clk_factor; 104 size_t num_clk_factor; 105 struct mtmips_clk *clk_periph; 106 size_t num_clk_periph; 107 }; 108 109 struct mtmips_clk_priv { 110 struct regmap *sysc; 111 const struct mtmips_clk_data *data; 112 }; 113 114 struct mtmips_clk { 115 struct clk_hw hw; 116 struct mtmips_clk_priv *priv; 117 }; 118 119 struct mtmips_clk_fixed { 120 const char *name; 121 const char *parent; 122 unsigned long rate; 123 struct clk_hw *hw; 124 }; 125 126 struct mtmips_clk_factor { 127 const char *name; 128 const char *parent; 129 int mult; 130 int div; 131 unsigned long flags; 132 struct clk_hw *hw; 133 }; 134 135 static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw, 136 unsigned long parent_rate) 137 { 138 return parent_rate; 139 } 140 141 static const struct clk_ops mtmips_periph_clk_ops = { 142 .recalc_rate = mtmips_pherip_clk_rate, 143 }; 144 145 #define CLK_PERIPH(_name, _parent) { \ 146 .init = &(const struct clk_init_data) { \ 147 .name = _name, \ 148 .ops = &mtmips_periph_clk_ops, \ 149 .parent_data = &(const struct clk_parent_data) {\ 150 .name = _parent, \ 151 .fw_name = _parent \ 152 }, \ 153 .num_parents = 1, \ 154 /* \ 155 * There are drivers for these SoCs that are \ 156 * older than clock driver and are not prepared \ 157 * for the clock. We don't want the kernel to \ 158 * disable anything so we add CLK_IS_CRITICAL \ 159 * flag here. \ 160 */ \ 161 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL \ 162 }, \ 163 } 164 165 static struct mtmips_clk rt2880_pherip_clks[] = { 166 { CLK_PERIPH("300100.timer", "bus") }, 167 { CLK_PERIPH("300120.watchdog", "bus") }, 168 { CLK_PERIPH("300500.uart", "bus") }, 169 { CLK_PERIPH("300900.i2c", "bus") }, 170 { CLK_PERIPH("300c00.uartlite", "bus") }, 171 { CLK_PERIPH("400000.ethernet", "bus") }, 172 { CLK_PERIPH("480000.wmac", "xtal") } 173 }; 174 175 static struct mtmips_clk rt305x_pherip_clks[] = { 176 { CLK_PERIPH("10000100.timer", "bus") }, 177 { CLK_PERIPH("10000120.watchdog", "bus") }, 178 { CLK_PERIPH("10000500.uart", "bus") }, 179 { CLK_PERIPH("10000900.i2c", "bus") }, 180 { CLK_PERIPH("10000a00.i2s", "bus") }, 181 { CLK_PERIPH("10000b00.spi", "bus") }, 182 { CLK_PERIPH("10000b40.spi", "bus") }, 183 { CLK_PERIPH("10000c00.uartlite", "bus") }, 184 { CLK_PERIPH("10100000.ethernet", "bus") }, 185 { CLK_PERIPH("10180000.wmac", "xtal") } 186 }; 187 188 static struct mtmips_clk rt5350_pherip_clks[] = { 189 { CLK_PERIPH("10000100.timer", "bus") }, 190 { CLK_PERIPH("10000120.watchdog", "bus") }, 191 { CLK_PERIPH("10000500.uart", "periph") }, 192 { CLK_PERIPH("10000900.i2c", "periph") }, 193 { CLK_PERIPH("10000a00.i2s", "periph") }, 194 { CLK_PERIPH("10000b00.spi", "bus") }, 195 { CLK_PERIPH("10000b40.spi", "bus") }, 196 { CLK_PERIPH("10000c00.uartlite", "periph") }, 197 { CLK_PERIPH("10100000.ethernet", "bus") }, 198 { CLK_PERIPH("10180000.wmac", "xtal") } 199 }; 200 201 static struct mtmips_clk mt7620_pherip_clks[] = { 202 { CLK_PERIPH("10000100.timer", "periph") }, 203 { CLK_PERIPH("10000120.watchdog", "periph") }, 204 { CLK_PERIPH("10000500.uart", "periph") }, 205 { CLK_PERIPH("10000900.i2c", "periph") }, 206 { CLK_PERIPH("10000a00.i2s", "periph") }, 207 { CLK_PERIPH("10000b00.spi", "bus") }, 208 { CLK_PERIPH("10000b40.spi", "bus") }, 209 { CLK_PERIPH("10000c00.uartlite", "periph") }, 210 { CLK_PERIPH("10180000.wmac", "xtal") } 211 }; 212 213 static struct mtmips_clk mt76x8_pherip_clks[] = { 214 { CLK_PERIPH("10000100.timer", "periph") }, 215 { CLK_PERIPH("10000120.watchdog", "periph") }, 216 { CLK_PERIPH("10000900.i2c", "periph") }, 217 { CLK_PERIPH("10000a00.i2s", "pcmi2s") }, 218 { CLK_PERIPH("10000b00.spi", "bus") }, 219 { CLK_PERIPH("10000b40.spi", "bus") }, 220 { CLK_PERIPH("10000c00.uart0", "periph") }, 221 { CLK_PERIPH("10000d00.uart1", "periph") }, 222 { CLK_PERIPH("10000e00.uart2", "periph") }, 223 { CLK_PERIPH("10300000.wmac", "xtal") } 224 }; 225 226 static int mtmips_register_pherip_clocks(struct device_node *np, 227 struct clk_hw_onecell_data *clk_data, 228 struct mtmips_clk_priv *priv) 229 { 230 struct clk_hw **hws = clk_data->hws; 231 struct mtmips_clk *sclk; 232 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed + 233 priv->data->num_clk_factor; 234 int ret, i; 235 236 for (i = 0; i < priv->data->num_clk_periph; i++) { 237 int idx = idx_start + i; 238 239 sclk = &priv->data->clk_periph[i]; 240 ret = of_clk_hw_register(np, &sclk->hw); 241 if (ret) { 242 pr_err("Couldn't register peripheral clock %d\n", idx); 243 goto err_clk_unreg; 244 } 245 246 hws[idx] = &sclk->hw; 247 } 248 249 return 0; 250 251 err_clk_unreg: 252 while (--i >= 0) { 253 sclk = &priv->data->clk_periph[i]; 254 clk_hw_unregister(&sclk->hw); 255 } 256 return ret; 257 } 258 259 #define CLK_FIXED(_name, _parent, _rate) \ 260 { \ 261 .name = _name, \ 262 .parent = _parent, \ 263 .rate = _rate \ 264 } 265 266 static struct mtmips_clk_fixed rt305x_fixed_clocks[] = { 267 CLK_FIXED("xtal", NULL, 40000000) 268 }; 269 270 static struct mtmips_clk_fixed rt3352_fixed_clocks[] = { 271 CLK_FIXED("periph", "xtal", 40000000) 272 }; 273 274 static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = { 275 CLK_FIXED("pcmi2s", "xtal", 480000000), 276 CLK_FIXED("periph", "xtal", 40000000) 277 }; 278 279 static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data, 280 struct mtmips_clk_priv *priv) 281 { 282 struct clk_hw **hws = clk_data->hws; 283 struct mtmips_clk_fixed *sclk; 284 size_t idx_start = priv->data->num_clk_base; 285 int ret, i; 286 287 for (i = 0; i < priv->data->num_clk_fixed; i++) { 288 int idx = idx_start + i; 289 290 sclk = &priv->data->clk_fixed[i]; 291 sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name, 292 sclk->parent, 0, 293 sclk->rate); 294 if (IS_ERR(sclk->hw)) { 295 pr_err("Couldn't register fixed clock %d\n", idx); 296 goto err_clk_unreg; 297 } 298 299 hws[idx] = sclk->hw; 300 } 301 302 return 0; 303 304 err_clk_unreg: 305 while (--i >= 0) { 306 sclk = &priv->data->clk_fixed[i]; 307 clk_hw_unregister_fixed_rate(sclk->hw); 308 } 309 return ret; 310 } 311 312 #define CLK_FACTOR(_name, _parent, _mult, _div) \ 313 { \ 314 .name = _name, \ 315 .parent = _parent, \ 316 .mult = _mult, \ 317 .div = _div, \ 318 .flags = CLK_SET_RATE_PARENT \ 319 } 320 321 static struct mtmips_clk_factor rt2880_factor_clocks[] = { 322 CLK_FACTOR("bus", "cpu", 1, 2) 323 }; 324 325 static struct mtmips_clk_factor rt305x_factor_clocks[] = { 326 CLK_FACTOR("bus", "cpu", 1, 3) 327 }; 328 329 static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data, 330 struct mtmips_clk_priv *priv) 331 { 332 struct clk_hw **hws = clk_data->hws; 333 struct mtmips_clk_factor *sclk; 334 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed; 335 int ret, i; 336 337 for (i = 0; i < priv->data->num_clk_factor; i++) { 338 int idx = idx_start + i; 339 340 sclk = &priv->data->clk_factor[i]; 341 sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name, 342 sclk->parent, sclk->flags, 343 sclk->mult, sclk->div); 344 if (IS_ERR(sclk->hw)) { 345 pr_err("Couldn't register factor clock %d\n", idx); 346 goto err_clk_unreg; 347 } 348 349 hws[idx] = sclk->hw; 350 } 351 352 return 0; 353 354 err_clk_unreg: 355 while (--i >= 0) { 356 sclk = &priv->data->clk_factor[i]; 357 clk_hw_unregister_fixed_factor(sclk->hw); 358 } 359 return ret; 360 } 361 362 static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw) 363 { 364 return container_of(hw, struct mtmips_clk, hw); 365 } 366 367 static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw, 368 unsigned long parent_rate) 369 { 370 struct mtmips_clk *clk = to_mtmips_clk(hw); 371 struct regmap *sysc = clk->priv->sysc; 372 u32 val; 373 374 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val); 375 if (!(val & RT5350_CLKCFG0_XTAL_SEL)) 376 return 20000000; 377 378 return 40000000; 379 } 380 381 static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw, 382 unsigned long xtal_clk) 383 { 384 struct mtmips_clk *clk = to_mtmips_clk(hw); 385 struct regmap *sysc = clk->priv->sysc; 386 u32 t; 387 388 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 389 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK; 390 391 switch (t) { 392 case RT5350_SYSCFG0_CPUCLK_360: 393 return 360000000; 394 case RT5350_SYSCFG0_CPUCLK_320: 395 return 320000000; 396 case RT5350_SYSCFG0_CPUCLK_300: 397 return 300000000; 398 default: 399 BUG(); 400 } 401 } 402 403 static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw, 404 unsigned long parent_rate) 405 { 406 if (parent_rate == 320000000) 407 return parent_rate / 4; 408 409 return parent_rate / 3; 410 } 411 412 static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw, 413 unsigned long xtal_clk) 414 { 415 struct mtmips_clk *clk = to_mtmips_clk(hw); 416 struct regmap *sysc = clk->priv->sysc; 417 u32 t; 418 419 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 420 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK; 421 422 switch (t) { 423 case RT3352_SYSCFG0_CPUCLK_LOW: 424 return 384000000; 425 case RT3352_SYSCFG0_CPUCLK_HIGH: 426 return 400000000; 427 default: 428 BUG(); 429 } 430 } 431 432 static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw, 433 unsigned long xtal_clk) 434 { 435 struct mtmips_clk *clk = to_mtmips_clk(hw); 436 struct regmap *sysc = clk->priv->sysc; 437 u32 t; 438 439 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 440 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK; 441 442 switch (t) { 443 case RT305X_SYSCFG_CPUCLK_LOW: 444 return 320000000; 445 case RT305X_SYSCFG_CPUCLK_HIGH: 446 return 384000000; 447 default: 448 BUG(); 449 } 450 } 451 452 static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw, 453 unsigned long xtal_clk) 454 { 455 struct mtmips_clk *clk = to_mtmips_clk(hw); 456 struct regmap *sysc = clk->priv->sysc; 457 u32 t; 458 459 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 460 t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK; 461 462 switch (t) { 463 case RT3883_SYSCFG0_CPUCLK_250: 464 return 250000000; 465 case RT3883_SYSCFG0_CPUCLK_384: 466 return 384000000; 467 case RT3883_SYSCFG0_CPUCLK_480: 468 return 480000000; 469 case RT3883_SYSCFG0_CPUCLK_500: 470 return 500000000; 471 default: 472 BUG(); 473 } 474 } 475 476 static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw, 477 unsigned long parent_rate) 478 { 479 struct mtmips_clk *clk = to_mtmips_clk(hw); 480 struct regmap *sysc = clk->priv->sysc; 481 u32 ddr2; 482 u32 t; 483 484 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 485 ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2; 486 487 switch (parent_rate) { 488 case 250000000: 489 return (ddr2) ? 125000000 : 83000000; 490 case 384000000: 491 return (ddr2) ? 128000000 : 96000000; 492 case 480000000: 493 return (ddr2) ? 160000000 : 120000000; 494 case 500000000: 495 return (ddr2) ? 166000000 : 125000000; 496 default: 497 WARN_ON_ONCE(parent_rate == 0); 498 return parent_rate / 4; 499 } 500 } 501 502 static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw, 503 unsigned long xtal_clk) 504 { 505 struct mtmips_clk *clk = to_mtmips_clk(hw); 506 struct regmap *sysc = clk->priv->sysc; 507 u32 t; 508 509 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 510 t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK; 511 512 switch (t) { 513 case RT2880_CONFIG_CPUCLK_250: 514 return 250000000; 515 case RT2880_CONFIG_CPUCLK_266: 516 return 266000000; 517 case RT2880_CONFIG_CPUCLK_280: 518 return 280000000; 519 case RT2880_CONFIG_CPUCLK_300: 520 return 300000000; 521 default: 522 BUG(); 523 } 524 } 525 526 static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) 527 { 528 u64 t; 529 530 t = ref_rate; 531 t *= mul; 532 t = div_u64(t, div); 533 534 return t; 535 } 536 537 static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw, 538 unsigned long parent_rate) 539 { 540 static const u32 clk_divider[] = { 2, 3, 4, 8 }; 541 struct mtmips_clk *clk = to_mtmips_clk(hw); 542 struct regmap *sysc = clk->priv->sysc; 543 unsigned long cpu_pll; 544 u32 t; 545 u32 mul; 546 u32 div; 547 548 regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t); 549 if (t & CPLL_CFG0_BYPASS_REF_CLK) { 550 cpu_pll = parent_rate; 551 } else if ((t & CPLL_CFG0_SW_CFG) == 0) { 552 cpu_pll = 600000000; 553 } else { 554 mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & 555 CPLL_CFG0_PLL_MULT_RATIO_MASK; 556 mul += 24; 557 if (t & CPLL_CFG0_LC_CURFCK) 558 mul *= 2; 559 560 div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & 561 CPLL_CFG0_PLL_DIV_RATIO_MASK; 562 563 WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider)); 564 565 cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]); 566 } 567 568 regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t); 569 if (t & CPLL_CFG1_CPU_AUX1) 570 return parent_rate; 571 572 if (t & CPLL_CFG1_CPU_AUX0) 573 return 480000000; 574 575 return cpu_pll; 576 } 577 578 static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw, 579 unsigned long parent_rate) 580 { 581 struct mtmips_clk *clk = to_mtmips_clk(hw); 582 struct regmap *sysc = clk->priv->sysc; 583 u32 t; 584 u32 mul; 585 u32 div; 586 587 regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); 588 mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; 589 div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & 590 CPU_SYS_CLKCFG_CPU_FDIV_MASK; 591 592 return mt7620_calc_rate(parent_rate, mul, div); 593 } 594 595 static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw, 596 unsigned long parent_rate) 597 { 598 static const u32 ocp_dividers[16] = { 599 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, 600 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, 601 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, 602 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, 603 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, 604 }; 605 struct mtmips_clk *clk = to_mtmips_clk(hw); 606 struct regmap *sysc = clk->priv->sysc; 607 u32 t; 608 u32 ocp_ratio; 609 u32 div; 610 611 regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); 612 ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & 613 CPU_SYS_CLKCFG_OCP_RATIO_MASK; 614 615 if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers))) 616 return parent_rate; 617 618 div = ocp_dividers[ocp_ratio]; 619 620 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) 621 return parent_rate; 622 623 return parent_rate / div; 624 } 625 626 static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw, 627 unsigned long parent_rate) 628 { 629 struct mtmips_clk *clk = to_mtmips_clk(hw); 630 struct regmap *sysc = clk->priv->sysc; 631 u32 t; 632 633 regmap_read(sysc, SYSC_REG_CLKCFG0, &t); 634 if (t & CLKCFG0_PERI_CLK_SEL) 635 return parent_rate; 636 637 return 40000000; 638 } 639 640 static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw, 641 unsigned long parent_rate) 642 { 643 struct mtmips_clk *clk = to_mtmips_clk(hw); 644 struct regmap *sysc = clk->priv->sysc; 645 u32 t; 646 647 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 648 if (t & MT7620_XTAL_FREQ_SEL) 649 return 40000000; 650 651 return 20000000; 652 } 653 654 static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw, 655 unsigned long xtal_clk) 656 { 657 if (xtal_clk == 40000000) 658 return 580000000; 659 660 return 575000000; 661 } 662 663 #define CLK_BASE(_name, _parent, _recalc) { \ 664 .init = &(const struct clk_init_data) { \ 665 .name = _name, \ 666 .ops = &(const struct clk_ops) { \ 667 .recalc_rate = _recalc, \ 668 }, \ 669 .parent_data = &(const struct clk_parent_data) { \ 670 .name = _parent, \ 671 .fw_name = _parent \ 672 }, \ 673 .num_parents = _parent ? 1 : 0 \ 674 }, \ 675 } 676 677 static struct mtmips_clk rt2880_clks_base[] = { 678 { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) } 679 }; 680 681 static struct mtmips_clk rt305x_clks_base[] = { 682 { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) } 683 }; 684 685 static struct mtmips_clk rt3352_clks_base[] = { 686 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) }, 687 { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) } 688 }; 689 690 static struct mtmips_clk rt3883_clks_base[] = { 691 { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) }, 692 { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) } 693 }; 694 695 static struct mtmips_clk rt5350_clks_base[] = { 696 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) }, 697 { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) }, 698 { CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) } 699 }; 700 701 static struct mtmips_clk mt7620_clks_base[] = { 702 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) }, 703 { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) }, 704 { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) }, 705 { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) }, 706 { CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) } 707 }; 708 709 static struct mtmips_clk mt76x8_clks_base[] = { 710 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) }, 711 { CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) } 712 }; 713 714 static int mtmips_register_clocks(struct device_node *np, 715 struct clk_hw_onecell_data *clk_data, 716 struct mtmips_clk_priv *priv) 717 { 718 struct clk_hw **hws = clk_data->hws; 719 struct mtmips_clk *sclk; 720 int ret, i; 721 722 for (i = 0; i < priv->data->num_clk_base; i++) { 723 sclk = &priv->data->clk_base[i]; 724 sclk->priv = priv; 725 ret = of_clk_hw_register(np, &sclk->hw); 726 if (ret) { 727 pr_err("Couldn't register top clock %i\n", i); 728 goto err_clk_unreg; 729 } 730 731 hws[i] = &sclk->hw; 732 } 733 734 return 0; 735 736 err_clk_unreg: 737 while (--i >= 0) { 738 sclk = &priv->data->clk_base[i]; 739 clk_hw_unregister(&sclk->hw); 740 } 741 return ret; 742 } 743 744 static const struct mtmips_clk_data rt2880_clk_data = { 745 .clk_base = rt2880_clks_base, 746 .num_clk_base = ARRAY_SIZE(rt2880_clks_base), 747 .clk_fixed = rt305x_fixed_clocks, 748 .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks), 749 .clk_factor = rt2880_factor_clocks, 750 .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks), 751 .clk_periph = rt2880_pherip_clks, 752 .num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks), 753 }; 754 755 static const struct mtmips_clk_data rt305x_clk_data = { 756 .clk_base = rt305x_clks_base, 757 .num_clk_base = ARRAY_SIZE(rt305x_clks_base), 758 .clk_fixed = rt305x_fixed_clocks, 759 .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks), 760 .clk_factor = rt305x_factor_clocks, 761 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), 762 .clk_periph = rt305x_pherip_clks, 763 .num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks), 764 }; 765 766 static const struct mtmips_clk_data rt3352_clk_data = { 767 .clk_base = rt3352_clks_base, 768 .num_clk_base = ARRAY_SIZE(rt3352_clks_base), 769 .clk_fixed = rt3352_fixed_clocks, 770 .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks), 771 .clk_factor = rt305x_factor_clocks, 772 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), 773 .clk_periph = rt5350_pherip_clks, 774 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), 775 }; 776 777 static const struct mtmips_clk_data rt3883_clk_data = { 778 .clk_base = rt3883_clks_base, 779 .num_clk_base = ARRAY_SIZE(rt3883_clks_base), 780 .clk_fixed = rt305x_fixed_clocks, 781 .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks), 782 .clk_factor = NULL, 783 .num_clk_factor = 0, 784 .clk_periph = rt5350_pherip_clks, 785 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), 786 }; 787 788 static const struct mtmips_clk_data rt5350_clk_data = { 789 .clk_base = rt5350_clks_base, 790 .num_clk_base = ARRAY_SIZE(rt5350_clks_base), 791 .clk_fixed = rt3352_fixed_clocks, 792 .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks), 793 .clk_factor = NULL, 794 .num_clk_factor = 0, 795 .clk_periph = rt5350_pherip_clks, 796 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), 797 }; 798 799 static const struct mtmips_clk_data mt7620_clk_data = { 800 .clk_base = mt7620_clks_base, 801 .num_clk_base = ARRAY_SIZE(mt7620_clks_base), 802 .clk_fixed = NULL, 803 .num_clk_fixed = 0, 804 .clk_factor = NULL, 805 .num_clk_factor = 0, 806 .clk_periph = mt7620_pherip_clks, 807 .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks), 808 }; 809 810 static const struct mtmips_clk_data mt76x8_clk_data = { 811 .clk_base = mt76x8_clks_base, 812 .num_clk_base = ARRAY_SIZE(mt76x8_clks_base), 813 .clk_fixed = mt76x8_fixed_clocks, 814 .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks), 815 .clk_factor = rt305x_factor_clocks, 816 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), 817 .clk_periph = mt76x8_pherip_clks, 818 .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks), 819 }; 820 821 static const struct of_device_id mtmips_of_match[] = { 822 { 823 .compatible = "ralink,rt2880-sysc", 824 .data = &rt2880_clk_data, 825 }, 826 { 827 .compatible = "ralink,rt3050-sysc", 828 .data = &rt305x_clk_data, 829 }, 830 { 831 .compatible = "ralink,rt3052-sysc", 832 .data = &rt305x_clk_data, 833 }, 834 { 835 .compatible = "ralink,rt3352-sysc", 836 .data = &rt3352_clk_data, 837 }, 838 { 839 .compatible = "ralink,rt3883-sysc", 840 .data = &rt3883_clk_data, 841 }, 842 { 843 .compatible = "ralink,rt5350-sysc", 844 .data = &rt5350_clk_data, 845 }, 846 { 847 .compatible = "ralink,mt7620-sysc", 848 .data = &mt7620_clk_data, 849 }, 850 { 851 .compatible = "ralink,mt7628-sysc", 852 .data = &mt76x8_clk_data, 853 }, 854 { 855 .compatible = "ralink,mt7688-sysc", 856 .data = &mt76x8_clk_data, 857 }, 858 {} 859 }; 860 861 static void __init mtmips_clk_regs_init(struct device_node *node, 862 struct mtmips_clk_priv *priv) 863 { 864 u32 t; 865 866 if (!of_device_is_compatible(node, "ralink,mt7620-sysc")) 867 return; 868 869 /* 870 * When the CPU goes into sleep mode, the BUS 871 * clock will be too low for USB to function properly. 872 * Adjust the busses fractional divider to fix this 873 */ 874 regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); 875 t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); 876 t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; 877 regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t); 878 } 879 880 static void __init mtmips_clk_init(struct device_node *node) 881 { 882 const struct of_device_id *match; 883 const struct mtmips_clk_data *data; 884 struct mtmips_clk_priv *priv; 885 struct clk_hw_onecell_data *clk_data; 886 int ret, i, count; 887 888 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 889 if (!priv) 890 return; 891 892 priv->sysc = syscon_node_to_regmap(node); 893 if (IS_ERR(priv->sysc)) { 894 pr_err("Could not get sysc syscon regmap\n"); 895 goto free_clk_priv; 896 } 897 898 mtmips_clk_regs_init(node, priv); 899 900 match = of_match_node(mtmips_of_match, node); 901 if (WARN_ON(!match)) 902 return; 903 904 data = match->data; 905 priv->data = data; 906 count = priv->data->num_clk_base + priv->data->num_clk_fixed + 907 priv->data->num_clk_factor + priv->data->num_clk_periph; 908 clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL); 909 if (!clk_data) 910 goto free_clk_priv; 911 912 ret = mtmips_register_clocks(node, clk_data, priv); 913 if (ret) { 914 pr_err("Couldn't register top clocks\n"); 915 goto free_clk_data; 916 } 917 918 ret = mtmips_register_fixed_clocks(clk_data, priv); 919 if (ret) { 920 pr_err("Couldn't register fixed clocks\n"); 921 goto unreg_clk_top; 922 } 923 924 ret = mtmips_register_factor_clocks(clk_data, priv); 925 if (ret) { 926 pr_err("Couldn't register factor clocks\n"); 927 goto unreg_clk_fixed; 928 } 929 930 ret = mtmips_register_pherip_clocks(node, clk_data, priv); 931 if (ret) { 932 pr_err("Couldn't register peripheral clocks\n"); 933 goto unreg_clk_factor; 934 } 935 936 clk_data->num = count; 937 938 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 939 if (ret) { 940 pr_err("Couldn't add clk hw provider\n"); 941 goto unreg_clk_periph; 942 } 943 944 return; 945 946 unreg_clk_periph: 947 for (i = 0; i < priv->data->num_clk_periph; i++) { 948 struct mtmips_clk *sclk = &priv->data->clk_periph[i]; 949 950 clk_hw_unregister(&sclk->hw); 951 } 952 953 unreg_clk_factor: 954 for (i = 0; i < priv->data->num_clk_factor; i++) { 955 struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i]; 956 957 clk_hw_unregister_fixed_factor(sclk->hw); 958 } 959 960 unreg_clk_fixed: 961 for (i = 0; i < priv->data->num_clk_fixed; i++) { 962 struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i]; 963 964 clk_hw_unregister_fixed_rate(sclk->hw); 965 } 966 967 unreg_clk_top: 968 for (i = 0; i < priv->data->num_clk_base; i++) { 969 struct mtmips_clk *sclk = &priv->data->clk_base[i]; 970 971 clk_hw_unregister(&sclk->hw); 972 } 973 974 free_clk_data: 975 kfree(clk_data); 976 977 free_clk_priv: 978 kfree(priv); 979 } 980 CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init); 981 CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init); 982 CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init); 983 CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init); 984 CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init); 985 CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init); 986 CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init); 987 CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init); 988 CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init); 989 990 struct mtmips_rst { 991 struct reset_controller_dev rcdev; 992 struct regmap *sysc; 993 }; 994 995 static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev) 996 { 997 return container_of(dev, struct mtmips_rst, rcdev); 998 } 999 1000 static int mtmips_assert_device(struct reset_controller_dev *rcdev, 1001 unsigned long id) 1002 { 1003 struct mtmips_rst *data = to_mtmips_rst(rcdev); 1004 struct regmap *sysc = data->sysc; 1005 1006 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); 1007 } 1008 1009 static int mtmips_deassert_device(struct reset_controller_dev *rcdev, 1010 unsigned long id) 1011 { 1012 struct mtmips_rst *data = to_mtmips_rst(rcdev); 1013 struct regmap *sysc = data->sysc; 1014 1015 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); 1016 } 1017 1018 static int mtmips_reset_device(struct reset_controller_dev *rcdev, 1019 unsigned long id) 1020 { 1021 int ret; 1022 1023 ret = mtmips_assert_device(rcdev, id); 1024 if (ret < 0) 1025 return ret; 1026 1027 return mtmips_deassert_device(rcdev, id); 1028 } 1029 1030 static int mtmips_rst_xlate(struct reset_controller_dev *rcdev, 1031 const struct of_phandle_args *reset_spec) 1032 { 1033 unsigned long id = reset_spec->args[0]; 1034 1035 if (id == 0 || id >= rcdev->nr_resets) 1036 return -EINVAL; 1037 1038 return id; 1039 } 1040 1041 static const struct reset_control_ops reset_ops = { 1042 .reset = mtmips_reset_device, 1043 .assert = mtmips_assert_device, 1044 .deassert = mtmips_deassert_device 1045 }; 1046 1047 static int mtmips_reset_init(struct device *dev, struct regmap *sysc) 1048 { 1049 struct mtmips_rst *rst_data; 1050 1051 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); 1052 if (!rst_data) 1053 return -ENOMEM; 1054 1055 rst_data->sysc = sysc; 1056 rst_data->rcdev.ops = &reset_ops; 1057 rst_data->rcdev.owner = THIS_MODULE; 1058 rst_data->rcdev.nr_resets = 32; 1059 rst_data->rcdev.of_reset_n_cells = 1; 1060 rst_data->rcdev.of_xlate = mtmips_rst_xlate; 1061 rst_data->rcdev.of_node = dev_of_node(dev); 1062 1063 return devm_reset_controller_register(dev, &rst_data->rcdev); 1064 } 1065 1066 static int mtmips_clk_probe(struct platform_device *pdev) 1067 { 1068 struct device_node *np = pdev->dev.of_node; 1069 struct device *dev = &pdev->dev; 1070 struct mtmips_clk_priv *priv; 1071 int ret; 1072 1073 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1074 if (!priv) 1075 return -ENOMEM; 1076 1077 priv->sysc = syscon_node_to_regmap(np); 1078 if (IS_ERR(priv->sysc)) 1079 return dev_err_probe(dev, PTR_ERR(priv->sysc), 1080 "Could not get sysc syscon regmap\n"); 1081 1082 ret = mtmips_reset_init(dev, priv->sysc); 1083 if (ret) 1084 return dev_err_probe(dev, ret, "Could not init reset controller\n"); 1085 1086 return 0; 1087 } 1088 1089 static const struct of_device_id mtmips_clk_of_match[] = { 1090 { .compatible = "ralink,rt2880-reset" }, 1091 { .compatible = "ralink,rt2880-sysc" }, 1092 { .compatible = "ralink,rt3050-sysc" }, 1093 { .compatible = "ralink,rt3052-sysc" }, 1094 { .compatible = "ralink,rt3352-sysc" }, 1095 { .compatible = "ralink,rt3883-sysc" }, 1096 { .compatible = "ralink,rt5350-sysc" }, 1097 { .compatible = "ralink,mt7620-sysc" }, 1098 { .compatible = "ralink,mt7628-sysc" }, 1099 { .compatible = "ralink,mt7688-sysc" }, 1100 {} 1101 }; 1102 1103 static struct platform_driver mtmips_clk_driver = { 1104 .probe = mtmips_clk_probe, 1105 .driver = { 1106 .name = "mtmips-clk", 1107 .of_match_table = mtmips_clk_of_match, 1108 }, 1109 }; 1110 1111 static int __init mtmips_clk_reset_init(void) 1112 { 1113 return platform_driver_register(&mtmips_clk_driver); 1114 } 1115 arch_initcall(mtmips_clk_reset_init); 1116