1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MTMIPS SoCs Clock Driver 4 * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com> 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/clk-provider.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/reset-controller.h> 13 #include <linux/slab.h> 14 15 /* Configuration registers */ 16 #define SYSC_REG_SYSTEM_CONFIG 0x10 17 #define SYSC_REG_CLKCFG0 0x2c 18 #define SYSC_REG_RESET_CTRL 0x34 19 #define SYSC_REG_CPU_SYS_CLKCFG 0x3c 20 #define SYSC_REG_CPLL_CONFIG0 0x54 21 #define SYSC_REG_CPLL_CONFIG1 0x58 22 23 /* RT2880 SoC */ 24 #define RT2880_CONFIG_CPUCLK_SHIFT 20 25 #define RT2880_CONFIG_CPUCLK_MASK 0x3 26 #define RT2880_CONFIG_CPUCLK_250 0x0 27 #define RT2880_CONFIG_CPUCLK_266 0x1 28 #define RT2880_CONFIG_CPUCLK_280 0x2 29 #define RT2880_CONFIG_CPUCLK_300 0x3 30 31 /* RT305X SoC */ 32 #define RT305X_SYSCFG_CPUCLK_SHIFT 18 33 #define RT305X_SYSCFG_CPUCLK_MASK 0x1 34 #define RT305X_SYSCFG_CPUCLK_LOW 0x0 35 #define RT305X_SYSCFG_CPUCLK_HIGH 0x1 36 37 /* RT3352 SoC */ 38 #define RT3352_SYSCFG0_CPUCLK_SHIFT 8 39 #define RT3352_SYSCFG0_CPUCLK_MASK 0x1 40 #define RT3352_SYSCFG0_CPUCLK_LOW 0x0 41 #define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 42 43 /* RT3383 SoC */ 44 #define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17) 45 #define RT3883_SYSCFG0_CPUCLK_SHIFT 8 46 #define RT3883_SYSCFG0_CPUCLK_MASK 0x3 47 #define RT3883_SYSCFG0_CPUCLK_250 0x0 48 #define RT3883_SYSCFG0_CPUCLK_384 0x1 49 #define RT3883_SYSCFG0_CPUCLK_480 0x2 50 #define RT3883_SYSCFG0_CPUCLK_500 0x3 51 52 /* RT5350 SoC */ 53 #define RT5350_CLKCFG0_XTAL_SEL BIT(20) 54 #define RT5350_SYSCFG0_CPUCLK_SHIFT 8 55 #define RT5350_SYSCFG0_CPUCLK_MASK 0x3 56 #define RT5350_SYSCFG0_CPUCLK_360 0x0 57 #define RT5350_SYSCFG0_CPUCLK_320 0x2 58 #define RT5350_SYSCFG0_CPUCLK_300 0x3 59 60 /* MT7620 and MT76x8 SoCs */ 61 #define MT7620_XTAL_FREQ_SEL BIT(6) 62 #define CPLL_CFG0_SW_CFG BIT(31) 63 #define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16 64 #define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7 65 #define CPLL_CFG0_LC_CURFCK BIT(15) 66 #define CPLL_CFG0_BYPASS_REF_CLK BIT(14) 67 #define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10 68 #define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3 69 #define CPLL_CFG1_CPU_AUX1 BIT(25) 70 #define CPLL_CFG1_CPU_AUX0 BIT(24) 71 #define CLKCFG0_PERI_CLK_SEL BIT(4) 72 #define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16 73 #define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf 74 #define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */ 75 #define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */ 76 #define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */ 77 #define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */ 78 #define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */ 79 #define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */ 80 #define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */ 81 #define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */ 82 #define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */ 83 #define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8 84 #define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f 85 #define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0 86 #define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f 87 88 /* clock scaling */ 89 #define CLKCFG_FDIV_MASK 0x1f00 90 #define CLKCFG_FDIV_USB_VAL 0x0300 91 #define CLKCFG_FFRAC_MASK 0x001f 92 #define CLKCFG_FFRAC_USB_VAL 0x0003 93 94 struct mtmips_clk; 95 struct mtmips_clk_fixed; 96 struct mtmips_clk_factor; 97 98 struct mtmips_clk_data { 99 struct mtmips_clk *clk_base; 100 size_t num_clk_base; 101 struct mtmips_clk_fixed *clk_fixed; 102 size_t num_clk_fixed; 103 struct mtmips_clk_factor *clk_factor; 104 size_t num_clk_factor; 105 struct mtmips_clk *clk_periph; 106 size_t num_clk_periph; 107 }; 108 109 struct mtmips_clk_priv { 110 struct regmap *sysc; 111 const struct mtmips_clk_data *data; 112 }; 113 114 struct mtmips_clk { 115 struct clk_hw hw; 116 struct mtmips_clk_priv *priv; 117 }; 118 119 struct mtmips_clk_fixed { 120 const char *name; 121 const char *parent; 122 unsigned long rate; 123 struct clk_hw *hw; 124 }; 125 126 struct mtmips_clk_factor { 127 const char *name; 128 const char *parent; 129 int mult; 130 int div; 131 unsigned long flags; 132 struct clk_hw *hw; 133 }; 134 135 static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw, 136 unsigned long parent_rate) 137 { 138 return parent_rate; 139 } 140 141 static const struct clk_ops mtmips_periph_clk_ops = { 142 .recalc_rate = mtmips_pherip_clk_rate, 143 }; 144 145 #define CLK_PERIPH(_name, _parent) { \ 146 .init = &(const struct clk_init_data) { \ 147 .name = _name, \ 148 .ops = &mtmips_periph_clk_ops, \ 149 .parent_data = &(const struct clk_parent_data) {\ 150 .name = _parent, \ 151 .fw_name = _parent \ 152 }, \ 153 .num_parents = 1, \ 154 /* \ 155 * There are drivers for these SoCs that are \ 156 * older than clock driver and are not prepared \ 157 * for the clock. We don't want the kernel to \ 158 * disable anything so we add CLK_IS_CRITICAL \ 159 * flag here. \ 160 */ \ 161 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL \ 162 }, \ 163 } 164 165 static struct mtmips_clk rt2880_pherip_clks[] = { 166 { CLK_PERIPH("300100.timer", "bus") }, 167 { CLK_PERIPH("300120.watchdog", "bus") }, 168 { CLK_PERIPH("300500.uart", "bus") }, 169 { CLK_PERIPH("300900.i2c", "bus") }, 170 { CLK_PERIPH("300c00.uartlite", "bus") }, 171 { CLK_PERIPH("400000.ethernet", "bus") }, 172 { CLK_PERIPH("480000.wmac", "xtal") } 173 }; 174 175 static struct mtmips_clk rt305x_pherip_clks[] = { 176 { CLK_PERIPH("10000100.timer", "bus") }, 177 { CLK_PERIPH("10000120.watchdog", "bus") }, 178 { CLK_PERIPH("10000500.uart", "bus") }, 179 { CLK_PERIPH("10000900.i2c", "bus") }, 180 { CLK_PERIPH("10000a00.i2s", "bus") }, 181 { CLK_PERIPH("10000b00.spi", "bus") }, 182 { CLK_PERIPH("10000b40.spi", "bus") }, 183 { CLK_PERIPH("10000c00.uartlite", "bus") }, 184 { CLK_PERIPH("10100000.ethernet", "bus") }, 185 { CLK_PERIPH("10180000.wmac", "xtal") } 186 }; 187 188 static struct mtmips_clk rt5350_pherip_clks[] = { 189 { CLK_PERIPH("10000100.timer", "bus") }, 190 { CLK_PERIPH("10000120.watchdog", "bus") }, 191 { CLK_PERIPH("10000500.uart", "periph") }, 192 { CLK_PERIPH("10000900.i2c", "periph") }, 193 { CLK_PERIPH("10000a00.i2s", "periph") }, 194 { CLK_PERIPH("10000b00.spi", "bus") }, 195 { CLK_PERIPH("10000b40.spi", "bus") }, 196 { CLK_PERIPH("10000c00.uartlite", "periph") }, 197 { CLK_PERIPH("10100000.ethernet", "bus") }, 198 { CLK_PERIPH("10180000.wmac", "xtal") } 199 }; 200 201 static struct mtmips_clk mt7620_pherip_clks[] = { 202 { CLK_PERIPH("10000100.timer", "periph") }, 203 { CLK_PERIPH("10000120.watchdog", "periph") }, 204 { CLK_PERIPH("10000500.uart", "periph") }, 205 { CLK_PERIPH("10000900.i2c", "periph") }, 206 { CLK_PERIPH("10000a00.i2s", "periph") }, 207 { CLK_PERIPH("10000b00.spi", "bus") }, 208 { CLK_PERIPH("10000b40.spi", "bus") }, 209 { CLK_PERIPH("10000c00.uartlite", "periph") }, 210 { CLK_PERIPH("10180000.wmac", "xtal") } 211 }; 212 213 static struct mtmips_clk mt76x8_pherip_clks[] = { 214 { CLK_PERIPH("10000100.timer", "periph") }, 215 { CLK_PERIPH("10000120.watchdog", "periph") }, 216 { CLK_PERIPH("10000900.i2c", "periph") }, 217 { CLK_PERIPH("10000a00.i2s", "pcmi2s") }, 218 { CLK_PERIPH("10000b00.spi", "bus") }, 219 { CLK_PERIPH("10000b40.spi", "bus") }, 220 { CLK_PERIPH("10000c00.uart0", "periph") }, 221 { CLK_PERIPH("10000d00.uart1", "periph") }, 222 { CLK_PERIPH("10000e00.uart2", "periph") }, 223 { CLK_PERIPH("10300000.wmac", "xtal") } 224 }; 225 226 static int mtmips_register_pherip_clocks(struct device_node *np, 227 struct clk_hw_onecell_data *clk_data, 228 struct mtmips_clk_priv *priv) 229 { 230 struct clk_hw **hws = clk_data->hws; 231 struct mtmips_clk *sclk; 232 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed + 233 priv->data->num_clk_factor; 234 int ret, i; 235 236 for (i = 0; i < priv->data->num_clk_periph; i++) { 237 int idx = idx_start + i; 238 239 sclk = &priv->data->clk_periph[i]; 240 ret = of_clk_hw_register(np, &sclk->hw); 241 if (ret) { 242 pr_err("Couldn't register peripheral clock %d\n", idx); 243 goto err_clk_unreg; 244 } 245 246 hws[idx] = &sclk->hw; 247 } 248 249 return 0; 250 251 err_clk_unreg: 252 while (--i >= 0) { 253 sclk = &priv->data->clk_periph[i]; 254 clk_hw_unregister(&sclk->hw); 255 } 256 return ret; 257 } 258 259 #define CLK_FIXED(_name, _parent, _rate) \ 260 { \ 261 .name = _name, \ 262 .parent = _parent, \ 263 .rate = _rate \ 264 } 265 266 static struct mtmips_clk_fixed rt3883_fixed_clocks[] = { 267 CLK_FIXED("xtal", NULL, 40000000), 268 CLK_FIXED("periph", "xtal", 40000000) 269 }; 270 271 static struct mtmips_clk_fixed rt3352_fixed_clocks[] = { 272 CLK_FIXED("periph", "xtal", 40000000) 273 }; 274 275 static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = { 276 CLK_FIXED("pcmi2s", "xtal", 480000000), 277 CLK_FIXED("periph", "xtal", 40000000) 278 }; 279 280 static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data, 281 struct mtmips_clk_priv *priv) 282 { 283 struct clk_hw **hws = clk_data->hws; 284 struct mtmips_clk_fixed *sclk; 285 size_t idx_start = priv->data->num_clk_base; 286 int ret, i; 287 288 for (i = 0; i < priv->data->num_clk_fixed; i++) { 289 int idx = idx_start + i; 290 291 sclk = &priv->data->clk_fixed[i]; 292 sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name, 293 sclk->parent, 0, 294 sclk->rate); 295 if (IS_ERR(sclk->hw)) { 296 ret = PTR_ERR(sclk->hw); 297 pr_err("Couldn't register fixed clock %d\n", idx); 298 goto err_clk_unreg; 299 } 300 301 hws[idx] = sclk->hw; 302 } 303 304 return 0; 305 306 err_clk_unreg: 307 while (--i >= 0) { 308 sclk = &priv->data->clk_fixed[i]; 309 clk_hw_unregister_fixed_rate(sclk->hw); 310 } 311 return ret; 312 } 313 314 #define CLK_FACTOR(_name, _parent, _mult, _div) \ 315 { \ 316 .name = _name, \ 317 .parent = _parent, \ 318 .mult = _mult, \ 319 .div = _div, \ 320 .flags = CLK_SET_RATE_PARENT \ 321 } 322 323 static struct mtmips_clk_factor rt2880_factor_clocks[] = { 324 CLK_FACTOR("bus", "cpu", 1, 2) 325 }; 326 327 static struct mtmips_clk_factor rt305x_factor_clocks[] = { 328 CLK_FACTOR("bus", "cpu", 1, 3) 329 }; 330 331 static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data, 332 struct mtmips_clk_priv *priv) 333 { 334 struct clk_hw **hws = clk_data->hws; 335 struct mtmips_clk_factor *sclk; 336 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed; 337 int ret, i; 338 339 for (i = 0; i < priv->data->num_clk_factor; i++) { 340 int idx = idx_start + i; 341 342 sclk = &priv->data->clk_factor[i]; 343 sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name, 344 sclk->parent, sclk->flags, 345 sclk->mult, sclk->div); 346 if (IS_ERR(sclk->hw)) { 347 ret = PTR_ERR(sclk->hw); 348 pr_err("Couldn't register factor clock %d\n", idx); 349 goto err_clk_unreg; 350 } 351 352 hws[idx] = sclk->hw; 353 } 354 355 return 0; 356 357 err_clk_unreg: 358 while (--i >= 0) { 359 sclk = &priv->data->clk_factor[i]; 360 clk_hw_unregister_fixed_factor(sclk->hw); 361 } 362 return ret; 363 } 364 365 static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw) 366 { 367 return container_of(hw, struct mtmips_clk, hw); 368 } 369 370 static unsigned long rt2880_xtal_recalc_rate(struct clk_hw *hw, 371 unsigned long parent_rate) 372 { 373 return 40000000; 374 } 375 376 static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw, 377 unsigned long parent_rate) 378 { 379 struct mtmips_clk *clk = to_mtmips_clk(hw); 380 struct regmap *sysc = clk->priv->sysc; 381 u32 val; 382 383 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val); 384 if (!(val & RT5350_CLKCFG0_XTAL_SEL)) 385 return 20000000; 386 387 return 40000000; 388 } 389 390 static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw, 391 unsigned long xtal_clk) 392 { 393 struct mtmips_clk *clk = to_mtmips_clk(hw); 394 struct regmap *sysc = clk->priv->sysc; 395 u32 t; 396 397 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 398 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK; 399 400 switch (t) { 401 case RT5350_SYSCFG0_CPUCLK_360: 402 return 360000000; 403 case RT5350_SYSCFG0_CPUCLK_320: 404 return 320000000; 405 case RT5350_SYSCFG0_CPUCLK_300: 406 return 300000000; 407 default: 408 BUG(); 409 } 410 } 411 412 static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw, 413 unsigned long parent_rate) 414 { 415 if (parent_rate == 320000000) 416 return parent_rate / 4; 417 418 return parent_rate / 3; 419 } 420 421 static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw, 422 unsigned long xtal_clk) 423 { 424 struct mtmips_clk *clk = to_mtmips_clk(hw); 425 struct regmap *sysc = clk->priv->sysc; 426 u32 t; 427 428 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 429 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK; 430 431 switch (t) { 432 case RT3352_SYSCFG0_CPUCLK_LOW: 433 return 384000000; 434 case RT3352_SYSCFG0_CPUCLK_HIGH: 435 return 400000000; 436 default: 437 BUG(); 438 } 439 } 440 441 static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw, 442 unsigned long xtal_clk) 443 { 444 struct mtmips_clk *clk = to_mtmips_clk(hw); 445 struct regmap *sysc = clk->priv->sysc; 446 u32 t; 447 448 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 449 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK; 450 451 switch (t) { 452 case RT305X_SYSCFG_CPUCLK_LOW: 453 return 320000000; 454 case RT305X_SYSCFG_CPUCLK_HIGH: 455 return 384000000; 456 default: 457 BUG(); 458 } 459 } 460 461 static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw, 462 unsigned long xtal_clk) 463 { 464 struct mtmips_clk *clk = to_mtmips_clk(hw); 465 struct regmap *sysc = clk->priv->sysc; 466 u32 t; 467 468 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 469 t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK; 470 471 switch (t) { 472 case RT3883_SYSCFG0_CPUCLK_250: 473 return 250000000; 474 case RT3883_SYSCFG0_CPUCLK_384: 475 return 384000000; 476 case RT3883_SYSCFG0_CPUCLK_480: 477 return 480000000; 478 case RT3883_SYSCFG0_CPUCLK_500: 479 return 500000000; 480 default: 481 BUG(); 482 } 483 } 484 485 static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw, 486 unsigned long parent_rate) 487 { 488 struct mtmips_clk *clk = to_mtmips_clk(hw); 489 struct regmap *sysc = clk->priv->sysc; 490 u32 ddr2; 491 u32 t; 492 493 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 494 ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2; 495 496 switch (parent_rate) { 497 case 250000000: 498 return (ddr2) ? 125000000 : 83000000; 499 case 384000000: 500 return (ddr2) ? 128000000 : 96000000; 501 case 480000000: 502 return (ddr2) ? 160000000 : 120000000; 503 case 500000000: 504 return (ddr2) ? 166000000 : 125000000; 505 default: 506 WARN_ON_ONCE(parent_rate == 0); 507 return parent_rate / 4; 508 } 509 } 510 511 static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw, 512 unsigned long xtal_clk) 513 { 514 struct mtmips_clk *clk = to_mtmips_clk(hw); 515 struct regmap *sysc = clk->priv->sysc; 516 u32 t; 517 518 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 519 t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK; 520 521 switch (t) { 522 case RT2880_CONFIG_CPUCLK_250: 523 return 250000000; 524 case RT2880_CONFIG_CPUCLK_266: 525 return 266000000; 526 case RT2880_CONFIG_CPUCLK_280: 527 return 280000000; 528 case RT2880_CONFIG_CPUCLK_300: 529 return 300000000; 530 default: 531 BUG(); 532 } 533 } 534 535 static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) 536 { 537 u64 t; 538 539 t = ref_rate; 540 t *= mul; 541 t = div_u64(t, div); 542 543 return t; 544 } 545 546 static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw, 547 unsigned long parent_rate) 548 { 549 static const u32 clk_divider[] = { 2, 3, 4, 8 }; 550 struct mtmips_clk *clk = to_mtmips_clk(hw); 551 struct regmap *sysc = clk->priv->sysc; 552 unsigned long cpu_pll; 553 u32 t; 554 u32 mul; 555 u32 div; 556 557 regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t); 558 if (t & CPLL_CFG0_BYPASS_REF_CLK) { 559 cpu_pll = parent_rate; 560 } else if ((t & CPLL_CFG0_SW_CFG) == 0) { 561 cpu_pll = 600000000; 562 } else { 563 mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & 564 CPLL_CFG0_PLL_MULT_RATIO_MASK; 565 mul += 24; 566 if (t & CPLL_CFG0_LC_CURFCK) 567 mul *= 2; 568 569 div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & 570 CPLL_CFG0_PLL_DIV_RATIO_MASK; 571 572 WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider)); 573 574 cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]); 575 } 576 577 regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t); 578 if (t & CPLL_CFG1_CPU_AUX1) 579 return parent_rate; 580 581 if (t & CPLL_CFG1_CPU_AUX0) 582 return 480000000; 583 584 return cpu_pll; 585 } 586 587 static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw, 588 unsigned long parent_rate) 589 { 590 struct mtmips_clk *clk = to_mtmips_clk(hw); 591 struct regmap *sysc = clk->priv->sysc; 592 u32 t; 593 u32 mul; 594 u32 div; 595 596 regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); 597 mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; 598 div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & 599 CPU_SYS_CLKCFG_CPU_FDIV_MASK; 600 601 return mt7620_calc_rate(parent_rate, mul, div); 602 } 603 604 static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw, 605 unsigned long parent_rate) 606 { 607 static const u32 ocp_dividers[16] = { 608 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, 609 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, 610 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, 611 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, 612 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, 613 }; 614 struct mtmips_clk *clk = to_mtmips_clk(hw); 615 struct regmap *sysc = clk->priv->sysc; 616 u32 t; 617 u32 ocp_ratio; 618 u32 div; 619 620 regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); 621 ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & 622 CPU_SYS_CLKCFG_OCP_RATIO_MASK; 623 624 if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers))) 625 return parent_rate; 626 627 div = ocp_dividers[ocp_ratio]; 628 629 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) 630 return parent_rate; 631 632 return parent_rate / div; 633 } 634 635 static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw, 636 unsigned long parent_rate) 637 { 638 struct mtmips_clk *clk = to_mtmips_clk(hw); 639 struct regmap *sysc = clk->priv->sysc; 640 u32 t; 641 642 regmap_read(sysc, SYSC_REG_CLKCFG0, &t); 643 if (t & CLKCFG0_PERI_CLK_SEL) 644 return parent_rate; 645 646 return 40000000; 647 } 648 649 static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw, 650 unsigned long parent_rate) 651 { 652 struct mtmips_clk *clk = to_mtmips_clk(hw); 653 struct regmap *sysc = clk->priv->sysc; 654 u32 t; 655 656 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 657 if (t & MT7620_XTAL_FREQ_SEL) 658 return 40000000; 659 660 return 20000000; 661 } 662 663 static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw, 664 unsigned long xtal_clk) 665 { 666 if (xtal_clk == 40000000) 667 return 580000000; 668 669 return 575000000; 670 } 671 672 #define CLK_BASE(_name, _parent, _recalc) { \ 673 .init = &(const struct clk_init_data) { \ 674 .name = _name, \ 675 .ops = &(const struct clk_ops) { \ 676 .recalc_rate = _recalc, \ 677 }, \ 678 .parent_data = &(const struct clk_parent_data) { \ 679 .name = _parent, \ 680 .fw_name = _parent \ 681 }, \ 682 .num_parents = _parent ? 1 : 0 \ 683 }, \ 684 } 685 686 static struct mtmips_clk rt2880_clks_base[] = { 687 { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) }, 688 { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) } 689 }; 690 691 static struct mtmips_clk rt305x_clks_base[] = { 692 { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) }, 693 { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) } 694 }; 695 696 static struct mtmips_clk rt3352_clks_base[] = { 697 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) }, 698 { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) } 699 }; 700 701 static struct mtmips_clk rt3883_clks_base[] = { 702 { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) }, 703 { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) }, 704 { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) } 705 }; 706 707 static struct mtmips_clk rt5350_clks_base[] = { 708 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) }, 709 { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) }, 710 { CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) } 711 }; 712 713 static struct mtmips_clk mt7620_clks_base[] = { 714 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) }, 715 { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) }, 716 { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) }, 717 { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) }, 718 { CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) } 719 }; 720 721 static struct mtmips_clk mt76x8_clks_base[] = { 722 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) }, 723 { CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) } 724 }; 725 726 static int mtmips_register_clocks(struct device_node *np, 727 struct clk_hw_onecell_data *clk_data, 728 struct mtmips_clk_priv *priv) 729 { 730 struct clk_hw **hws = clk_data->hws; 731 struct mtmips_clk *sclk; 732 int ret, i; 733 734 for (i = 0; i < priv->data->num_clk_base; i++) { 735 sclk = &priv->data->clk_base[i]; 736 sclk->priv = priv; 737 ret = of_clk_hw_register(np, &sclk->hw); 738 if (ret) { 739 pr_err("Couldn't register top clock %i\n", i); 740 goto err_clk_unreg; 741 } 742 743 hws[i] = &sclk->hw; 744 } 745 746 return 0; 747 748 err_clk_unreg: 749 while (--i >= 0) { 750 sclk = &priv->data->clk_base[i]; 751 clk_hw_unregister(&sclk->hw); 752 } 753 return ret; 754 } 755 756 static const struct mtmips_clk_data rt2880_clk_data = { 757 .clk_base = rt2880_clks_base, 758 .num_clk_base = ARRAY_SIZE(rt2880_clks_base), 759 .clk_fixed = NULL, 760 .num_clk_fixed = 0, 761 .clk_factor = rt2880_factor_clocks, 762 .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks), 763 .clk_periph = rt2880_pherip_clks, 764 .num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks), 765 }; 766 767 static const struct mtmips_clk_data rt305x_clk_data = { 768 .clk_base = rt305x_clks_base, 769 .num_clk_base = ARRAY_SIZE(rt305x_clks_base), 770 .clk_fixed = NULL, 771 .num_clk_fixed = 0, 772 .clk_factor = rt305x_factor_clocks, 773 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), 774 .clk_periph = rt305x_pherip_clks, 775 .num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks), 776 }; 777 778 static const struct mtmips_clk_data rt3352_clk_data = { 779 .clk_base = rt3352_clks_base, 780 .num_clk_base = ARRAY_SIZE(rt3352_clks_base), 781 .clk_fixed = rt3352_fixed_clocks, 782 .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks), 783 .clk_factor = rt305x_factor_clocks, 784 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), 785 .clk_periph = rt5350_pherip_clks, 786 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), 787 }; 788 789 static const struct mtmips_clk_data rt3883_clk_data = { 790 .clk_base = rt3883_clks_base, 791 .num_clk_base = ARRAY_SIZE(rt3883_clks_base), 792 .clk_fixed = rt3883_fixed_clocks, 793 .num_clk_fixed = ARRAY_SIZE(rt3883_fixed_clocks), 794 .clk_factor = NULL, 795 .num_clk_factor = 0, 796 .clk_periph = rt5350_pherip_clks, 797 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), 798 }; 799 800 static const struct mtmips_clk_data rt5350_clk_data = { 801 .clk_base = rt5350_clks_base, 802 .num_clk_base = ARRAY_SIZE(rt5350_clks_base), 803 .clk_fixed = rt3352_fixed_clocks, 804 .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks), 805 .clk_factor = NULL, 806 .num_clk_factor = 0, 807 .clk_periph = rt5350_pherip_clks, 808 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), 809 }; 810 811 static const struct mtmips_clk_data mt7620_clk_data = { 812 .clk_base = mt7620_clks_base, 813 .num_clk_base = ARRAY_SIZE(mt7620_clks_base), 814 .clk_fixed = NULL, 815 .num_clk_fixed = 0, 816 .clk_factor = NULL, 817 .num_clk_factor = 0, 818 .clk_periph = mt7620_pherip_clks, 819 .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks), 820 }; 821 822 static const struct mtmips_clk_data mt76x8_clk_data = { 823 .clk_base = mt76x8_clks_base, 824 .num_clk_base = ARRAY_SIZE(mt76x8_clks_base), 825 .clk_fixed = mt76x8_fixed_clocks, 826 .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks), 827 .clk_factor = rt305x_factor_clocks, 828 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), 829 .clk_periph = mt76x8_pherip_clks, 830 .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks), 831 }; 832 833 static const struct of_device_id mtmips_of_match[] = { 834 { 835 .compatible = "ralink,rt2880-reset", 836 .data = NULL, 837 }, 838 { 839 .compatible = "ralink,rt2880-sysc", 840 .data = &rt2880_clk_data, 841 }, 842 { 843 .compatible = "ralink,rt3050-sysc", 844 .data = &rt305x_clk_data, 845 }, 846 { 847 .compatible = "ralink,rt3052-sysc", 848 .data = &rt305x_clk_data, 849 }, 850 { 851 .compatible = "ralink,rt3352-sysc", 852 .data = &rt3352_clk_data, 853 }, 854 { 855 .compatible = "ralink,rt3883-sysc", 856 .data = &rt3883_clk_data, 857 }, 858 { 859 .compatible = "ralink,rt5350-sysc", 860 .data = &rt5350_clk_data, 861 }, 862 { 863 .compatible = "ralink,mt7620-sysc", 864 .data = &mt7620_clk_data, 865 }, 866 { 867 .compatible = "ralink,mt7628-sysc", 868 .data = &mt76x8_clk_data, 869 }, 870 { 871 .compatible = "ralink,mt7688-sysc", 872 .data = &mt76x8_clk_data, 873 }, 874 {} 875 }; 876 877 static void __init mtmips_clk_regs_init(struct device_node *node, 878 struct mtmips_clk_priv *priv) 879 { 880 u32 t; 881 882 if (!of_device_is_compatible(node, "ralink,mt7620-sysc")) 883 return; 884 885 /* 886 * When the CPU goes into sleep mode, the BUS 887 * clock will be too low for USB to function properly. 888 * Adjust the busses fractional divider to fix this 889 */ 890 regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); 891 t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); 892 t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; 893 regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t); 894 } 895 896 static void __init mtmips_clk_init(struct device_node *node) 897 { 898 const struct of_device_id *match; 899 const struct mtmips_clk_data *data; 900 struct mtmips_clk_priv *priv; 901 struct clk_hw_onecell_data *clk_data; 902 int ret, i, count; 903 904 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 905 if (!priv) 906 return; 907 908 priv->sysc = syscon_node_to_regmap(node); 909 if (IS_ERR(priv->sysc)) { 910 pr_err("Could not get sysc syscon regmap\n"); 911 goto free_clk_priv; 912 } 913 914 mtmips_clk_regs_init(node, priv); 915 916 match = of_match_node(mtmips_of_match, node); 917 if (WARN_ON(!match)) 918 return; 919 920 data = match->data; 921 priv->data = data; 922 count = priv->data->num_clk_base + priv->data->num_clk_fixed + 923 priv->data->num_clk_factor + priv->data->num_clk_periph; 924 clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL); 925 if (!clk_data) 926 goto free_clk_priv; 927 928 ret = mtmips_register_clocks(node, clk_data, priv); 929 if (ret) { 930 pr_err("Couldn't register top clocks\n"); 931 goto free_clk_data; 932 } 933 934 ret = mtmips_register_fixed_clocks(clk_data, priv); 935 if (ret) { 936 pr_err("Couldn't register fixed clocks\n"); 937 goto unreg_clk_top; 938 } 939 940 ret = mtmips_register_factor_clocks(clk_data, priv); 941 if (ret) { 942 pr_err("Couldn't register factor clocks\n"); 943 goto unreg_clk_fixed; 944 } 945 946 ret = mtmips_register_pherip_clocks(node, clk_data, priv); 947 if (ret) { 948 pr_err("Couldn't register peripheral clocks\n"); 949 goto unreg_clk_factor; 950 } 951 952 clk_data->num = count; 953 954 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 955 if (ret) { 956 pr_err("Couldn't add clk hw provider\n"); 957 goto unreg_clk_periph; 958 } 959 960 return; 961 962 unreg_clk_periph: 963 for (i = 0; i < priv->data->num_clk_periph; i++) { 964 struct mtmips_clk *sclk = &priv->data->clk_periph[i]; 965 966 clk_hw_unregister(&sclk->hw); 967 } 968 969 unreg_clk_factor: 970 for (i = 0; i < priv->data->num_clk_factor; i++) { 971 struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i]; 972 973 clk_hw_unregister_fixed_factor(sclk->hw); 974 } 975 976 unreg_clk_fixed: 977 for (i = 0; i < priv->data->num_clk_fixed; i++) { 978 struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i]; 979 980 clk_hw_unregister_fixed_rate(sclk->hw); 981 } 982 983 unreg_clk_top: 984 for (i = 0; i < priv->data->num_clk_base; i++) { 985 struct mtmips_clk *sclk = &priv->data->clk_base[i]; 986 987 clk_hw_unregister(&sclk->hw); 988 } 989 990 free_clk_data: 991 kfree(clk_data); 992 993 free_clk_priv: 994 kfree(priv); 995 } 996 CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init); 997 CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init); 998 CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init); 999 CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init); 1000 CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init); 1001 CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init); 1002 CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init); 1003 CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init); 1004 CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init); 1005 1006 struct mtmips_rst { 1007 struct reset_controller_dev rcdev; 1008 struct regmap *sysc; 1009 }; 1010 1011 static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev) 1012 { 1013 return container_of(dev, struct mtmips_rst, rcdev); 1014 } 1015 1016 static int mtmips_assert_device(struct reset_controller_dev *rcdev, 1017 unsigned long id) 1018 { 1019 struct mtmips_rst *data = to_mtmips_rst(rcdev); 1020 struct regmap *sysc = data->sysc; 1021 1022 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); 1023 } 1024 1025 static int mtmips_deassert_device(struct reset_controller_dev *rcdev, 1026 unsigned long id) 1027 { 1028 struct mtmips_rst *data = to_mtmips_rst(rcdev); 1029 struct regmap *sysc = data->sysc; 1030 1031 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); 1032 } 1033 1034 static int mtmips_reset_device(struct reset_controller_dev *rcdev, 1035 unsigned long id) 1036 { 1037 int ret; 1038 1039 ret = mtmips_assert_device(rcdev, id); 1040 if (ret < 0) 1041 return ret; 1042 1043 return mtmips_deassert_device(rcdev, id); 1044 } 1045 1046 static int mtmips_rst_xlate(struct reset_controller_dev *rcdev, 1047 const struct of_phandle_args *reset_spec) 1048 { 1049 unsigned long id = reset_spec->args[0]; 1050 1051 if (id == 0 || id >= rcdev->nr_resets) 1052 return -EINVAL; 1053 1054 return id; 1055 } 1056 1057 static const struct reset_control_ops reset_ops = { 1058 .reset = mtmips_reset_device, 1059 .assert = mtmips_assert_device, 1060 .deassert = mtmips_deassert_device 1061 }; 1062 1063 static int mtmips_reset_init(struct device *dev, struct regmap *sysc) 1064 { 1065 struct mtmips_rst *rst_data; 1066 1067 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); 1068 if (!rst_data) 1069 return -ENOMEM; 1070 1071 rst_data->sysc = sysc; 1072 rst_data->rcdev.ops = &reset_ops; 1073 rst_data->rcdev.owner = THIS_MODULE; 1074 rst_data->rcdev.nr_resets = 32; 1075 rst_data->rcdev.of_reset_n_cells = 1; 1076 rst_data->rcdev.of_xlate = mtmips_rst_xlate; 1077 rst_data->rcdev.of_node = dev_of_node(dev); 1078 1079 return devm_reset_controller_register(dev, &rst_data->rcdev); 1080 } 1081 1082 static int mtmips_clk_probe(struct platform_device *pdev) 1083 { 1084 struct device_node *np = pdev->dev.of_node; 1085 struct device *dev = &pdev->dev; 1086 struct mtmips_clk_priv *priv; 1087 int ret; 1088 1089 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1090 if (!priv) 1091 return -ENOMEM; 1092 1093 priv->sysc = syscon_node_to_regmap(np); 1094 if (IS_ERR(priv->sysc)) 1095 return dev_err_probe(dev, PTR_ERR(priv->sysc), 1096 "Could not get sysc syscon regmap\n"); 1097 1098 ret = mtmips_reset_init(dev, priv->sysc); 1099 if (ret) 1100 return dev_err_probe(dev, ret, "Could not init reset controller\n"); 1101 1102 return 0; 1103 } 1104 1105 static struct platform_driver mtmips_clk_driver = { 1106 .probe = mtmips_clk_probe, 1107 .driver = { 1108 .name = "mtmips-clk", 1109 .of_match_table = mtmips_of_match, 1110 }, 1111 }; 1112 1113 static int __init mtmips_clk_reset_init(void) 1114 { 1115 return platform_driver_register(&mtmips_clk_driver); 1116 } 1117 arch_initcall(mtmips_clk_reset_init); 1118