1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Mediatek MT7621 Clock Driver 4 * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/clk-provider.h> 10 #include <linux/clk.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/slab.h> 15 #include <dt-bindings/clock/mt7621-clk.h> 16 17 /* Configuration registers */ 18 #define SYSC_REG_SYSTEM_CONFIG0 0x10 19 #define SYSC_REG_SYSTEM_CONFIG1 0x14 20 #define SYSC_REG_CLKCFG0 0x2c 21 #define SYSC_REG_CLKCFG1 0x30 22 #define SYSC_REG_CUR_CLK_STS 0x44 23 #define MEMC_REG_CPU_PLL 0x648 24 25 #define XTAL_MODE_SEL_MASK GENMASK(8, 6) 26 #define CPU_CLK_SEL_MASK GENMASK(31, 30) 27 #define CUR_CPU_FDIV_MASK GENMASK(12, 8) 28 #define CUR_CPU_FFRAC_MASK GENMASK(4, 0) 29 #define CPU_PLL_PREDIV_MASK GENMASK(13, 12) 30 #define CPU_PLL_FBDIV_MASK GENMASK(10, 4) 31 32 struct mt7621_clk_priv { 33 struct regmap *sysc; 34 struct regmap *memc; 35 }; 36 37 struct mt7621_clk { 38 struct clk_hw hw; 39 struct mt7621_clk_priv *priv; 40 }; 41 42 struct mt7621_fixed_clk { 43 u8 idx; 44 const char *name; 45 const char *parent_name; 46 unsigned long rate; 47 struct clk_hw *hw; 48 }; 49 50 struct mt7621_gate { 51 u8 idx; 52 const char *name; 53 const char *parent_name; 54 struct mt7621_clk_priv *priv; 55 u32 bit_idx; 56 struct clk_hw hw; 57 }; 58 59 #define GATE(_id, _name, _pname, _shift) \ 60 { \ 61 .idx = _id, \ 62 .name = _name, \ 63 .parent_name = _pname, \ 64 .bit_idx = _shift \ 65 } 66 67 static struct mt7621_gate mt7621_gates[] = { 68 GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)), 69 GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)), 70 GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)), 71 GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)), 72 GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)), 73 GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)), 74 GATE(MT7621_CLK_GDMA, "gdma", "bus", BIT(14)), 75 GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)), 76 GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)), 77 GATE(MT7621_CLK_I2S, "i2s", "270m", BIT(17)), 78 GATE(MT7621_CLK_SPI, "spi", "bus", BIT(18)), 79 GATE(MT7621_CLK_UART1, "uart1", "50m", BIT(19)), 80 GATE(MT7621_CLK_UART2, "uart2", "50m", BIT(20)), 81 GATE(MT7621_CLK_UART3, "uart3", "50m", BIT(21)), 82 GATE(MT7621_CLK_ETH, "eth", "50m", BIT(23)), 83 GATE(MT7621_CLK_PCIE0, "pcie0", "125m", BIT(24)), 84 GATE(MT7621_CLK_PCIE1, "pcie1", "125m", BIT(25)), 85 GATE(MT7621_CLK_PCIE2, "pcie2", "125m", BIT(26)), 86 GATE(MT7621_CLK_CRYPTO, "crypto", "250m", BIT(29)), 87 GATE(MT7621_CLK_SHXC, "shxc", "50m", BIT(30)) 88 }; 89 90 static inline struct mt7621_gate *to_mt7621_gate(struct clk_hw *hw) 91 { 92 return container_of(hw, struct mt7621_gate, hw); 93 } 94 95 static int mt7621_gate_enable(struct clk_hw *hw) 96 { 97 struct mt7621_gate *clk_gate = to_mt7621_gate(hw); 98 struct regmap *sysc = clk_gate->priv->sysc; 99 100 return regmap_update_bits(sysc, SYSC_REG_CLKCFG1, 101 clk_gate->bit_idx, clk_gate->bit_idx); 102 } 103 104 static void mt7621_gate_disable(struct clk_hw *hw) 105 { 106 struct mt7621_gate *clk_gate = to_mt7621_gate(hw); 107 struct regmap *sysc = clk_gate->priv->sysc; 108 109 regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0); 110 } 111 112 static int mt7621_gate_is_enabled(struct clk_hw *hw) 113 { 114 struct mt7621_gate *clk_gate = to_mt7621_gate(hw); 115 struct regmap *sysc = clk_gate->priv->sysc; 116 u32 val; 117 118 if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val)) 119 return 0; 120 121 return val & BIT(clk_gate->bit_idx); 122 } 123 124 static const struct clk_ops mt7621_gate_ops = { 125 .enable = mt7621_gate_enable, 126 .disable = mt7621_gate_disable, 127 .is_enabled = mt7621_gate_is_enabled, 128 }; 129 130 static int mt7621_gate_ops_init(struct device *dev, 131 struct mt7621_gate *sclk) 132 { 133 struct clk_init_data init = { 134 .flags = CLK_SET_RATE_PARENT, 135 .num_parents = 1, 136 .parent_names = &sclk->parent_name, 137 .ops = &mt7621_gate_ops, 138 .name = sclk->name, 139 }; 140 141 sclk->hw.init = &init; 142 return devm_clk_hw_register(dev, &sclk->hw); 143 } 144 145 static int mt7621_register_gates(struct device *dev, 146 struct clk_hw_onecell_data *clk_data, 147 struct mt7621_clk_priv *priv) 148 { 149 struct clk_hw **hws = clk_data->hws; 150 struct mt7621_gate *sclk; 151 int ret, i; 152 153 for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) { 154 sclk = &mt7621_gates[i]; 155 sclk->priv = priv; 156 ret = mt7621_gate_ops_init(dev, sclk); 157 if (ret) { 158 dev_err(dev, "Couldn't register clock %s\n", sclk->name); 159 goto err_clk_unreg; 160 } 161 162 hws[sclk->idx] = &sclk->hw; 163 } 164 165 return 0; 166 167 err_clk_unreg: 168 while (--i >= 0) { 169 sclk = &mt7621_gates[i]; 170 clk_hw_unregister(&sclk->hw); 171 } 172 return ret; 173 } 174 175 #define FIXED(_id, _name, _rate) \ 176 { \ 177 .idx = _id, \ 178 .name = _name, \ 179 .parent_name = "xtal", \ 180 .rate = _rate \ 181 } 182 183 static struct mt7621_fixed_clk mt7621_fixed_clks[] = { 184 FIXED(MT7621_CLK_50M, "50m", 50000000), 185 FIXED(MT7621_CLK_125M, "125m", 125000000), 186 FIXED(MT7621_CLK_150M, "150m", 150000000), 187 FIXED(MT7621_CLK_250M, "250m", 250000000), 188 FIXED(MT7621_CLK_270M, "270m", 270000000), 189 }; 190 191 static int mt7621_register_fixed_clocks(struct device *dev, 192 struct clk_hw_onecell_data *clk_data) 193 { 194 struct clk_hw **hws = clk_data->hws; 195 struct mt7621_fixed_clk *sclk; 196 int ret, i; 197 198 for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) { 199 sclk = &mt7621_fixed_clks[i]; 200 sclk->hw = clk_hw_register_fixed_rate(dev, sclk->name, 201 sclk->parent_name, 0, 202 sclk->rate); 203 if (IS_ERR(sclk->hw)) { 204 dev_err(dev, "Couldn't register clock %s\n", sclk->name); 205 ret = PTR_ERR(sclk->hw); 206 goto err_clk_unreg; 207 } 208 209 hws[sclk->idx] = sclk->hw; 210 } 211 212 return 0; 213 214 err_clk_unreg: 215 while (--i >= 0) { 216 sclk = &mt7621_fixed_clks[i]; 217 clk_hw_unregister_fixed_rate(sclk->hw); 218 } 219 return ret; 220 } 221 222 static inline struct mt7621_clk *to_mt7621_clk(struct clk_hw *hw) 223 { 224 return container_of(hw, struct mt7621_clk, hw); 225 } 226 227 static unsigned long mt7621_xtal_recalc_rate(struct clk_hw *hw, 228 unsigned long parent_rate) 229 { 230 struct mt7621_clk *clk = to_mt7621_clk(hw); 231 struct regmap *sysc = clk->priv->sysc; 232 u32 val; 233 234 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG0, &val); 235 val = FIELD_GET(XTAL_MODE_SEL_MASK, val); 236 237 if (val <= 2) 238 return 20000000; 239 if (val <= 5) 240 return 40000000; 241 242 return 25000000; 243 } 244 245 static unsigned long mt7621_cpu_recalc_rate(struct clk_hw *hw, 246 unsigned long xtal_clk) 247 { 248 static const u32 prediv_tbl[] = { 0, 1, 2, 2 }; 249 struct mt7621_clk *clk = to_mt7621_clk(hw); 250 struct regmap *sysc = clk->priv->sysc; 251 struct regmap *memc = clk->priv->memc; 252 u32 clkcfg, clk_sel, curclk, ffiv, ffrac; 253 u32 pll, prediv, fbdiv; 254 unsigned long cpu_clk; 255 256 regmap_read(sysc, SYSC_REG_CLKCFG0, &clkcfg); 257 clk_sel = FIELD_GET(CPU_CLK_SEL_MASK, clkcfg); 258 259 regmap_read(sysc, SYSC_REG_CUR_CLK_STS, &curclk); 260 ffiv = FIELD_GET(CUR_CPU_FDIV_MASK, curclk); 261 ffrac = FIELD_GET(CUR_CPU_FFRAC_MASK, curclk); 262 263 switch (clk_sel) { 264 case 0: 265 cpu_clk = 500000000; 266 break; 267 case 1: 268 regmap_read(memc, MEMC_REG_CPU_PLL, &pll); 269 fbdiv = FIELD_GET(CPU_PLL_FBDIV_MASK, pll); 270 prediv = FIELD_GET(CPU_PLL_PREDIV_MASK, pll); 271 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; 272 break; 273 default: 274 cpu_clk = xtal_clk; 275 } 276 277 return cpu_clk / ffiv * ffrac; 278 } 279 280 static unsigned long mt7621_bus_recalc_rate(struct clk_hw *hw, 281 unsigned long parent_rate) 282 { 283 return parent_rate / 4; 284 } 285 286 #define CLK_BASE(_name, _parent, _recalc) { \ 287 .init = &(struct clk_init_data) { \ 288 .name = _name, \ 289 .ops = &(const struct clk_ops) { \ 290 .recalc_rate = _recalc, \ 291 }, \ 292 .parent_data = &(const struct clk_parent_data) { \ 293 .name = _parent, \ 294 .fw_name = _parent \ 295 }, \ 296 .num_parents = _parent ? 1 : 0 \ 297 }, \ 298 } 299 300 static struct mt7621_clk mt7621_clks_base[] = { 301 { CLK_BASE("xtal", NULL, mt7621_xtal_recalc_rate) }, 302 { CLK_BASE("cpu", "xtal", mt7621_cpu_recalc_rate) }, 303 { CLK_BASE("bus", "cpu", mt7621_bus_recalc_rate) }, 304 }; 305 306 static struct clk_hw *mt7621_clk_early[MT7621_CLK_MAX]; 307 308 static int mt7621_register_early_clocks(struct device_node *np, 309 struct clk_hw_onecell_data *clk_data, 310 struct mt7621_clk_priv *priv) 311 { 312 struct clk_hw **hws = clk_data->hws; 313 struct mt7621_clk *sclk; 314 int ret, i, j; 315 316 for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) { 317 sclk = &mt7621_clks_base[i]; 318 sclk->priv = priv; 319 ret = of_clk_hw_register(np, &sclk->hw); 320 if (ret) { 321 pr_err("Couldn't register top clock %i\n", i); 322 goto err_clk_unreg; 323 } 324 325 hws[i] = &sclk->hw; 326 mt7621_clk_early[i] = &sclk->hw; 327 } 328 329 for (j = i; j < MT7621_CLK_MAX; j++) 330 mt7621_clk_early[j] = ERR_PTR(-EPROBE_DEFER); 331 332 return 0; 333 334 err_clk_unreg: 335 while (--i >= 0) { 336 sclk = &mt7621_clks_base[i]; 337 clk_hw_unregister(&sclk->hw); 338 } 339 return ret; 340 } 341 342 static void __init mt7621_clk_init(struct device_node *node) 343 { 344 struct mt7621_clk_priv *priv; 345 struct clk_hw_onecell_data *clk_data; 346 int ret, i, count; 347 348 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 349 if (!priv) 350 return; 351 352 priv->sysc = syscon_node_to_regmap(node); 353 if (IS_ERR(priv->sysc)) { 354 pr_err("Could not get sysc syscon regmap\n"); 355 goto free_clk_priv; 356 } 357 358 priv->memc = syscon_regmap_lookup_by_phandle(node, "ralink,memctl"); 359 if (IS_ERR(priv->memc)) { 360 pr_err("Could not get memc syscon regmap\n"); 361 goto free_clk_priv; 362 } 363 364 count = ARRAY_SIZE(mt7621_clks_base) + 365 ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); 366 clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL); 367 if (!clk_data) 368 goto free_clk_priv; 369 370 ret = mt7621_register_early_clocks(node, clk_data, priv); 371 if (ret) { 372 pr_err("Couldn't register top clocks\n"); 373 goto free_clk_data; 374 } 375 376 clk_data->num = count; 377 378 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 379 if (ret) { 380 pr_err("Couldn't add clk hw provider\n"); 381 goto unreg_clk_top; 382 } 383 384 return; 385 386 unreg_clk_top: 387 for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) { 388 struct mt7621_clk *sclk = &mt7621_clks_base[i]; 389 390 clk_hw_unregister(&sclk->hw); 391 } 392 393 free_clk_data: 394 kfree(clk_data); 395 396 free_clk_priv: 397 kfree(priv); 398 } 399 CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init); 400 401 static int mt7621_clk_probe(struct platform_device *pdev) 402 { 403 struct device_node *np = pdev->dev.of_node; 404 struct clk_hw_onecell_data *clk_data; 405 struct device *dev = &pdev->dev; 406 struct mt7621_clk_priv *priv; 407 int ret, i, count; 408 409 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 410 if (!priv) 411 return -ENOMEM; 412 413 priv->sysc = syscon_node_to_regmap(np); 414 if (IS_ERR(priv->sysc)) { 415 ret = PTR_ERR(priv->sysc); 416 dev_err(dev, "Could not get sysc syscon regmap\n"); 417 return ret; 418 } 419 420 priv->memc = syscon_regmap_lookup_by_phandle(np, "ralink,memctl"); 421 if (IS_ERR(priv->memc)) { 422 ret = PTR_ERR(priv->memc); 423 dev_err(dev, "Could not get memc syscon regmap\n"); 424 return ret; 425 } 426 427 count = ARRAY_SIZE(mt7621_clks_base) + 428 ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); 429 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count), 430 GFP_KERNEL); 431 if (!clk_data) 432 return -ENOMEM; 433 434 for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) 435 clk_data->hws[i] = mt7621_clk_early[i]; 436 437 ret = mt7621_register_fixed_clocks(dev, clk_data); 438 if (ret) { 439 dev_err(dev, "Couldn't register fixed clocks\n"); 440 return ret; 441 } 442 443 ret = mt7621_register_gates(dev, clk_data, priv); 444 if (ret) { 445 dev_err(dev, "Couldn't register fixed clock gates\n"); 446 goto unreg_clk_fixed; 447 } 448 449 clk_data->num = count; 450 451 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); 452 if (ret) { 453 dev_err(dev, "Couldn't add clk hw provider\n"); 454 goto unreg_clk_gates; 455 } 456 457 return 0; 458 459 unreg_clk_gates: 460 for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) { 461 struct mt7621_gate *sclk = &mt7621_gates[i]; 462 463 clk_hw_unregister(&sclk->hw); 464 } 465 466 unreg_clk_fixed: 467 for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) { 468 struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i]; 469 470 clk_hw_unregister_fixed_rate(sclk->hw); 471 } 472 473 return ret; 474 } 475 476 static const struct of_device_id mt7621_clk_of_match[] = { 477 { .compatible = "mediatek,mt7621-sysc" }, 478 {} 479 }; 480 481 static struct platform_driver mt7621_clk_driver = { 482 .probe = mt7621_clk_probe, 483 .driver = { 484 .name = "mt7621-clk", 485 .of_match_table = mt7621_clk_of_match, 486 }, 487 }; 488 builtin_platform_driver(mt7621_clk_driver); 489