1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10 
11 #include <dt-bindings/clock/qcom,videocc-sm8150.h>
12 
13 #include "common.h"
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "reset.h"
19 #include "gdsc.h"
20 
21 enum {
22 	P_BI_TCXO,
23 	P_CHIP_SLEEP_CLK,
24 	P_CORE_BI_PLL_TEST_SE,
25 	P_VIDEO_PLL0_OUT_EVEN,
26 	P_VIDEO_PLL0_OUT_MAIN,
27 	P_VIDEO_PLL0_OUT_ODD,
28 };
29 
30 static struct pll_vco trion_vco[] = {
31 	{ 249600000, 2000000000, 0 },
32 };
33 
34 static struct alpha_pll_config video_pll0_config = {
35 	.l = 0x14,
36 	.alpha = 0xD555,
37 	.config_ctl_val = 0x20485699,
38 	.config_ctl_hi_val = 0x00002267,
39 	.config_ctl_hi1_val = 0x00000024,
40 	.user_ctl_val = 0x00000000,
41 	.user_ctl_hi_val = 0x00000805,
42 	.user_ctl_hi1_val = 0x000000D0,
43 };
44 
45 static struct clk_alpha_pll video_pll0 = {
46 	.offset = 0x42c,
47 	.vco_table = trion_vco,
48 	.num_vco = ARRAY_SIZE(trion_vco),
49 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
50 	.clkr = {
51 		.hw.init = &(struct clk_init_data){
52 			.name = "video_pll0",
53 			.parent_data = &(const struct clk_parent_data){
54 				.fw_name = "bi_tcxo",
55 			},
56 			.num_parents = 1,
57 			.ops = &clk_alpha_pll_trion_ops,
58 		},
59 	},
60 };
61 
62 static const struct parent_map video_cc_parent_map_0[] = {
63 	{ P_BI_TCXO, 0 },
64 	{ P_VIDEO_PLL0_OUT_MAIN, 1 },
65 };
66 
67 static const struct clk_parent_data video_cc_parent_data_0[] = {
68 	{ .fw_name = "bi_tcxo" },
69 	{ .hw = &video_pll0.clkr.hw },
70 };
71 
72 static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
73 	F(19200000, P_BI_TCXO, 1, 0, 0),
74 	F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
75 	F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
76 	F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
77 	F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
78 	F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
79 	F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
80 	{ }
81 };
82 
83 static struct clk_rcg2 video_cc_iris_clk_src = {
84 	.cmd_rcgr = 0x7f0,
85 	.mnd_width = 0,
86 	.hid_width = 5,
87 	.parent_map = video_cc_parent_map_0,
88 	.freq_tbl = ftbl_video_cc_iris_clk_src,
89 	.clkr.hw.init = &(struct clk_init_data){
90 		.name = "video_cc_iris_clk_src",
91 		.parent_data = video_cc_parent_data_0,
92 		.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
93 		.flags = CLK_SET_RATE_PARENT,
94 		.ops = &clk_rcg2_shared_ops,
95 	},
96 };
97 
98 static struct clk_branch video_cc_iris_ahb_clk = {
99 	.halt_reg = 0x8f4,
100 	.halt_check = BRANCH_VOTED,
101 	.clkr = {
102 		.enable_reg = 0x8f4,
103 		.enable_mask = BIT(0),
104 		.hw.init = &(struct clk_init_data){
105 			.name = "video_cc_iris_ahb_clk",
106 			.parent_data = &(const struct clk_parent_data){
107 				.hw = &video_cc_iris_clk_src.clkr.hw,
108 			},
109 			.num_parents = 1,
110 			.flags = CLK_SET_RATE_PARENT,
111 			.ops = &clk_branch2_ops,
112 		},
113 	},
114 };
115 
116 static struct clk_branch video_cc_mvs0_core_clk = {
117 	.halt_reg = 0x890,
118 	.halt_check = BRANCH_VOTED,
119 	.clkr = {
120 		.enable_reg = 0x890,
121 		.enable_mask = BIT(0),
122 		.hw.init = &(struct clk_init_data){
123 			.name = "video_cc_mvs0_core_clk",
124 			.parent_data = &(const struct clk_parent_data){
125 				.hw = &video_cc_iris_clk_src.clkr.hw,
126 			},
127 			.num_parents = 1,
128 			.flags = CLK_SET_RATE_PARENT,
129 			.ops = &clk_branch2_ops,
130 		},
131 	},
132 };
133 
134 static struct clk_branch video_cc_mvs1_core_clk = {
135 	.halt_reg = 0x8d0,
136 	.halt_check = BRANCH_VOTED,
137 	.clkr = {
138 		.enable_reg = 0x8d0,
139 		.enable_mask = BIT(0),
140 		.hw.init = &(struct clk_init_data){
141 			.name = "video_cc_mvs1_core_clk",
142 			.parent_data = &(const struct clk_parent_data){
143 				.hw = &video_cc_iris_clk_src.clkr.hw,
144 			},
145 			.num_parents = 1,
146 			.flags = CLK_SET_RATE_PARENT,
147 			.ops = &clk_branch2_ops,
148 		},
149 	},
150 };
151 
152 static struct clk_branch video_cc_mvsc_core_clk = {
153 	.halt_reg = 0x850,
154 	.halt_check = BRANCH_HALT,
155 	.clkr = {
156 		.enable_reg = 0x850,
157 		.enable_mask = BIT(0),
158 		.hw.init = &(struct clk_init_data){
159 			.name = "video_cc_mvsc_core_clk",
160 			.parent_data = &(const struct clk_parent_data){
161 				.hw = &video_cc_iris_clk_src.clkr.hw,
162 			},
163 			.num_parents = 1,
164 			.flags = CLK_SET_RATE_PARENT,
165 			.ops = &clk_branch2_ops,
166 		},
167 	},
168 };
169 
170 static struct gdsc venus_gdsc = {
171 	.gdscr = 0x814,
172 	.pd = {
173 		.name = "venus_gdsc",
174 	},
175 	.flags = 0,
176 	.pwrsts = PWRSTS_OFF_ON,
177 };
178 
179 static struct gdsc vcodec0_gdsc = {
180 	.gdscr = 0x874,
181 	.pd = {
182 		.name = "vcodec0_gdsc",
183 	},
184 	.flags = HW_CTRL,
185 	.pwrsts = PWRSTS_OFF_ON,
186 };
187 
188 static struct gdsc vcodec1_gdsc = {
189 	.gdscr = 0x8b4,
190 	.pd = {
191 		.name = "vcodec1_gdsc",
192 	},
193 	.flags = HW_CTRL,
194 	.pwrsts = PWRSTS_OFF_ON,
195 };
196 static struct clk_regmap *video_cc_sm8150_clocks[] = {
197 	[VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
198 	[VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
199 	[VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
200 	[VIDEO_CC_MVS1_CORE_CLK] = &video_cc_mvs1_core_clk.clkr,
201 	[VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
202 	[VIDEO_CC_PLL0] = &video_pll0.clkr,
203 };
204 
205 static struct gdsc *video_cc_sm8150_gdscs[] = {
206 	[VENUS_GDSC] = &venus_gdsc,
207 	[VCODEC0_GDSC] = &vcodec0_gdsc,
208 	[VCODEC1_GDSC] = &vcodec1_gdsc,
209 };
210 
211 static const struct regmap_config video_cc_sm8150_regmap_config = {
212 	.reg_bits	= 32,
213 	.reg_stride	= 4,
214 	.val_bits	= 32,
215 	.max_register	= 0xb94,
216 	.fast_io	= true,
217 };
218 
219 static const struct qcom_reset_map video_cc_sm8150_resets[] = {
220 	[VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
221 };
222 
223 static const struct qcom_cc_desc video_cc_sm8150_desc = {
224 	.config = &video_cc_sm8150_regmap_config,
225 	.clks = video_cc_sm8150_clocks,
226 	.num_clks = ARRAY_SIZE(video_cc_sm8150_clocks),
227 	.resets = video_cc_sm8150_resets,
228 	.num_resets = ARRAY_SIZE(video_cc_sm8150_resets),
229 	.gdscs = video_cc_sm8150_gdscs,
230 	.num_gdscs = ARRAY_SIZE(video_cc_sm8150_gdscs),
231 };
232 
233 static const struct of_device_id video_cc_sm8150_match_table[] = {
234 	{ .compatible = "qcom,sm8150-videocc" },
235 	{ }
236 };
237 MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table);
238 
239 static int video_cc_sm8150_probe(struct platform_device *pdev)
240 {
241 	struct regmap *regmap;
242 
243 	regmap = qcom_cc_map(pdev, &video_cc_sm8150_desc);
244 	if (IS_ERR(regmap))
245 		return PTR_ERR(regmap);
246 
247 	clk_trion_pll_configure(&video_pll0, regmap, &video_pll0_config);
248 
249 	/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
250 	regmap_update_bits(regmap, 0x984, 0x1, 0x1);
251 
252 	return qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
253 }
254 
255 static struct platform_driver video_cc_sm8150_driver = {
256 	.probe = video_cc_sm8150_probe,
257 	.driver = {
258 		.name	= "video_cc-sm8150",
259 		.of_match_table = video_cc_sm8150_match_table,
260 	},
261 };
262 
263 static int __init video_cc_sm8150_init(void)
264 {
265 	return platform_driver_register(&video_cc_sm8150_driver);
266 }
267 subsys_initcall(video_cc_sm8150_init);
268 
269 static void __exit video_cc_sm8150_exit(void)
270 {
271 	platform_driver_unregister(&video_cc_sm8150_driver);
272 }
273 module_exit(video_cc_sm8150_exit);
274 
275 MODULE_LICENSE("GPL v2");
276 MODULE_DESCRIPTION("QTI VIDEOCC SM8150 Driver");
277