1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019, Linaro Ltd. 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/err.h> 8 #include <linux/platform_device.h> 9 #include <linux/module.h> 10 #include <linux/of_address.h> 11 #include <linux/pm_clock.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 15 #include <dt-bindings/clock/qcom,turingcc-qcs404.h> 16 17 #include "clk-regmap.h" 18 #include "clk-branch.h" 19 #include "common.h" 20 #include "reset.h" 21 22 static struct clk_branch turing_wrapper_aon_cbcr = { 23 .halt_reg = 0x5098, 24 .halt_check = BRANCH_HALT, 25 .clkr = { 26 .enable_reg = 0x5098, 27 .enable_mask = BIT(0), 28 .hw.init = &(struct clk_init_data) { 29 .name = "turing_wrapper_aon_clk", 30 .ops = &clk_branch2_aon_ops, 31 }, 32 }, 33 }; 34 35 static struct clk_branch turing_q6ss_ahbm_aon_cbcr = { 36 .halt_reg = 0x9000, 37 .halt_check = BRANCH_HALT, 38 .clkr = { 39 .enable_reg = 0x9000, 40 .enable_mask = BIT(0), 41 .hw.init = &(struct clk_init_data) { 42 .name = "turing_q6ss_ahbm_aon_cbcr", 43 .ops = &clk_branch2_ops, 44 }, 45 }, 46 }; 47 48 static struct clk_branch turing_q6ss_q6_axim_clk = { 49 .halt_reg = 0xb000, 50 .halt_check = BRANCH_HALT, 51 .clkr = { 52 .enable_reg = 0xb000, 53 .enable_mask = BIT(0), 54 .hw.init = &(struct clk_init_data) { 55 .name = "turing_q6ss_q6_axim_clk", 56 .ops = &clk_branch2_aon_ops, 57 }, 58 }, 59 }; 60 61 static struct clk_branch turing_q6ss_ahbs_aon_cbcr = { 62 .halt_reg = 0x10000, 63 .halt_check = BRANCH_HALT, 64 .clkr = { 65 .enable_reg = 0x10000, 66 .enable_mask = BIT(0), 67 .hw.init = &(struct clk_init_data) { 68 .name = "turing_q6ss_ahbs_aon_clk", 69 .ops = &clk_branch2_aon_ops, 70 }, 71 }, 72 }; 73 74 static struct clk_branch turing_wrapper_qos_ahbs_aon_cbcr = { 75 .halt_reg = 0x11014, 76 .halt_check = BRANCH_HALT, 77 .clkr = { 78 .enable_reg = 0x11014, 79 .enable_mask = BIT(0), 80 .hw.init = &(struct clk_init_data) { 81 .name = "turing_wrapper_qos_ahbs_aon_clk", 82 .ops = &clk_branch2_aon_ops, 83 }, 84 }, 85 }; 86 87 static struct clk_regmap *turingcc_clocks[] = { 88 [TURING_WRAPPER_AON_CLK] = &turing_wrapper_aon_cbcr.clkr, 89 [TURING_Q6SS_AHBM_AON_CLK] = &turing_q6ss_ahbm_aon_cbcr.clkr, 90 [TURING_Q6SS_Q6_AXIM_CLK] = &turing_q6ss_q6_axim_clk.clkr, 91 [TURING_Q6SS_AHBS_AON_CLK] = &turing_q6ss_ahbs_aon_cbcr.clkr, 92 [TURING_WRAPPER_QOS_AHBS_AON_CLK] = &turing_wrapper_qos_ahbs_aon_cbcr.clkr, 93 }; 94 95 static const struct regmap_config turingcc_regmap_config = { 96 .reg_bits = 32, 97 .reg_stride = 4, 98 .val_bits = 32, 99 .max_register = 0x23004, 100 .fast_io = true, 101 }; 102 103 static const struct qcom_cc_desc turingcc_desc = { 104 .config = &turingcc_regmap_config, 105 .clks = turingcc_clocks, 106 .num_clks = ARRAY_SIZE(turingcc_clocks), 107 }; 108 109 static int turingcc_probe(struct platform_device *pdev) 110 { 111 int ret; 112 113 ret = devm_pm_runtime_enable(&pdev->dev); 114 if (ret) 115 return ret; 116 117 ret = devm_pm_clk_create(&pdev->dev); 118 if (ret) 119 return ret; 120 121 ret = pm_clk_add(&pdev->dev, NULL); 122 if (ret < 0) { 123 dev_err(&pdev->dev, "failed to acquire iface clock\n"); 124 return ret; 125 } 126 127 ret = qcom_cc_probe(pdev, &turingcc_desc); 128 if (ret < 0) 129 return ret; 130 131 return 0; 132 } 133 134 static const struct dev_pm_ops turingcc_pm_ops = { 135 SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 136 }; 137 138 static const struct of_device_id turingcc_match_table[] = { 139 { .compatible = "qcom,qcs404-turingcc" }, 140 { } 141 }; 142 MODULE_DEVICE_TABLE(of, turingcc_match_table); 143 144 static struct platform_driver turingcc_driver = { 145 .probe = turingcc_probe, 146 .driver = { 147 .name = "qcs404-turingcc", 148 .of_match_table = turingcc_match_table, 149 .pm = &turingcc_pm_ops, 150 }, 151 }; 152 153 module_platform_driver(turingcc_driver); 154 155 MODULE_DESCRIPTION("Qualcomm QCS404 Turing Clock Controller"); 156 MODULE_LICENSE("GPL v2"); 157