1 /*x 2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 #include <linux/clk.h> 25 26 #include <dt-bindings/clock/qcom,mmcc-msm8996.h> 27 28 #include "common.h" 29 #include "clk-regmap.h" 30 #include "clk-regmap-divider.h" 31 #include "clk-alpha-pll.h" 32 #include "clk-rcg.h" 33 #include "clk-branch.h" 34 #include "reset.h" 35 #include "gdsc.h" 36 37 enum { 38 P_XO, 39 P_MMPLL0, 40 P_GPLL0, 41 P_GPLL0_DIV, 42 P_MMPLL1, 43 P_MMPLL9, 44 P_MMPLL2, 45 P_MMPLL8, 46 P_MMPLL3, 47 P_DSI0PLL, 48 P_DSI1PLL, 49 P_MMPLL5, 50 P_HDMIPLL, 51 P_DSI0PLL_BYTE, 52 P_DSI1PLL_BYTE, 53 P_MMPLL4, 54 }; 55 56 static const struct parent_map mmss_xo_hdmi_map[] = { 57 { P_XO, 0 }, 58 { P_HDMIPLL, 1 } 59 }; 60 61 static const char * const mmss_xo_hdmi[] = { 62 "xo", 63 "hdmipll" 64 }; 65 66 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { 67 { P_XO, 0 }, 68 { P_DSI0PLL, 1 }, 69 { P_DSI1PLL, 2 } 70 }; 71 72 static const char * const mmss_xo_dsi0pll_dsi1pll[] = { 73 "xo", 74 "dsi0pll", 75 "dsi1pll" 76 }; 77 78 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { 79 { P_XO, 0 }, 80 { P_GPLL0, 5 }, 81 { P_GPLL0_DIV, 6 } 82 }; 83 84 static const char * const mmss_xo_gpll0_gpll0_div[] = { 85 "xo", 86 "gpll0", 87 "gpll0_div" 88 }; 89 90 static const struct parent_map mmss_xo_dsibyte_map[] = { 91 { P_XO, 0 }, 92 { P_DSI0PLL_BYTE, 1 }, 93 { P_DSI1PLL_BYTE, 2 } 94 }; 95 96 static const char * const mmss_xo_dsibyte[] = { 97 "xo", 98 "dsi0pllbyte", 99 "dsi1pllbyte" 100 }; 101 102 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { 103 { P_XO, 0 }, 104 { P_MMPLL0, 1 }, 105 { P_GPLL0, 5 }, 106 { P_GPLL0_DIV, 6 } 107 }; 108 109 static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = { 110 "xo", 111 "mmpll0", 112 "gpll0", 113 "gpll0_div" 114 }; 115 116 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { 117 { P_XO, 0 }, 118 { P_MMPLL0, 1 }, 119 { P_MMPLL1, 2 }, 120 { P_GPLL0, 5 }, 121 { P_GPLL0_DIV, 6 } 122 }; 123 124 static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { 125 "xo", 126 "mmpll0", 127 "mmpll1", 128 "gpll0", 129 "gpll0_div" 130 }; 131 132 static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { 133 { P_XO, 0 }, 134 { P_MMPLL0, 1 }, 135 { P_MMPLL3, 3 }, 136 { P_GPLL0, 5 }, 137 { P_GPLL0_DIV, 6 } 138 }; 139 140 static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { 141 "xo", 142 "mmpll0", 143 "mmpll3", 144 "gpll0", 145 "gpll0_div" 146 }; 147 148 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { 149 { P_XO, 0 }, 150 { P_MMPLL0, 1 }, 151 { P_MMPLL5, 2 }, 152 { P_GPLL0, 5 }, 153 { P_GPLL0_DIV, 6 } 154 }; 155 156 static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { 157 "xo", 158 "mmpll0", 159 "mmpll5", 160 "gpll0", 161 "gpll0_div" 162 }; 163 164 static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { 165 { P_XO, 0 }, 166 { P_MMPLL0, 1 }, 167 { P_MMPLL4, 3 }, 168 { P_GPLL0, 5 }, 169 { P_GPLL0_DIV, 6 } 170 }; 171 172 static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { 173 "xo", 174 "mmpll0", 175 "mmpll4", 176 "gpll0", 177 "gpll0_div" 178 }; 179 180 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { 181 { P_XO, 0 }, 182 { P_MMPLL0, 1 }, 183 { P_MMPLL9, 2 }, 184 { P_MMPLL2, 3 }, 185 { P_MMPLL8, 4 }, 186 { P_GPLL0, 5 } 187 }; 188 189 static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { 190 "xo", 191 "mmpll0", 192 "mmpll9", 193 "mmpll2", 194 "mmpll8", 195 "gpll0" 196 }; 197 198 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { 199 { P_XO, 0 }, 200 { P_MMPLL0, 1 }, 201 { P_MMPLL9, 2 }, 202 { P_MMPLL2, 3 }, 203 { P_MMPLL8, 4 }, 204 { P_GPLL0, 5 }, 205 { P_GPLL0_DIV, 6 } 206 }; 207 208 static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { 209 "xo", 210 "mmpll0", 211 "mmpll9", 212 "mmpll2", 213 "mmpll8", 214 "gpll0", 215 "gpll0_div" 216 }; 217 218 static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { 219 { P_XO, 0 }, 220 { P_MMPLL0, 1 }, 221 { P_MMPLL1, 2 }, 222 { P_MMPLL4, 3 }, 223 { P_MMPLL3, 4 }, 224 { P_GPLL0, 5 }, 225 { P_GPLL0_DIV, 6 } 226 }; 227 228 static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { 229 "xo", 230 "mmpll0", 231 "mmpll1", 232 "mmpll4", 233 "mmpll3", 234 "gpll0", 235 "gpll0_div" 236 }; 237 238 static struct clk_fixed_factor gpll0_div = { 239 .mult = 1, 240 .div = 2, 241 .hw.init = &(struct clk_init_data){ 242 .name = "gpll0_div", 243 .parent_names = (const char *[]){ "gpll0" }, 244 .num_parents = 1, 245 .ops = &clk_fixed_factor_ops, 246 }, 247 }; 248 249 static struct pll_vco mmpll_p_vco[] = { 250 { 250000000, 500000000, 3 }, 251 { 500000000, 1000000000, 2 }, 252 { 1000000000, 1500000000, 1 }, 253 { 1500000000, 2000000000, 0 }, 254 }; 255 256 static struct pll_vco mmpll_gfx_vco[] = { 257 { 400000000, 1000000000, 2 }, 258 { 1000000000, 1500000000, 1 }, 259 { 1500000000, 2000000000, 0 }, 260 }; 261 262 static struct pll_vco mmpll_t_vco[] = { 263 { 500000000, 1500000000, 0 }, 264 }; 265 266 static struct clk_alpha_pll mmpll0_early = { 267 .offset = 0x0, 268 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 269 .vco_table = mmpll_p_vco, 270 .num_vco = ARRAY_SIZE(mmpll_p_vco), 271 .clkr = { 272 .enable_reg = 0x100, 273 .enable_mask = BIT(0), 274 .hw.init = &(struct clk_init_data){ 275 .name = "mmpll0_early", 276 .parent_names = (const char *[]){ "xo" }, 277 .num_parents = 1, 278 .ops = &clk_alpha_pll_ops, 279 }, 280 }, 281 }; 282 283 static struct clk_alpha_pll_postdiv mmpll0 = { 284 .offset = 0x0, 285 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 286 .width = 4, 287 .clkr.hw.init = &(struct clk_init_data){ 288 .name = "mmpll0", 289 .parent_names = (const char *[]){ "mmpll0_early" }, 290 .num_parents = 1, 291 .ops = &clk_alpha_pll_postdiv_ops, 292 .flags = CLK_SET_RATE_PARENT, 293 }, 294 }; 295 296 static struct clk_alpha_pll mmpll1_early = { 297 .offset = 0x30, 298 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 299 .vco_table = mmpll_p_vco, 300 .num_vco = ARRAY_SIZE(mmpll_p_vco), 301 .clkr = { 302 .enable_reg = 0x100, 303 .enable_mask = BIT(1), 304 .hw.init = &(struct clk_init_data){ 305 .name = "mmpll1_early", 306 .parent_names = (const char *[]){ "xo" }, 307 .num_parents = 1, 308 .ops = &clk_alpha_pll_ops, 309 } 310 }, 311 }; 312 313 static struct clk_alpha_pll_postdiv mmpll1 = { 314 .offset = 0x30, 315 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 316 .width = 4, 317 .clkr.hw.init = &(struct clk_init_data){ 318 .name = "mmpll1", 319 .parent_names = (const char *[]){ "mmpll1_early" }, 320 .num_parents = 1, 321 .ops = &clk_alpha_pll_postdiv_ops, 322 .flags = CLK_SET_RATE_PARENT, 323 }, 324 }; 325 326 static struct clk_alpha_pll mmpll2_early = { 327 .offset = 0x4100, 328 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 329 .vco_table = mmpll_gfx_vco, 330 .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 331 .clkr.hw.init = &(struct clk_init_data){ 332 .name = "mmpll2_early", 333 .parent_names = (const char *[]){ "xo" }, 334 .num_parents = 1, 335 .ops = &clk_alpha_pll_ops, 336 }, 337 }; 338 339 static struct clk_alpha_pll_postdiv mmpll2 = { 340 .offset = 0x4100, 341 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 342 .width = 4, 343 .clkr.hw.init = &(struct clk_init_data){ 344 .name = "mmpll2", 345 .parent_names = (const char *[]){ "mmpll2_early" }, 346 .num_parents = 1, 347 .ops = &clk_alpha_pll_postdiv_ops, 348 .flags = CLK_SET_RATE_PARENT, 349 }, 350 }; 351 352 static struct clk_alpha_pll mmpll3_early = { 353 .offset = 0x60, 354 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 355 .vco_table = mmpll_p_vco, 356 .num_vco = ARRAY_SIZE(mmpll_p_vco), 357 .clkr.hw.init = &(struct clk_init_data){ 358 .name = "mmpll3_early", 359 .parent_names = (const char *[]){ "xo" }, 360 .num_parents = 1, 361 .ops = &clk_alpha_pll_ops, 362 }, 363 }; 364 365 static struct clk_alpha_pll_postdiv mmpll3 = { 366 .offset = 0x60, 367 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 368 .width = 4, 369 .clkr.hw.init = &(struct clk_init_data){ 370 .name = "mmpll3", 371 .parent_names = (const char *[]){ "mmpll3_early" }, 372 .num_parents = 1, 373 .ops = &clk_alpha_pll_postdiv_ops, 374 .flags = CLK_SET_RATE_PARENT, 375 }, 376 }; 377 378 static struct clk_alpha_pll mmpll4_early = { 379 .offset = 0x90, 380 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 381 .vco_table = mmpll_t_vco, 382 .num_vco = ARRAY_SIZE(mmpll_t_vco), 383 .clkr.hw.init = &(struct clk_init_data){ 384 .name = "mmpll4_early", 385 .parent_names = (const char *[]){ "xo" }, 386 .num_parents = 1, 387 .ops = &clk_alpha_pll_ops, 388 }, 389 }; 390 391 static struct clk_alpha_pll_postdiv mmpll4 = { 392 .offset = 0x90, 393 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 394 .width = 2, 395 .clkr.hw.init = &(struct clk_init_data){ 396 .name = "mmpll4", 397 .parent_names = (const char *[]){ "mmpll4_early" }, 398 .num_parents = 1, 399 .ops = &clk_alpha_pll_postdiv_ops, 400 .flags = CLK_SET_RATE_PARENT, 401 }, 402 }; 403 404 static struct clk_alpha_pll mmpll5_early = { 405 .offset = 0xc0, 406 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 407 .vco_table = mmpll_p_vco, 408 .num_vco = ARRAY_SIZE(mmpll_p_vco), 409 .clkr.hw.init = &(struct clk_init_data){ 410 .name = "mmpll5_early", 411 .parent_names = (const char *[]){ "xo" }, 412 .num_parents = 1, 413 .ops = &clk_alpha_pll_ops, 414 }, 415 }; 416 417 static struct clk_alpha_pll_postdiv mmpll5 = { 418 .offset = 0xc0, 419 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 420 .width = 4, 421 .clkr.hw.init = &(struct clk_init_data){ 422 .name = "mmpll5", 423 .parent_names = (const char *[]){ "mmpll5_early" }, 424 .num_parents = 1, 425 .ops = &clk_alpha_pll_postdiv_ops, 426 .flags = CLK_SET_RATE_PARENT, 427 }, 428 }; 429 430 static struct clk_alpha_pll mmpll8_early = { 431 .offset = 0x4130, 432 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 433 .vco_table = mmpll_gfx_vco, 434 .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 435 .clkr.hw.init = &(struct clk_init_data){ 436 .name = "mmpll8_early", 437 .parent_names = (const char *[]){ "xo" }, 438 .num_parents = 1, 439 .ops = &clk_alpha_pll_ops, 440 }, 441 }; 442 443 static struct clk_alpha_pll_postdiv mmpll8 = { 444 .offset = 0x4130, 445 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 446 .width = 4, 447 .clkr.hw.init = &(struct clk_init_data){ 448 .name = "mmpll8", 449 .parent_names = (const char *[]){ "mmpll8_early" }, 450 .num_parents = 1, 451 .ops = &clk_alpha_pll_postdiv_ops, 452 .flags = CLK_SET_RATE_PARENT, 453 }, 454 }; 455 456 static struct clk_alpha_pll mmpll9_early = { 457 .offset = 0x4200, 458 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 459 .vco_table = mmpll_t_vco, 460 .num_vco = ARRAY_SIZE(mmpll_t_vco), 461 .clkr.hw.init = &(struct clk_init_data){ 462 .name = "mmpll9_early", 463 .parent_names = (const char *[]){ "xo" }, 464 .num_parents = 1, 465 .ops = &clk_alpha_pll_ops, 466 }, 467 }; 468 469 static struct clk_alpha_pll_postdiv mmpll9 = { 470 .offset = 0x4200, 471 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 472 .width = 2, 473 .clkr.hw.init = &(struct clk_init_data){ 474 .name = "mmpll9", 475 .parent_names = (const char *[]){ "mmpll9_early" }, 476 .num_parents = 1, 477 .ops = &clk_alpha_pll_postdiv_ops, 478 .flags = CLK_SET_RATE_PARENT, 479 }, 480 }; 481 482 static const struct freq_tbl ftbl_ahb_clk_src[] = { 483 F(19200000, P_XO, 1, 0, 0), 484 F(40000000, P_GPLL0_DIV, 7.5, 0, 0), 485 F(80000000, P_MMPLL0, 10, 0, 0), 486 { } 487 }; 488 489 static struct clk_rcg2 ahb_clk_src = { 490 .cmd_rcgr = 0x5000, 491 .hid_width = 5, 492 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 493 .freq_tbl = ftbl_ahb_clk_src, 494 .clkr.hw.init = &(struct clk_init_data){ 495 .name = "ahb_clk_src", 496 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 497 .num_parents = 4, 498 .ops = &clk_rcg2_ops, 499 }, 500 }; 501 502 static const struct freq_tbl ftbl_axi_clk_src[] = { 503 F(19200000, P_XO, 1, 0, 0), 504 F(75000000, P_GPLL0_DIV, 4, 0, 0), 505 F(100000000, P_GPLL0, 6, 0, 0), 506 F(171430000, P_GPLL0, 3.5, 0, 0), 507 F(200000000, P_GPLL0, 3, 0, 0), 508 F(320000000, P_MMPLL0, 2.5, 0, 0), 509 F(400000000, P_MMPLL0, 2, 0, 0), 510 { } 511 }; 512 513 static struct clk_rcg2 axi_clk_src = { 514 .cmd_rcgr = 0x5040, 515 .hid_width = 5, 516 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 517 .freq_tbl = ftbl_axi_clk_src, 518 .clkr.hw.init = &(struct clk_init_data){ 519 .name = "axi_clk_src", 520 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 521 .num_parents = 5, 522 .ops = &clk_rcg2_ops, 523 }, 524 }; 525 526 static struct clk_rcg2 maxi_clk_src = { 527 .cmd_rcgr = 0x5090, 528 .hid_width = 5, 529 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 530 .freq_tbl = ftbl_axi_clk_src, 531 .clkr.hw.init = &(struct clk_init_data){ 532 .name = "maxi_clk_src", 533 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 534 .num_parents = 5, 535 .ops = &clk_rcg2_ops, 536 }, 537 }; 538 539 static struct clk_rcg2 gfx3d_clk_src = { 540 .cmd_rcgr = 0x4000, 541 .hid_width = 5, 542 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map, 543 .clkr.hw.init = &(struct clk_init_data){ 544 .name = "gfx3d_clk_src", 545 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, 546 .num_parents = 6, 547 .ops = &clk_gfx3d_ops, 548 .flags = CLK_SET_RATE_PARENT, 549 }, 550 }; 551 552 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { 553 F(19200000, P_XO, 1, 0, 0), 554 { } 555 }; 556 557 static struct clk_rcg2 rbbmtimer_clk_src = { 558 .cmd_rcgr = 0x4090, 559 .hid_width = 5, 560 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 561 .freq_tbl = ftbl_rbbmtimer_clk_src, 562 .clkr.hw.init = &(struct clk_init_data){ 563 .name = "rbbmtimer_clk_src", 564 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 565 .num_parents = 4, 566 .ops = &clk_rcg2_ops, 567 }, 568 }; 569 570 static struct clk_rcg2 isense_clk_src = { 571 .cmd_rcgr = 0x4010, 572 .hid_width = 5, 573 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map, 574 .clkr.hw.init = &(struct clk_init_data){ 575 .name = "isense_clk_src", 576 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div, 577 .num_parents = 7, 578 .ops = &clk_rcg2_ops, 579 }, 580 }; 581 582 static const struct freq_tbl ftbl_rbcpr_clk_src[] = { 583 F(19200000, P_XO, 1, 0, 0), 584 F(50000000, P_GPLL0, 12, 0, 0), 585 { } 586 }; 587 588 static struct clk_rcg2 rbcpr_clk_src = { 589 .cmd_rcgr = 0x4060, 590 .hid_width = 5, 591 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 592 .freq_tbl = ftbl_rbcpr_clk_src, 593 .clkr.hw.init = &(struct clk_init_data){ 594 .name = "rbcpr_clk_src", 595 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 596 .num_parents = 4, 597 .ops = &clk_rcg2_ops, 598 }, 599 }; 600 601 static const struct freq_tbl ftbl_video_core_clk_src[] = { 602 F(75000000, P_GPLL0_DIV, 4, 0, 0), 603 F(150000000, P_GPLL0, 4, 0, 0), 604 F(346666667, P_MMPLL3, 3, 0, 0), 605 F(520000000, P_MMPLL3, 2, 0, 0), 606 { } 607 }; 608 609 static struct clk_rcg2 video_core_clk_src = { 610 .cmd_rcgr = 0x1000, 611 .mnd_width = 8, 612 .hid_width = 5, 613 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 614 .freq_tbl = ftbl_video_core_clk_src, 615 .clkr.hw.init = &(struct clk_init_data){ 616 .name = "video_core_clk_src", 617 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 618 .num_parents = 5, 619 .ops = &clk_rcg2_ops, 620 }, 621 }; 622 623 static struct clk_rcg2 video_subcore0_clk_src = { 624 .cmd_rcgr = 0x1060, 625 .mnd_width = 8, 626 .hid_width = 5, 627 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 628 .freq_tbl = ftbl_video_core_clk_src, 629 .clkr.hw.init = &(struct clk_init_data){ 630 .name = "video_subcore0_clk_src", 631 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 632 .num_parents = 5, 633 .ops = &clk_rcg2_ops, 634 }, 635 }; 636 637 static struct clk_rcg2 video_subcore1_clk_src = { 638 .cmd_rcgr = 0x1080, 639 .mnd_width = 8, 640 .hid_width = 5, 641 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 642 .freq_tbl = ftbl_video_core_clk_src, 643 .clkr.hw.init = &(struct clk_init_data){ 644 .name = "video_subcore1_clk_src", 645 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 646 .num_parents = 5, 647 .ops = &clk_rcg2_ops, 648 }, 649 }; 650 651 static struct clk_rcg2 pclk0_clk_src = { 652 .cmd_rcgr = 0x2000, 653 .mnd_width = 8, 654 .hid_width = 5, 655 .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 656 .clkr.hw.init = &(struct clk_init_data){ 657 .name = "pclk0_clk_src", 658 .parent_names = mmss_xo_dsi0pll_dsi1pll, 659 .num_parents = 3, 660 .ops = &clk_pixel_ops, 661 .flags = CLK_SET_RATE_PARENT, 662 }, 663 }; 664 665 static struct clk_rcg2 pclk1_clk_src = { 666 .cmd_rcgr = 0x2020, 667 .mnd_width = 8, 668 .hid_width = 5, 669 .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 670 .clkr.hw.init = &(struct clk_init_data){ 671 .name = "pclk1_clk_src", 672 .parent_names = mmss_xo_dsi0pll_dsi1pll, 673 .num_parents = 3, 674 .ops = &clk_pixel_ops, 675 .flags = CLK_SET_RATE_PARENT, 676 }, 677 }; 678 679 static const struct freq_tbl ftbl_mdp_clk_src[] = { 680 F(85714286, P_GPLL0, 7, 0, 0), 681 F(100000000, P_GPLL0, 6, 0, 0), 682 F(150000000, P_GPLL0, 4, 0, 0), 683 F(171428571, P_GPLL0, 3.5, 0, 0), 684 F(200000000, P_GPLL0, 3, 0, 0), 685 F(275000000, P_MMPLL5, 3, 0, 0), 686 F(300000000, P_GPLL0, 2, 0, 0), 687 F(330000000, P_MMPLL5, 2.5, 0, 0), 688 F(412500000, P_MMPLL5, 2, 0, 0), 689 { } 690 }; 691 692 static struct clk_rcg2 mdp_clk_src = { 693 .cmd_rcgr = 0x2040, 694 .hid_width = 5, 695 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map, 696 .freq_tbl = ftbl_mdp_clk_src, 697 .clkr.hw.init = &(struct clk_init_data){ 698 .name = "mdp_clk_src", 699 .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, 700 .num_parents = 5, 701 .ops = &clk_rcg2_ops, 702 }, 703 }; 704 705 static struct freq_tbl extpclk_freq_tbl[] = { 706 { .src = P_HDMIPLL }, 707 { } 708 }; 709 710 static struct clk_rcg2 extpclk_clk_src = { 711 .cmd_rcgr = 0x2060, 712 .hid_width = 5, 713 .parent_map = mmss_xo_hdmi_map, 714 .freq_tbl = extpclk_freq_tbl, 715 .clkr.hw.init = &(struct clk_init_data){ 716 .name = "extpclk_clk_src", 717 .parent_names = mmss_xo_hdmi, 718 .num_parents = 2, 719 .ops = &clk_byte_ops, 720 .flags = CLK_SET_RATE_PARENT, 721 }, 722 }; 723 724 static struct freq_tbl ftbl_mdss_vsync_clk[] = { 725 F(19200000, P_XO, 1, 0, 0), 726 { } 727 }; 728 729 static struct clk_rcg2 vsync_clk_src = { 730 .cmd_rcgr = 0x2080, 731 .hid_width = 5, 732 .parent_map = mmss_xo_gpll0_gpll0_div_map, 733 .freq_tbl = ftbl_mdss_vsync_clk, 734 .clkr.hw.init = &(struct clk_init_data){ 735 .name = "vsync_clk_src", 736 .parent_names = mmss_xo_gpll0_gpll0_div, 737 .num_parents = 3, 738 .ops = &clk_rcg2_ops, 739 }, 740 }; 741 742 static struct freq_tbl ftbl_mdss_hdmi_clk[] = { 743 F(19200000, P_XO, 1, 0, 0), 744 { } 745 }; 746 747 static struct clk_rcg2 hdmi_clk_src = { 748 .cmd_rcgr = 0x2100, 749 .hid_width = 5, 750 .parent_map = mmss_xo_gpll0_gpll0_div_map, 751 .freq_tbl = ftbl_mdss_hdmi_clk, 752 .clkr.hw.init = &(struct clk_init_data){ 753 .name = "hdmi_clk_src", 754 .parent_names = mmss_xo_gpll0_gpll0_div, 755 .num_parents = 3, 756 .ops = &clk_rcg2_ops, 757 }, 758 }; 759 760 static struct clk_rcg2 byte0_clk_src = { 761 .cmd_rcgr = 0x2120, 762 .hid_width = 5, 763 .parent_map = mmss_xo_dsibyte_map, 764 .clkr.hw.init = &(struct clk_init_data){ 765 .name = "byte0_clk_src", 766 .parent_names = mmss_xo_dsibyte, 767 .num_parents = 3, 768 .ops = &clk_byte2_ops, 769 .flags = CLK_SET_RATE_PARENT, 770 }, 771 }; 772 773 static struct clk_rcg2 byte1_clk_src = { 774 .cmd_rcgr = 0x2140, 775 .hid_width = 5, 776 .parent_map = mmss_xo_dsibyte_map, 777 .clkr.hw.init = &(struct clk_init_data){ 778 .name = "byte1_clk_src", 779 .parent_names = mmss_xo_dsibyte, 780 .num_parents = 3, 781 .ops = &clk_byte2_ops, 782 .flags = CLK_SET_RATE_PARENT, 783 }, 784 }; 785 786 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { 787 F(19200000, P_XO, 1, 0, 0), 788 { } 789 }; 790 791 static struct clk_rcg2 esc0_clk_src = { 792 .cmd_rcgr = 0x2160, 793 .hid_width = 5, 794 .parent_map = mmss_xo_dsibyte_map, 795 .freq_tbl = ftbl_mdss_esc0_1_clk, 796 .clkr.hw.init = &(struct clk_init_data){ 797 .name = "esc0_clk_src", 798 .parent_names = mmss_xo_dsibyte, 799 .num_parents = 3, 800 .ops = &clk_rcg2_ops, 801 }, 802 }; 803 804 static struct clk_rcg2 esc1_clk_src = { 805 .cmd_rcgr = 0x2180, 806 .hid_width = 5, 807 .parent_map = mmss_xo_dsibyte_map, 808 .freq_tbl = ftbl_mdss_esc0_1_clk, 809 .clkr.hw.init = &(struct clk_init_data){ 810 .name = "esc1_clk_src", 811 .parent_names = mmss_xo_dsibyte, 812 .num_parents = 3, 813 .ops = &clk_rcg2_ops, 814 }, 815 }; 816 817 static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { 818 F(10000, P_XO, 16, 1, 120), 819 F(24000, P_XO, 16, 1, 50), 820 F(6000000, P_GPLL0_DIV, 10, 1, 5), 821 F(12000000, P_GPLL0_DIV, 1, 1, 25), 822 F(13000000, P_GPLL0_DIV, 2, 13, 150), 823 F(24000000, P_GPLL0_DIV, 1, 2, 25), 824 { } 825 }; 826 827 static struct clk_rcg2 camss_gp0_clk_src = { 828 .cmd_rcgr = 0x3420, 829 .mnd_width = 8, 830 .hid_width = 5, 831 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 832 .freq_tbl = ftbl_camss_gp0_clk_src, 833 .clkr.hw.init = &(struct clk_init_data){ 834 .name = "camss_gp0_clk_src", 835 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 836 .num_parents = 5, 837 .ops = &clk_rcg2_ops, 838 }, 839 }; 840 841 static struct clk_rcg2 camss_gp1_clk_src = { 842 .cmd_rcgr = 0x3450, 843 .mnd_width = 8, 844 .hid_width = 5, 845 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 846 .freq_tbl = ftbl_camss_gp0_clk_src, 847 .clkr.hw.init = &(struct clk_init_data){ 848 .name = "camss_gp1_clk_src", 849 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 850 .num_parents = 5, 851 .ops = &clk_rcg2_ops, 852 }, 853 }; 854 855 static const struct freq_tbl ftbl_mclk0_clk_src[] = { 856 F(4800000, P_XO, 4, 0, 0), 857 F(6000000, P_GPLL0_DIV, 10, 1, 5), 858 F(8000000, P_GPLL0_DIV, 1, 2, 75), 859 F(9600000, P_XO, 2, 0, 0), 860 F(16666667, P_GPLL0_DIV, 2, 1, 9), 861 F(19200000, P_XO, 1, 0, 0), 862 F(24000000, P_GPLL0_DIV, 1, 2, 25), 863 F(33333333, P_GPLL0_DIV, 1, 1, 9), 864 F(48000000, P_GPLL0, 1, 2, 25), 865 F(66666667, P_GPLL0, 1, 1, 9), 866 { } 867 }; 868 869 static struct clk_rcg2 mclk0_clk_src = { 870 .cmd_rcgr = 0x3360, 871 .mnd_width = 8, 872 .hid_width = 5, 873 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 874 .freq_tbl = ftbl_mclk0_clk_src, 875 .clkr.hw.init = &(struct clk_init_data){ 876 .name = "mclk0_clk_src", 877 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 878 .num_parents = 5, 879 .ops = &clk_rcg2_ops, 880 }, 881 }; 882 883 static struct clk_rcg2 mclk1_clk_src = { 884 .cmd_rcgr = 0x3390, 885 .mnd_width = 8, 886 .hid_width = 5, 887 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 888 .freq_tbl = ftbl_mclk0_clk_src, 889 .clkr.hw.init = &(struct clk_init_data){ 890 .name = "mclk1_clk_src", 891 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 892 .num_parents = 5, 893 .ops = &clk_rcg2_ops, 894 }, 895 }; 896 897 static struct clk_rcg2 mclk2_clk_src = { 898 .cmd_rcgr = 0x33c0, 899 .mnd_width = 8, 900 .hid_width = 5, 901 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 902 .freq_tbl = ftbl_mclk0_clk_src, 903 .clkr.hw.init = &(struct clk_init_data){ 904 .name = "mclk2_clk_src", 905 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 906 .num_parents = 5, 907 .ops = &clk_rcg2_ops, 908 }, 909 }; 910 911 static struct clk_rcg2 mclk3_clk_src = { 912 .cmd_rcgr = 0x33f0, 913 .mnd_width = 8, 914 .hid_width = 5, 915 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 916 .freq_tbl = ftbl_mclk0_clk_src, 917 .clkr.hw.init = &(struct clk_init_data){ 918 .name = "mclk3_clk_src", 919 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 920 .num_parents = 5, 921 .ops = &clk_rcg2_ops, 922 }, 923 }; 924 925 static const struct freq_tbl ftbl_cci_clk_src[] = { 926 F(19200000, P_XO, 1, 0, 0), 927 F(37500000, P_GPLL0, 16, 0, 0), 928 F(50000000, P_GPLL0, 12, 0, 0), 929 F(100000000, P_GPLL0, 6, 0, 0), 930 { } 931 }; 932 933 static struct clk_rcg2 cci_clk_src = { 934 .cmd_rcgr = 0x3300, 935 .mnd_width = 8, 936 .hid_width = 5, 937 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 938 .freq_tbl = ftbl_cci_clk_src, 939 .clkr.hw.init = &(struct clk_init_data){ 940 .name = "cci_clk_src", 941 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 942 .num_parents = 5, 943 .ops = &clk_rcg2_ops, 944 }, 945 }; 946 947 static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { 948 F(100000000, P_GPLL0_DIV, 3, 0, 0), 949 F(200000000, P_GPLL0, 3, 0, 0), 950 F(266666667, P_MMPLL0, 3, 0, 0), 951 { } 952 }; 953 954 static struct clk_rcg2 csi0phytimer_clk_src = { 955 .cmd_rcgr = 0x3000, 956 .hid_width = 5, 957 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 958 .freq_tbl = ftbl_csi0phytimer_clk_src, 959 .clkr.hw.init = &(struct clk_init_data){ 960 .name = "csi0phytimer_clk_src", 961 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 962 .num_parents = 7, 963 .ops = &clk_rcg2_ops, 964 }, 965 }; 966 967 static struct clk_rcg2 csi1phytimer_clk_src = { 968 .cmd_rcgr = 0x3030, 969 .hid_width = 5, 970 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 971 .freq_tbl = ftbl_csi0phytimer_clk_src, 972 .clkr.hw.init = &(struct clk_init_data){ 973 .name = "csi1phytimer_clk_src", 974 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 975 .num_parents = 7, 976 .ops = &clk_rcg2_ops, 977 }, 978 }; 979 980 static struct clk_rcg2 csi2phytimer_clk_src = { 981 .cmd_rcgr = 0x3060, 982 .hid_width = 5, 983 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 984 .freq_tbl = ftbl_csi0phytimer_clk_src, 985 .clkr.hw.init = &(struct clk_init_data){ 986 .name = "csi2phytimer_clk_src", 987 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 988 .num_parents = 7, 989 .ops = &clk_rcg2_ops, 990 }, 991 }; 992 993 static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = { 994 F(100000000, P_GPLL0_DIV, 3, 0, 0), 995 F(200000000, P_GPLL0, 3, 0, 0), 996 F(320000000, P_MMPLL4, 3, 0, 0), 997 F(384000000, P_MMPLL4, 2.5, 0, 0), 998 { } 999 }; 1000 1001 static struct clk_rcg2 csiphy0_3p_clk_src = { 1002 .cmd_rcgr = 0x3240, 1003 .hid_width = 5, 1004 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1005 .freq_tbl = ftbl_csiphy0_3p_clk_src, 1006 .clkr.hw.init = &(struct clk_init_data){ 1007 .name = "csiphy0_3p_clk_src", 1008 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1009 .num_parents = 7, 1010 .ops = &clk_rcg2_ops, 1011 }, 1012 }; 1013 1014 static struct clk_rcg2 csiphy1_3p_clk_src = { 1015 .cmd_rcgr = 0x3260, 1016 .hid_width = 5, 1017 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1018 .freq_tbl = ftbl_csiphy0_3p_clk_src, 1019 .clkr.hw.init = &(struct clk_init_data){ 1020 .name = "csiphy1_3p_clk_src", 1021 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1022 .num_parents = 7, 1023 .ops = &clk_rcg2_ops, 1024 }, 1025 }; 1026 1027 static struct clk_rcg2 csiphy2_3p_clk_src = { 1028 .cmd_rcgr = 0x3280, 1029 .hid_width = 5, 1030 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1031 .freq_tbl = ftbl_csiphy0_3p_clk_src, 1032 .clkr.hw.init = &(struct clk_init_data){ 1033 .name = "csiphy2_3p_clk_src", 1034 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1035 .num_parents = 7, 1036 .ops = &clk_rcg2_ops, 1037 }, 1038 }; 1039 1040 static const struct freq_tbl ftbl_jpeg0_clk_src[] = { 1041 F(75000000, P_GPLL0_DIV, 4, 0, 0), 1042 F(150000000, P_GPLL0, 4, 0, 0), 1043 F(228571429, P_MMPLL0, 3.5, 0, 0), 1044 F(266666667, P_MMPLL0, 3, 0, 0), 1045 F(320000000, P_MMPLL0, 2.5, 0, 0), 1046 F(480000000, P_MMPLL4, 2, 0, 0), 1047 { } 1048 }; 1049 1050 static struct clk_rcg2 jpeg0_clk_src = { 1051 .cmd_rcgr = 0x3500, 1052 .hid_width = 5, 1053 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1054 .freq_tbl = ftbl_jpeg0_clk_src, 1055 .clkr.hw.init = &(struct clk_init_data){ 1056 .name = "jpeg0_clk_src", 1057 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1058 .num_parents = 7, 1059 .ops = &clk_rcg2_ops, 1060 }, 1061 }; 1062 1063 static const struct freq_tbl ftbl_jpeg2_clk_src[] = { 1064 F(75000000, P_GPLL0_DIV, 4, 0, 0), 1065 F(150000000, P_GPLL0, 4, 0, 0), 1066 F(228571429, P_MMPLL0, 3.5, 0, 0), 1067 F(266666667, P_MMPLL0, 3, 0, 0), 1068 F(320000000, P_MMPLL0, 2.5, 0, 0), 1069 { } 1070 }; 1071 1072 static struct clk_rcg2 jpeg2_clk_src = { 1073 .cmd_rcgr = 0x3540, 1074 .hid_width = 5, 1075 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1076 .freq_tbl = ftbl_jpeg2_clk_src, 1077 .clkr.hw.init = &(struct clk_init_data){ 1078 .name = "jpeg2_clk_src", 1079 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1080 .num_parents = 7, 1081 .ops = &clk_rcg2_ops, 1082 }, 1083 }; 1084 1085 static struct clk_rcg2 jpeg_dma_clk_src = { 1086 .cmd_rcgr = 0x3560, 1087 .hid_width = 5, 1088 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1089 .freq_tbl = ftbl_jpeg0_clk_src, 1090 .clkr.hw.init = &(struct clk_init_data){ 1091 .name = "jpeg_dma_clk_src", 1092 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1093 .num_parents = 7, 1094 .ops = &clk_rcg2_ops, 1095 }, 1096 }; 1097 1098 static const struct freq_tbl ftbl_vfe0_clk_src[] = { 1099 F(75000000, P_GPLL0_DIV, 4, 0, 0), 1100 F(100000000, P_GPLL0_DIV, 3, 0, 0), 1101 F(300000000, P_GPLL0, 2, 0, 0), 1102 F(320000000, P_MMPLL0, 2.5, 0, 0), 1103 F(480000000, P_MMPLL4, 2, 0, 0), 1104 F(600000000, P_GPLL0, 1, 0, 0), 1105 { } 1106 }; 1107 1108 static struct clk_rcg2 vfe0_clk_src = { 1109 .cmd_rcgr = 0x3600, 1110 .hid_width = 5, 1111 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1112 .freq_tbl = ftbl_vfe0_clk_src, 1113 .clkr.hw.init = &(struct clk_init_data){ 1114 .name = "vfe0_clk_src", 1115 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1116 .num_parents = 7, 1117 .ops = &clk_rcg2_ops, 1118 }, 1119 }; 1120 1121 static struct clk_rcg2 vfe1_clk_src = { 1122 .cmd_rcgr = 0x3620, 1123 .hid_width = 5, 1124 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1125 .freq_tbl = ftbl_vfe0_clk_src, 1126 .clkr.hw.init = &(struct clk_init_data){ 1127 .name = "vfe1_clk_src", 1128 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1129 .num_parents = 7, 1130 .ops = &clk_rcg2_ops, 1131 }, 1132 }; 1133 1134 static const struct freq_tbl ftbl_cpp_clk_src[] = { 1135 F(100000000, P_GPLL0_DIV, 3, 0, 0), 1136 F(200000000, P_GPLL0, 3, 0, 0), 1137 F(320000000, P_MMPLL0, 2.5, 0, 0), 1138 F(480000000, P_MMPLL4, 2, 0, 0), 1139 F(640000000, P_MMPLL4, 1.5, 0, 0), 1140 { } 1141 }; 1142 1143 static struct clk_rcg2 cpp_clk_src = { 1144 .cmd_rcgr = 0x3640, 1145 .hid_width = 5, 1146 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1147 .freq_tbl = ftbl_cpp_clk_src, 1148 .clkr.hw.init = &(struct clk_init_data){ 1149 .name = "cpp_clk_src", 1150 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1151 .num_parents = 7, 1152 .ops = &clk_rcg2_ops, 1153 }, 1154 }; 1155 1156 static const struct freq_tbl ftbl_csi0_clk_src[] = { 1157 F(100000000, P_GPLL0_DIV, 3, 0, 0), 1158 F(200000000, P_GPLL0, 3, 0, 0), 1159 F(266666667, P_MMPLL0, 3, 0, 0), 1160 F(480000000, P_MMPLL4, 2, 0, 0), 1161 F(600000000, P_GPLL0, 1, 0, 0), 1162 { } 1163 }; 1164 1165 static struct clk_rcg2 csi0_clk_src = { 1166 .cmd_rcgr = 0x3090, 1167 .hid_width = 5, 1168 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1169 .freq_tbl = ftbl_csi0_clk_src, 1170 .clkr.hw.init = &(struct clk_init_data){ 1171 .name = "csi0_clk_src", 1172 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1173 .num_parents = 7, 1174 .ops = &clk_rcg2_ops, 1175 }, 1176 }; 1177 1178 static struct clk_rcg2 csi1_clk_src = { 1179 .cmd_rcgr = 0x3100, 1180 .hid_width = 5, 1181 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1182 .freq_tbl = ftbl_csi0_clk_src, 1183 .clkr.hw.init = &(struct clk_init_data){ 1184 .name = "csi1_clk_src", 1185 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1186 .num_parents = 7, 1187 .ops = &clk_rcg2_ops, 1188 }, 1189 }; 1190 1191 static struct clk_rcg2 csi2_clk_src = { 1192 .cmd_rcgr = 0x3160, 1193 .hid_width = 5, 1194 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1195 .freq_tbl = ftbl_csi0_clk_src, 1196 .clkr.hw.init = &(struct clk_init_data){ 1197 .name = "csi2_clk_src", 1198 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1199 .num_parents = 7, 1200 .ops = &clk_rcg2_ops, 1201 }, 1202 }; 1203 1204 static struct clk_rcg2 csi3_clk_src = { 1205 .cmd_rcgr = 0x31c0, 1206 .hid_width = 5, 1207 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1208 .freq_tbl = ftbl_csi0_clk_src, 1209 .clkr.hw.init = &(struct clk_init_data){ 1210 .name = "csi3_clk_src", 1211 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1212 .num_parents = 7, 1213 .ops = &clk_rcg2_ops, 1214 }, 1215 }; 1216 1217 static const struct freq_tbl ftbl_fd_core_clk_src[] = { 1218 F(100000000, P_GPLL0_DIV, 3, 0, 0), 1219 F(200000000, P_GPLL0, 3, 0, 0), 1220 F(400000000, P_MMPLL0, 2, 0, 0), 1221 { } 1222 }; 1223 1224 static struct clk_rcg2 fd_core_clk_src = { 1225 .cmd_rcgr = 0x3b00, 1226 .hid_width = 5, 1227 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 1228 .freq_tbl = ftbl_fd_core_clk_src, 1229 .clkr.hw.init = &(struct clk_init_data){ 1230 .name = "fd_core_clk_src", 1231 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 1232 .num_parents = 5, 1233 .ops = &clk_rcg2_ops, 1234 }, 1235 }; 1236 1237 static struct clk_branch mmss_mmagic_ahb_clk = { 1238 .halt_reg = 0x5024, 1239 .clkr = { 1240 .enable_reg = 0x5024, 1241 .enable_mask = BIT(0), 1242 .hw.init = &(struct clk_init_data){ 1243 .name = "mmss_mmagic_ahb_clk", 1244 .parent_names = (const char *[]){ "ahb_clk_src" }, 1245 .num_parents = 1, 1246 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1247 .ops = &clk_branch2_ops, 1248 }, 1249 }, 1250 }; 1251 1252 static struct clk_branch mmss_mmagic_cfg_ahb_clk = { 1253 .halt_reg = 0x5054, 1254 .clkr = { 1255 .enable_reg = 0x5054, 1256 .enable_mask = BIT(0), 1257 .hw.init = &(struct clk_init_data){ 1258 .name = "mmss_mmagic_cfg_ahb_clk", 1259 .parent_names = (const char *[]){ "ahb_clk_src" }, 1260 .num_parents = 1, 1261 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1262 .ops = &clk_branch2_ops, 1263 }, 1264 }, 1265 }; 1266 1267 static struct clk_branch mmss_misc_ahb_clk = { 1268 .halt_reg = 0x5018, 1269 .clkr = { 1270 .enable_reg = 0x5018, 1271 .enable_mask = BIT(0), 1272 .hw.init = &(struct clk_init_data){ 1273 .name = "mmss_misc_ahb_clk", 1274 .parent_names = (const char *[]){ "ahb_clk_src" }, 1275 .num_parents = 1, 1276 .flags = CLK_SET_RATE_PARENT, 1277 .ops = &clk_branch2_ops, 1278 }, 1279 }, 1280 }; 1281 1282 static struct clk_branch mmss_misc_cxo_clk = { 1283 .halt_reg = 0x5014, 1284 .clkr = { 1285 .enable_reg = 0x5014, 1286 .enable_mask = BIT(0), 1287 .hw.init = &(struct clk_init_data){ 1288 .name = "mmss_misc_cxo_clk", 1289 .parent_names = (const char *[]){ "xo" }, 1290 .num_parents = 1, 1291 .ops = &clk_branch2_ops, 1292 }, 1293 }, 1294 }; 1295 1296 static struct clk_branch mmss_mmagic_maxi_clk = { 1297 .halt_reg = 0x5074, 1298 .clkr = { 1299 .enable_reg = 0x5074, 1300 .enable_mask = BIT(0), 1301 .hw.init = &(struct clk_init_data){ 1302 .name = "mmss_mmagic_maxi_clk", 1303 .parent_names = (const char *[]){ "maxi_clk_src" }, 1304 .num_parents = 1, 1305 .flags = CLK_SET_RATE_PARENT, 1306 .ops = &clk_branch2_ops, 1307 }, 1308 }, 1309 }; 1310 1311 static struct clk_branch mmagic_camss_axi_clk = { 1312 .halt_reg = 0x3c44, 1313 .clkr = { 1314 .enable_reg = 0x3c44, 1315 .enable_mask = BIT(0), 1316 .hw.init = &(struct clk_init_data){ 1317 .name = "mmagic_camss_axi_clk", 1318 .parent_names = (const char *[]){ "axi_clk_src" }, 1319 .num_parents = 1, 1320 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1321 .ops = &clk_branch2_ops, 1322 }, 1323 }, 1324 }; 1325 1326 static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = { 1327 .halt_reg = 0x3c48, 1328 .clkr = { 1329 .enable_reg = 0x3c48, 1330 .enable_mask = BIT(0), 1331 .hw.init = &(struct clk_init_data){ 1332 .name = "mmagic_camss_noc_cfg_ahb_clk", 1333 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1334 .num_parents = 1, 1335 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1336 .ops = &clk_branch2_ops, 1337 }, 1338 }, 1339 }; 1340 1341 static struct clk_branch smmu_vfe_ahb_clk = { 1342 .halt_reg = 0x3c04, 1343 .clkr = { 1344 .enable_reg = 0x3c04, 1345 .enable_mask = BIT(0), 1346 .hw.init = &(struct clk_init_data){ 1347 .name = "smmu_vfe_ahb_clk", 1348 .parent_names = (const char *[]){ "ahb_clk_src" }, 1349 .num_parents = 1, 1350 .flags = CLK_SET_RATE_PARENT, 1351 .ops = &clk_branch2_ops, 1352 }, 1353 }, 1354 }; 1355 1356 static struct clk_branch smmu_vfe_axi_clk = { 1357 .halt_reg = 0x3c08, 1358 .clkr = { 1359 .enable_reg = 0x3c08, 1360 .enable_mask = BIT(0), 1361 .hw.init = &(struct clk_init_data){ 1362 .name = "smmu_vfe_axi_clk", 1363 .parent_names = (const char *[]){ "axi_clk_src" }, 1364 .num_parents = 1, 1365 .flags = CLK_SET_RATE_PARENT, 1366 .ops = &clk_branch2_ops, 1367 }, 1368 }, 1369 }; 1370 1371 static struct clk_branch smmu_cpp_ahb_clk = { 1372 .halt_reg = 0x3c14, 1373 .clkr = { 1374 .enable_reg = 0x3c14, 1375 .enable_mask = BIT(0), 1376 .hw.init = &(struct clk_init_data){ 1377 .name = "smmu_cpp_ahb_clk", 1378 .parent_names = (const char *[]){ "ahb_clk_src" }, 1379 .num_parents = 1, 1380 .flags = CLK_SET_RATE_PARENT, 1381 .ops = &clk_branch2_ops, 1382 }, 1383 }, 1384 }; 1385 1386 static struct clk_branch smmu_cpp_axi_clk = { 1387 .halt_reg = 0x3c18, 1388 .clkr = { 1389 .enable_reg = 0x3c18, 1390 .enable_mask = BIT(0), 1391 .hw.init = &(struct clk_init_data){ 1392 .name = "smmu_cpp_axi_clk", 1393 .parent_names = (const char *[]){ "axi_clk_src" }, 1394 .num_parents = 1, 1395 .flags = CLK_SET_RATE_PARENT, 1396 .ops = &clk_branch2_ops, 1397 }, 1398 }, 1399 }; 1400 1401 static struct clk_branch smmu_jpeg_ahb_clk = { 1402 .halt_reg = 0x3c24, 1403 .clkr = { 1404 .enable_reg = 0x3c24, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(struct clk_init_data){ 1407 .name = "smmu_jpeg_ahb_clk", 1408 .parent_names = (const char *[]){ "ahb_clk_src" }, 1409 .num_parents = 1, 1410 .flags = CLK_SET_RATE_PARENT, 1411 .ops = &clk_branch2_ops, 1412 }, 1413 }, 1414 }; 1415 1416 static struct clk_branch smmu_jpeg_axi_clk = { 1417 .halt_reg = 0x3c28, 1418 .clkr = { 1419 .enable_reg = 0x3c28, 1420 .enable_mask = BIT(0), 1421 .hw.init = &(struct clk_init_data){ 1422 .name = "smmu_jpeg_axi_clk", 1423 .parent_names = (const char *[]){ "axi_clk_src" }, 1424 .num_parents = 1, 1425 .flags = CLK_SET_RATE_PARENT, 1426 .ops = &clk_branch2_ops, 1427 }, 1428 }, 1429 }; 1430 1431 static struct clk_branch mmagic_mdss_axi_clk = { 1432 .halt_reg = 0x2474, 1433 .clkr = { 1434 .enable_reg = 0x2474, 1435 .enable_mask = BIT(0), 1436 .hw.init = &(struct clk_init_data){ 1437 .name = "mmagic_mdss_axi_clk", 1438 .parent_names = (const char *[]){ "axi_clk_src" }, 1439 .num_parents = 1, 1440 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1441 .ops = &clk_branch2_ops, 1442 }, 1443 }, 1444 }; 1445 1446 static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = { 1447 .halt_reg = 0x2478, 1448 .clkr = { 1449 .enable_reg = 0x2478, 1450 .enable_mask = BIT(0), 1451 .hw.init = &(struct clk_init_data){ 1452 .name = "mmagic_mdss_noc_cfg_ahb_clk", 1453 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1454 .num_parents = 1, 1455 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1456 .ops = &clk_branch2_ops, 1457 }, 1458 }, 1459 }; 1460 1461 static struct clk_branch smmu_rot_ahb_clk = { 1462 .halt_reg = 0x2444, 1463 .clkr = { 1464 .enable_reg = 0x2444, 1465 .enable_mask = BIT(0), 1466 .hw.init = &(struct clk_init_data){ 1467 .name = "smmu_rot_ahb_clk", 1468 .parent_names = (const char *[]){ "ahb_clk_src" }, 1469 .num_parents = 1, 1470 .flags = CLK_SET_RATE_PARENT, 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474 }; 1475 1476 static struct clk_branch smmu_rot_axi_clk = { 1477 .halt_reg = 0x2448, 1478 .clkr = { 1479 .enable_reg = 0x2448, 1480 .enable_mask = BIT(0), 1481 .hw.init = &(struct clk_init_data){ 1482 .name = "smmu_rot_axi_clk", 1483 .parent_names = (const char *[]){ "axi_clk_src" }, 1484 .num_parents = 1, 1485 .flags = CLK_SET_RATE_PARENT, 1486 .ops = &clk_branch2_ops, 1487 }, 1488 }, 1489 }; 1490 1491 static struct clk_branch smmu_mdp_ahb_clk = { 1492 .halt_reg = 0x2454, 1493 .clkr = { 1494 .enable_reg = 0x2454, 1495 .enable_mask = BIT(0), 1496 .hw.init = &(struct clk_init_data){ 1497 .name = "smmu_mdp_ahb_clk", 1498 .parent_names = (const char *[]){ "ahb_clk_src" }, 1499 .num_parents = 1, 1500 .flags = CLK_SET_RATE_PARENT, 1501 .ops = &clk_branch2_ops, 1502 }, 1503 }, 1504 }; 1505 1506 static struct clk_branch smmu_mdp_axi_clk = { 1507 .halt_reg = 0x2458, 1508 .clkr = { 1509 .enable_reg = 0x2458, 1510 .enable_mask = BIT(0), 1511 .hw.init = &(struct clk_init_data){ 1512 .name = "smmu_mdp_axi_clk", 1513 .parent_names = (const char *[]){ "axi_clk_src" }, 1514 .num_parents = 1, 1515 .flags = CLK_SET_RATE_PARENT, 1516 .ops = &clk_branch2_ops, 1517 }, 1518 }, 1519 }; 1520 1521 static struct clk_branch mmagic_video_axi_clk = { 1522 .halt_reg = 0x1194, 1523 .clkr = { 1524 .enable_reg = 0x1194, 1525 .enable_mask = BIT(0), 1526 .hw.init = &(struct clk_init_data){ 1527 .name = "mmagic_video_axi_clk", 1528 .parent_names = (const char *[]){ "axi_clk_src" }, 1529 .num_parents = 1, 1530 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1531 .ops = &clk_branch2_ops, 1532 }, 1533 }, 1534 }; 1535 1536 static struct clk_branch mmagic_video_noc_cfg_ahb_clk = { 1537 .halt_reg = 0x1198, 1538 .clkr = { 1539 .enable_reg = 0x1198, 1540 .enable_mask = BIT(0), 1541 .hw.init = &(struct clk_init_data){ 1542 .name = "mmagic_video_noc_cfg_ahb_clk", 1543 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1544 .num_parents = 1, 1545 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1546 .ops = &clk_branch2_ops, 1547 }, 1548 }, 1549 }; 1550 1551 static struct clk_branch smmu_video_ahb_clk = { 1552 .halt_reg = 0x1174, 1553 .clkr = { 1554 .enable_reg = 0x1174, 1555 .enable_mask = BIT(0), 1556 .hw.init = &(struct clk_init_data){ 1557 .name = "smmu_video_ahb_clk", 1558 .parent_names = (const char *[]){ "ahb_clk_src" }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_branch smmu_video_axi_clk = { 1567 .halt_reg = 0x1178, 1568 .clkr = { 1569 .enable_reg = 0x1178, 1570 .enable_mask = BIT(0), 1571 .hw.init = &(struct clk_init_data){ 1572 .name = "smmu_video_axi_clk", 1573 .parent_names = (const char *[]){ "axi_clk_src" }, 1574 .num_parents = 1, 1575 .flags = CLK_SET_RATE_PARENT, 1576 .ops = &clk_branch2_ops, 1577 }, 1578 }, 1579 }; 1580 1581 static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { 1582 .halt_reg = 0x5298, 1583 .clkr = { 1584 .enable_reg = 0x5298, 1585 .enable_mask = BIT(0), 1586 .hw.init = &(struct clk_init_data){ 1587 .name = "mmagic_bimc_noc_cfg_ahb_clk", 1588 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1589 .num_parents = 1, 1590 .flags = CLK_SET_RATE_PARENT, 1591 .ops = &clk_branch2_ops, 1592 }, 1593 }, 1594 }; 1595 1596 static struct clk_branch gpu_gx_gfx3d_clk = { 1597 .halt_reg = 0x4028, 1598 .clkr = { 1599 .enable_reg = 0x4028, 1600 .enable_mask = BIT(0), 1601 .hw.init = &(struct clk_init_data){ 1602 .name = "gpu_gx_gfx3d_clk", 1603 .parent_names = (const char *[]){ "gfx3d_clk_src" }, 1604 .num_parents = 1, 1605 .flags = CLK_SET_RATE_PARENT, 1606 .ops = &clk_branch2_ops, 1607 }, 1608 }, 1609 }; 1610 1611 static struct clk_branch gpu_gx_rbbmtimer_clk = { 1612 .halt_reg = 0x40b0, 1613 .clkr = { 1614 .enable_reg = 0x40b0, 1615 .enable_mask = BIT(0), 1616 .hw.init = &(struct clk_init_data){ 1617 .name = "gpu_gx_rbbmtimer_clk", 1618 .parent_names = (const char *[]){ "rbbmtimer_clk_src" }, 1619 .num_parents = 1, 1620 .flags = CLK_SET_RATE_PARENT, 1621 .ops = &clk_branch2_ops, 1622 }, 1623 }, 1624 }; 1625 1626 static struct clk_branch gpu_ahb_clk = { 1627 .halt_reg = 0x403c, 1628 .clkr = { 1629 .enable_reg = 0x403c, 1630 .enable_mask = BIT(0), 1631 .hw.init = &(struct clk_init_data){ 1632 .name = "gpu_ahb_clk", 1633 .parent_names = (const char *[]){ "ahb_clk_src" }, 1634 .num_parents = 1, 1635 .flags = CLK_SET_RATE_PARENT, 1636 .ops = &clk_branch2_ops, 1637 }, 1638 }, 1639 }; 1640 1641 static struct clk_branch gpu_aon_isense_clk = { 1642 .halt_reg = 0x4044, 1643 .clkr = { 1644 .enable_reg = 0x4044, 1645 .enable_mask = BIT(0), 1646 .hw.init = &(struct clk_init_data){ 1647 .name = "gpu_aon_isense_clk", 1648 .parent_names = (const char *[]){ "isense_clk_src" }, 1649 .num_parents = 1, 1650 .flags = CLK_SET_RATE_PARENT, 1651 .ops = &clk_branch2_ops, 1652 }, 1653 }, 1654 }; 1655 1656 static struct clk_branch vmem_maxi_clk = { 1657 .halt_reg = 0x1204, 1658 .clkr = { 1659 .enable_reg = 0x1204, 1660 .enable_mask = BIT(0), 1661 .hw.init = &(struct clk_init_data){ 1662 .name = "vmem_maxi_clk", 1663 .parent_names = (const char *[]){ "maxi_clk_src" }, 1664 .num_parents = 1, 1665 .flags = CLK_SET_RATE_PARENT, 1666 .ops = &clk_branch2_ops, 1667 }, 1668 }, 1669 }; 1670 1671 static struct clk_branch vmem_ahb_clk = { 1672 .halt_reg = 0x1208, 1673 .clkr = { 1674 .enable_reg = 0x1208, 1675 .enable_mask = BIT(0), 1676 .hw.init = &(struct clk_init_data){ 1677 .name = "vmem_ahb_clk", 1678 .parent_names = (const char *[]){ "ahb_clk_src" }, 1679 .num_parents = 1, 1680 .flags = CLK_SET_RATE_PARENT, 1681 .ops = &clk_branch2_ops, 1682 }, 1683 }, 1684 }; 1685 1686 static struct clk_branch mmss_rbcpr_clk = { 1687 .halt_reg = 0x4084, 1688 .clkr = { 1689 .enable_reg = 0x4084, 1690 .enable_mask = BIT(0), 1691 .hw.init = &(struct clk_init_data){ 1692 .name = "mmss_rbcpr_clk", 1693 .parent_names = (const char *[]){ "rbcpr_clk_src" }, 1694 .num_parents = 1, 1695 .flags = CLK_SET_RATE_PARENT, 1696 .ops = &clk_branch2_ops, 1697 }, 1698 }, 1699 }; 1700 1701 static struct clk_branch mmss_rbcpr_ahb_clk = { 1702 .halt_reg = 0x4088, 1703 .clkr = { 1704 .enable_reg = 0x4088, 1705 .enable_mask = BIT(0), 1706 .hw.init = &(struct clk_init_data){ 1707 .name = "mmss_rbcpr_ahb_clk", 1708 .parent_names = (const char *[]){ "ahb_clk_src" }, 1709 .num_parents = 1, 1710 .flags = CLK_SET_RATE_PARENT, 1711 .ops = &clk_branch2_ops, 1712 }, 1713 }, 1714 }; 1715 1716 static struct clk_branch video_core_clk = { 1717 .halt_reg = 0x1028, 1718 .clkr = { 1719 .enable_reg = 0x1028, 1720 .enable_mask = BIT(0), 1721 .hw.init = &(struct clk_init_data){ 1722 .name = "video_core_clk", 1723 .parent_names = (const char *[]){ "video_core_clk_src" }, 1724 .num_parents = 1, 1725 .flags = CLK_SET_RATE_PARENT, 1726 .ops = &clk_branch2_ops, 1727 }, 1728 }, 1729 }; 1730 1731 static struct clk_branch video_axi_clk = { 1732 .halt_reg = 0x1034, 1733 .clkr = { 1734 .enable_reg = 0x1034, 1735 .enable_mask = BIT(0), 1736 .hw.init = &(struct clk_init_data){ 1737 .name = "video_axi_clk", 1738 .parent_names = (const char *[]){ "axi_clk_src" }, 1739 .num_parents = 1, 1740 .flags = CLK_SET_RATE_PARENT, 1741 .ops = &clk_branch2_ops, 1742 }, 1743 }, 1744 }; 1745 1746 static struct clk_branch video_maxi_clk = { 1747 .halt_reg = 0x1038, 1748 .clkr = { 1749 .enable_reg = 0x1038, 1750 .enable_mask = BIT(0), 1751 .hw.init = &(struct clk_init_data){ 1752 .name = "video_maxi_clk", 1753 .parent_names = (const char *[]){ "maxi_clk_src" }, 1754 .num_parents = 1, 1755 .flags = CLK_SET_RATE_PARENT, 1756 .ops = &clk_branch2_ops, 1757 }, 1758 }, 1759 }; 1760 1761 static struct clk_branch video_ahb_clk = { 1762 .halt_reg = 0x1030, 1763 .clkr = { 1764 .enable_reg = 0x1030, 1765 .enable_mask = BIT(0), 1766 .hw.init = &(struct clk_init_data){ 1767 .name = "video_ahb_clk", 1768 .parent_names = (const char *[]){ "ahb_clk_src" }, 1769 .num_parents = 1, 1770 .flags = CLK_SET_RATE_PARENT, 1771 .ops = &clk_branch2_ops, 1772 }, 1773 }, 1774 }; 1775 1776 static struct clk_branch video_subcore0_clk = { 1777 .halt_reg = 0x1048, 1778 .clkr = { 1779 .enable_reg = 0x1048, 1780 .enable_mask = BIT(0), 1781 .hw.init = &(struct clk_init_data){ 1782 .name = "video_subcore0_clk", 1783 .parent_names = (const char *[]){ "video_subcore0_clk_src" }, 1784 .num_parents = 1, 1785 .flags = CLK_SET_RATE_PARENT, 1786 .ops = &clk_branch2_ops, 1787 }, 1788 }, 1789 }; 1790 1791 static struct clk_branch video_subcore1_clk = { 1792 .halt_reg = 0x104c, 1793 .clkr = { 1794 .enable_reg = 0x104c, 1795 .enable_mask = BIT(0), 1796 .hw.init = &(struct clk_init_data){ 1797 .name = "video_subcore1_clk", 1798 .parent_names = (const char *[]){ "video_subcore1_clk_src" }, 1799 .num_parents = 1, 1800 .flags = CLK_SET_RATE_PARENT, 1801 .ops = &clk_branch2_ops, 1802 }, 1803 }, 1804 }; 1805 1806 static struct clk_branch mdss_ahb_clk = { 1807 .halt_reg = 0x2308, 1808 .clkr = { 1809 .enable_reg = 0x2308, 1810 .enable_mask = BIT(0), 1811 .hw.init = &(struct clk_init_data){ 1812 .name = "mdss_ahb_clk", 1813 .parent_names = (const char *[]){ "ahb_clk_src" }, 1814 .num_parents = 1, 1815 .flags = CLK_SET_RATE_PARENT, 1816 .ops = &clk_branch2_ops, 1817 }, 1818 }, 1819 }; 1820 1821 static struct clk_branch mdss_hdmi_ahb_clk = { 1822 .halt_reg = 0x230c, 1823 .clkr = { 1824 .enable_reg = 0x230c, 1825 .enable_mask = BIT(0), 1826 .hw.init = &(struct clk_init_data){ 1827 .name = "mdss_hdmi_ahb_clk", 1828 .parent_names = (const char *[]){ "ahb_clk_src" }, 1829 .num_parents = 1, 1830 .flags = CLK_SET_RATE_PARENT, 1831 .ops = &clk_branch2_ops, 1832 }, 1833 }, 1834 }; 1835 1836 static struct clk_branch mdss_axi_clk = { 1837 .halt_reg = 0x2310, 1838 .clkr = { 1839 .enable_reg = 0x2310, 1840 .enable_mask = BIT(0), 1841 .hw.init = &(struct clk_init_data){ 1842 .name = "mdss_axi_clk", 1843 .parent_names = (const char *[]){ "axi_clk_src" }, 1844 .num_parents = 1, 1845 .flags = CLK_SET_RATE_PARENT, 1846 .ops = &clk_branch2_ops, 1847 }, 1848 }, 1849 }; 1850 1851 static struct clk_branch mdss_pclk0_clk = { 1852 .halt_reg = 0x2314, 1853 .clkr = { 1854 .enable_reg = 0x2314, 1855 .enable_mask = BIT(0), 1856 .hw.init = &(struct clk_init_data){ 1857 .name = "mdss_pclk0_clk", 1858 .parent_names = (const char *[]){ "pclk0_clk_src" }, 1859 .num_parents = 1, 1860 .flags = CLK_SET_RATE_PARENT, 1861 .ops = &clk_branch2_ops, 1862 }, 1863 }, 1864 }; 1865 1866 static struct clk_branch mdss_pclk1_clk = { 1867 .halt_reg = 0x2318, 1868 .clkr = { 1869 .enable_reg = 0x2318, 1870 .enable_mask = BIT(0), 1871 .hw.init = &(struct clk_init_data){ 1872 .name = "mdss_pclk1_clk", 1873 .parent_names = (const char *[]){ "pclk1_clk_src" }, 1874 .num_parents = 1, 1875 .flags = CLK_SET_RATE_PARENT, 1876 .ops = &clk_branch2_ops, 1877 }, 1878 }, 1879 }; 1880 1881 static struct clk_branch mdss_mdp_clk = { 1882 .halt_reg = 0x231c, 1883 .clkr = { 1884 .enable_reg = 0x231c, 1885 .enable_mask = BIT(0), 1886 .hw.init = &(struct clk_init_data){ 1887 .name = "mdss_mdp_clk", 1888 .parent_names = (const char *[]){ "mdp_clk_src" }, 1889 .num_parents = 1, 1890 .flags = CLK_SET_RATE_PARENT, 1891 .ops = &clk_branch2_ops, 1892 }, 1893 }, 1894 }; 1895 1896 static struct clk_branch mdss_extpclk_clk = { 1897 .halt_reg = 0x2324, 1898 .clkr = { 1899 .enable_reg = 0x2324, 1900 .enable_mask = BIT(0), 1901 .hw.init = &(struct clk_init_data){ 1902 .name = "mdss_extpclk_clk", 1903 .parent_names = (const char *[]){ "extpclk_clk_src" }, 1904 .num_parents = 1, 1905 .flags = CLK_SET_RATE_PARENT, 1906 .ops = &clk_branch2_ops, 1907 }, 1908 }, 1909 }; 1910 1911 static struct clk_branch mdss_vsync_clk = { 1912 .halt_reg = 0x2328, 1913 .clkr = { 1914 .enable_reg = 0x2328, 1915 .enable_mask = BIT(0), 1916 .hw.init = &(struct clk_init_data){ 1917 .name = "mdss_vsync_clk", 1918 .parent_names = (const char *[]){ "vsync_clk_src" }, 1919 .num_parents = 1, 1920 .flags = CLK_SET_RATE_PARENT, 1921 .ops = &clk_branch2_ops, 1922 }, 1923 }, 1924 }; 1925 1926 static struct clk_branch mdss_hdmi_clk = { 1927 .halt_reg = 0x2338, 1928 .clkr = { 1929 .enable_reg = 0x2338, 1930 .enable_mask = BIT(0), 1931 .hw.init = &(struct clk_init_data){ 1932 .name = "mdss_hdmi_clk", 1933 .parent_names = (const char *[]){ "hdmi_clk_src" }, 1934 .num_parents = 1, 1935 .flags = CLK_SET_RATE_PARENT, 1936 .ops = &clk_branch2_ops, 1937 }, 1938 }, 1939 }; 1940 1941 static struct clk_branch mdss_byte0_clk = { 1942 .halt_reg = 0x233c, 1943 .clkr = { 1944 .enable_reg = 0x233c, 1945 .enable_mask = BIT(0), 1946 .hw.init = &(struct clk_init_data){ 1947 .name = "mdss_byte0_clk", 1948 .parent_names = (const char *[]){ "byte0_clk_src" }, 1949 .num_parents = 1, 1950 .flags = CLK_SET_RATE_PARENT, 1951 .ops = &clk_branch2_ops, 1952 }, 1953 }, 1954 }; 1955 1956 static struct clk_branch mdss_byte1_clk = { 1957 .halt_reg = 0x2340, 1958 .clkr = { 1959 .enable_reg = 0x2340, 1960 .enable_mask = BIT(0), 1961 .hw.init = &(struct clk_init_data){ 1962 .name = "mdss_byte1_clk", 1963 .parent_names = (const char *[]){ "byte1_clk_src" }, 1964 .num_parents = 1, 1965 .flags = CLK_SET_RATE_PARENT, 1966 .ops = &clk_branch2_ops, 1967 }, 1968 }, 1969 }; 1970 1971 static struct clk_branch mdss_esc0_clk = { 1972 .halt_reg = 0x2344, 1973 .clkr = { 1974 .enable_reg = 0x2344, 1975 .enable_mask = BIT(0), 1976 .hw.init = &(struct clk_init_data){ 1977 .name = "mdss_esc0_clk", 1978 .parent_names = (const char *[]){ "esc0_clk_src" }, 1979 .num_parents = 1, 1980 .flags = CLK_SET_RATE_PARENT, 1981 .ops = &clk_branch2_ops, 1982 }, 1983 }, 1984 }; 1985 1986 static struct clk_branch mdss_esc1_clk = { 1987 .halt_reg = 0x2348, 1988 .clkr = { 1989 .enable_reg = 0x2348, 1990 .enable_mask = BIT(0), 1991 .hw.init = &(struct clk_init_data){ 1992 .name = "mdss_esc1_clk", 1993 .parent_names = (const char *[]){ "esc1_clk_src" }, 1994 .num_parents = 1, 1995 .flags = CLK_SET_RATE_PARENT, 1996 .ops = &clk_branch2_ops, 1997 }, 1998 }, 1999 }; 2000 2001 static struct clk_branch camss_top_ahb_clk = { 2002 .halt_reg = 0x3484, 2003 .clkr = { 2004 .enable_reg = 0x3484, 2005 .enable_mask = BIT(0), 2006 .hw.init = &(struct clk_init_data){ 2007 .name = "camss_top_ahb_clk", 2008 .parent_names = (const char *[]){ "ahb_clk_src" }, 2009 .num_parents = 1, 2010 .flags = CLK_SET_RATE_PARENT, 2011 .ops = &clk_branch2_ops, 2012 }, 2013 }, 2014 }; 2015 2016 static struct clk_branch camss_ahb_clk = { 2017 .halt_reg = 0x348c, 2018 .clkr = { 2019 .enable_reg = 0x348c, 2020 .enable_mask = BIT(0), 2021 .hw.init = &(struct clk_init_data){ 2022 .name = "camss_ahb_clk", 2023 .parent_names = (const char *[]){ "ahb_clk_src" }, 2024 .num_parents = 1, 2025 .flags = CLK_SET_RATE_PARENT, 2026 .ops = &clk_branch2_ops, 2027 }, 2028 }, 2029 }; 2030 2031 static struct clk_branch camss_micro_ahb_clk = { 2032 .halt_reg = 0x3494, 2033 .clkr = { 2034 .enable_reg = 0x3494, 2035 .enable_mask = BIT(0), 2036 .hw.init = &(struct clk_init_data){ 2037 .name = "camss_micro_ahb_clk", 2038 .parent_names = (const char *[]){ "ahb_clk_src" }, 2039 .num_parents = 1, 2040 .flags = CLK_SET_RATE_PARENT, 2041 .ops = &clk_branch2_ops, 2042 }, 2043 }, 2044 }; 2045 2046 static struct clk_branch camss_gp0_clk = { 2047 .halt_reg = 0x3444, 2048 .clkr = { 2049 .enable_reg = 0x3444, 2050 .enable_mask = BIT(0), 2051 .hw.init = &(struct clk_init_data){ 2052 .name = "camss_gp0_clk", 2053 .parent_names = (const char *[]){ "camss_gp0_clk_src" }, 2054 .num_parents = 1, 2055 .flags = CLK_SET_RATE_PARENT, 2056 .ops = &clk_branch2_ops, 2057 }, 2058 }, 2059 }; 2060 2061 static struct clk_branch camss_gp1_clk = { 2062 .halt_reg = 0x3474, 2063 .clkr = { 2064 .enable_reg = 0x3474, 2065 .enable_mask = BIT(0), 2066 .hw.init = &(struct clk_init_data){ 2067 .name = "camss_gp1_clk", 2068 .parent_names = (const char *[]){ "camss_gp1_clk_src" }, 2069 .num_parents = 1, 2070 .flags = CLK_SET_RATE_PARENT, 2071 .ops = &clk_branch2_ops, 2072 }, 2073 }, 2074 }; 2075 2076 static struct clk_branch camss_mclk0_clk = { 2077 .halt_reg = 0x3384, 2078 .clkr = { 2079 .enable_reg = 0x3384, 2080 .enable_mask = BIT(0), 2081 .hw.init = &(struct clk_init_data){ 2082 .name = "camss_mclk0_clk", 2083 .parent_names = (const char *[]){ "mclk0_clk_src" }, 2084 .num_parents = 1, 2085 .flags = CLK_SET_RATE_PARENT, 2086 .ops = &clk_branch2_ops, 2087 }, 2088 }, 2089 }; 2090 2091 static struct clk_branch camss_mclk1_clk = { 2092 .halt_reg = 0x33b4, 2093 .clkr = { 2094 .enable_reg = 0x33b4, 2095 .enable_mask = BIT(0), 2096 .hw.init = &(struct clk_init_data){ 2097 .name = "camss_mclk1_clk", 2098 .parent_names = (const char *[]){ "mclk1_clk_src" }, 2099 .num_parents = 1, 2100 .flags = CLK_SET_RATE_PARENT, 2101 .ops = &clk_branch2_ops, 2102 }, 2103 }, 2104 }; 2105 2106 static struct clk_branch camss_mclk2_clk = { 2107 .halt_reg = 0x33e4, 2108 .clkr = { 2109 .enable_reg = 0x33e4, 2110 .enable_mask = BIT(0), 2111 .hw.init = &(struct clk_init_data){ 2112 .name = "camss_mclk2_clk", 2113 .parent_names = (const char *[]){ "mclk2_clk_src" }, 2114 .num_parents = 1, 2115 .flags = CLK_SET_RATE_PARENT, 2116 .ops = &clk_branch2_ops, 2117 }, 2118 }, 2119 }; 2120 2121 static struct clk_branch camss_mclk3_clk = { 2122 .halt_reg = 0x3414, 2123 .clkr = { 2124 .enable_reg = 0x3414, 2125 .enable_mask = BIT(0), 2126 .hw.init = &(struct clk_init_data){ 2127 .name = "camss_mclk3_clk", 2128 .parent_names = (const char *[]){ "mclk3_clk_src" }, 2129 .num_parents = 1, 2130 .flags = CLK_SET_RATE_PARENT, 2131 .ops = &clk_branch2_ops, 2132 }, 2133 }, 2134 }; 2135 2136 static struct clk_branch camss_cci_clk = { 2137 .halt_reg = 0x3344, 2138 .clkr = { 2139 .enable_reg = 0x3344, 2140 .enable_mask = BIT(0), 2141 .hw.init = &(struct clk_init_data){ 2142 .name = "camss_cci_clk", 2143 .parent_names = (const char *[]){ "cci_clk_src" }, 2144 .num_parents = 1, 2145 .flags = CLK_SET_RATE_PARENT, 2146 .ops = &clk_branch2_ops, 2147 }, 2148 }, 2149 }; 2150 2151 static struct clk_branch camss_cci_ahb_clk = { 2152 .halt_reg = 0x3348, 2153 .clkr = { 2154 .enable_reg = 0x3348, 2155 .enable_mask = BIT(0), 2156 .hw.init = &(struct clk_init_data){ 2157 .name = "camss_cci_ahb_clk", 2158 .parent_names = (const char *[]){ "ahb_clk_src" }, 2159 .num_parents = 1, 2160 .flags = CLK_SET_RATE_PARENT, 2161 .ops = &clk_branch2_ops, 2162 }, 2163 }, 2164 }; 2165 2166 static struct clk_branch camss_csi0phytimer_clk = { 2167 .halt_reg = 0x3024, 2168 .clkr = { 2169 .enable_reg = 0x3024, 2170 .enable_mask = BIT(0), 2171 .hw.init = &(struct clk_init_data){ 2172 .name = "camss_csi0phytimer_clk", 2173 .parent_names = (const char *[]){ "csi0phytimer_clk_src" }, 2174 .num_parents = 1, 2175 .flags = CLK_SET_RATE_PARENT, 2176 .ops = &clk_branch2_ops, 2177 }, 2178 }, 2179 }; 2180 2181 static struct clk_branch camss_csi1phytimer_clk = { 2182 .halt_reg = 0x3054, 2183 .clkr = { 2184 .enable_reg = 0x3054, 2185 .enable_mask = BIT(0), 2186 .hw.init = &(struct clk_init_data){ 2187 .name = "camss_csi1phytimer_clk", 2188 .parent_names = (const char *[]){ "csi1phytimer_clk_src" }, 2189 .num_parents = 1, 2190 .flags = CLK_SET_RATE_PARENT, 2191 .ops = &clk_branch2_ops, 2192 }, 2193 }, 2194 }; 2195 2196 static struct clk_branch camss_csi2phytimer_clk = { 2197 .halt_reg = 0x3084, 2198 .clkr = { 2199 .enable_reg = 0x3084, 2200 .enable_mask = BIT(0), 2201 .hw.init = &(struct clk_init_data){ 2202 .name = "camss_csi2phytimer_clk", 2203 .parent_names = (const char *[]){ "csi2phytimer_clk_src" }, 2204 .num_parents = 1, 2205 .flags = CLK_SET_RATE_PARENT, 2206 .ops = &clk_branch2_ops, 2207 }, 2208 }, 2209 }; 2210 2211 static struct clk_branch camss_csiphy0_3p_clk = { 2212 .halt_reg = 0x3234, 2213 .clkr = { 2214 .enable_reg = 0x3234, 2215 .enable_mask = BIT(0), 2216 .hw.init = &(struct clk_init_data){ 2217 .name = "camss_csiphy0_3p_clk", 2218 .parent_names = (const char *[]){ "csiphy0_3p_clk_src" }, 2219 .num_parents = 1, 2220 .flags = CLK_SET_RATE_PARENT, 2221 .ops = &clk_branch2_ops, 2222 }, 2223 }, 2224 }; 2225 2226 static struct clk_branch camss_csiphy1_3p_clk = { 2227 .halt_reg = 0x3254, 2228 .clkr = { 2229 .enable_reg = 0x3254, 2230 .enable_mask = BIT(0), 2231 .hw.init = &(struct clk_init_data){ 2232 .name = "camss_csiphy1_3p_clk", 2233 .parent_names = (const char *[]){ "csiphy1_3p_clk_src" }, 2234 .num_parents = 1, 2235 .flags = CLK_SET_RATE_PARENT, 2236 .ops = &clk_branch2_ops, 2237 }, 2238 }, 2239 }; 2240 2241 static struct clk_branch camss_csiphy2_3p_clk = { 2242 .halt_reg = 0x3274, 2243 .clkr = { 2244 .enable_reg = 0x3274, 2245 .enable_mask = BIT(0), 2246 .hw.init = &(struct clk_init_data){ 2247 .name = "camss_csiphy2_3p_clk", 2248 .parent_names = (const char *[]){ "csiphy2_3p_clk_src" }, 2249 .num_parents = 1, 2250 .flags = CLK_SET_RATE_PARENT, 2251 .ops = &clk_branch2_ops, 2252 }, 2253 }, 2254 }; 2255 2256 static struct clk_branch camss_jpeg0_clk = { 2257 .halt_reg = 0x35a8, 2258 .clkr = { 2259 .enable_reg = 0x35a8, 2260 .enable_mask = BIT(0), 2261 .hw.init = &(struct clk_init_data){ 2262 .name = "camss_jpeg0_clk", 2263 .parent_names = (const char *[]){ "jpeg0_clk_src" }, 2264 .num_parents = 1, 2265 .flags = CLK_SET_RATE_PARENT, 2266 .ops = &clk_branch2_ops, 2267 }, 2268 }, 2269 }; 2270 2271 static struct clk_branch camss_jpeg2_clk = { 2272 .halt_reg = 0x35b0, 2273 .clkr = { 2274 .enable_reg = 0x35b0, 2275 .enable_mask = BIT(0), 2276 .hw.init = &(struct clk_init_data){ 2277 .name = "camss_jpeg2_clk", 2278 .parent_names = (const char *[]){ "jpeg2_clk_src" }, 2279 .num_parents = 1, 2280 .flags = CLK_SET_RATE_PARENT, 2281 .ops = &clk_branch2_ops, 2282 }, 2283 }, 2284 }; 2285 2286 static struct clk_branch camss_jpeg_dma_clk = { 2287 .halt_reg = 0x35c0, 2288 .clkr = { 2289 .enable_reg = 0x35c0, 2290 .enable_mask = BIT(0), 2291 .hw.init = &(struct clk_init_data){ 2292 .name = "camss_jpeg_dma_clk", 2293 .parent_names = (const char *[]){ "jpeg_dma_clk_src" }, 2294 .num_parents = 1, 2295 .flags = CLK_SET_RATE_PARENT, 2296 .ops = &clk_branch2_ops, 2297 }, 2298 }, 2299 }; 2300 2301 static struct clk_branch camss_jpeg_ahb_clk = { 2302 .halt_reg = 0x35b4, 2303 .clkr = { 2304 .enable_reg = 0x35b4, 2305 .enable_mask = BIT(0), 2306 .hw.init = &(struct clk_init_data){ 2307 .name = "camss_jpeg_ahb_clk", 2308 .parent_names = (const char *[]){ "ahb_clk_src" }, 2309 .num_parents = 1, 2310 .flags = CLK_SET_RATE_PARENT, 2311 .ops = &clk_branch2_ops, 2312 }, 2313 }, 2314 }; 2315 2316 static struct clk_branch camss_jpeg_axi_clk = { 2317 .halt_reg = 0x35b8, 2318 .clkr = { 2319 .enable_reg = 0x35b8, 2320 .enable_mask = BIT(0), 2321 .hw.init = &(struct clk_init_data){ 2322 .name = "camss_jpeg_axi_clk", 2323 .parent_names = (const char *[]){ "axi_clk_src" }, 2324 .num_parents = 1, 2325 .flags = CLK_SET_RATE_PARENT, 2326 .ops = &clk_branch2_ops, 2327 }, 2328 }, 2329 }; 2330 2331 static struct clk_branch camss_vfe_ahb_clk = { 2332 .halt_reg = 0x36b8, 2333 .clkr = { 2334 .enable_reg = 0x36b8, 2335 .enable_mask = BIT(0), 2336 .hw.init = &(struct clk_init_data){ 2337 .name = "camss_vfe_ahb_clk", 2338 .parent_names = (const char *[]){ "ahb_clk_src" }, 2339 .num_parents = 1, 2340 .flags = CLK_SET_RATE_PARENT, 2341 .ops = &clk_branch2_ops, 2342 }, 2343 }, 2344 }; 2345 2346 static struct clk_branch camss_vfe_axi_clk = { 2347 .halt_reg = 0x36bc, 2348 .clkr = { 2349 .enable_reg = 0x36bc, 2350 .enable_mask = BIT(0), 2351 .hw.init = &(struct clk_init_data){ 2352 .name = "camss_vfe_axi_clk", 2353 .parent_names = (const char *[]){ "axi_clk_src" }, 2354 .num_parents = 1, 2355 .flags = CLK_SET_RATE_PARENT, 2356 .ops = &clk_branch2_ops, 2357 }, 2358 }, 2359 }; 2360 2361 static struct clk_branch camss_vfe0_clk = { 2362 .halt_reg = 0x36a8, 2363 .clkr = { 2364 .enable_reg = 0x36a8, 2365 .enable_mask = BIT(0), 2366 .hw.init = &(struct clk_init_data){ 2367 .name = "camss_vfe0_clk", 2368 .parent_names = (const char *[]){ "vfe0_clk_src" }, 2369 .num_parents = 1, 2370 .flags = CLK_SET_RATE_PARENT, 2371 .ops = &clk_branch2_ops, 2372 }, 2373 }, 2374 }; 2375 2376 static struct clk_branch camss_vfe0_stream_clk = { 2377 .halt_reg = 0x3720, 2378 .clkr = { 2379 .enable_reg = 0x3720, 2380 .enable_mask = BIT(0), 2381 .hw.init = &(struct clk_init_data){ 2382 .name = "camss_vfe0_stream_clk", 2383 .parent_names = (const char *[]){ "vfe0_clk_src" }, 2384 .num_parents = 1, 2385 .flags = CLK_SET_RATE_PARENT, 2386 .ops = &clk_branch2_ops, 2387 }, 2388 }, 2389 }; 2390 2391 static struct clk_branch camss_vfe0_ahb_clk = { 2392 .halt_reg = 0x3668, 2393 .clkr = { 2394 .enable_reg = 0x3668, 2395 .enable_mask = BIT(0), 2396 .hw.init = &(struct clk_init_data){ 2397 .name = "camss_vfe0_ahb_clk", 2398 .parent_names = (const char *[]){ "ahb_clk_src" }, 2399 .num_parents = 1, 2400 .flags = CLK_SET_RATE_PARENT, 2401 .ops = &clk_branch2_ops, 2402 }, 2403 }, 2404 }; 2405 2406 static struct clk_branch camss_vfe1_clk = { 2407 .halt_reg = 0x36ac, 2408 .clkr = { 2409 .enable_reg = 0x36ac, 2410 .enable_mask = BIT(0), 2411 .hw.init = &(struct clk_init_data){ 2412 .name = "camss_vfe1_clk", 2413 .parent_names = (const char *[]){ "vfe1_clk_src" }, 2414 .num_parents = 1, 2415 .flags = CLK_SET_RATE_PARENT, 2416 .ops = &clk_branch2_ops, 2417 }, 2418 }, 2419 }; 2420 2421 static struct clk_branch camss_vfe1_stream_clk = { 2422 .halt_reg = 0x3724, 2423 .clkr = { 2424 .enable_reg = 0x3724, 2425 .enable_mask = BIT(0), 2426 .hw.init = &(struct clk_init_data){ 2427 .name = "camss_vfe1_stream_clk", 2428 .parent_names = (const char *[]){ "vfe1_clk_src" }, 2429 .num_parents = 1, 2430 .flags = CLK_SET_RATE_PARENT, 2431 .ops = &clk_branch2_ops, 2432 }, 2433 }, 2434 }; 2435 2436 static struct clk_branch camss_vfe1_ahb_clk = { 2437 .halt_reg = 0x3678, 2438 .clkr = { 2439 .enable_reg = 0x3678, 2440 .enable_mask = BIT(0), 2441 .hw.init = &(struct clk_init_data){ 2442 .name = "camss_vfe1_ahb_clk", 2443 .parent_names = (const char *[]){ "ahb_clk_src" }, 2444 .num_parents = 1, 2445 .flags = CLK_SET_RATE_PARENT, 2446 .ops = &clk_branch2_ops, 2447 }, 2448 }, 2449 }; 2450 2451 static struct clk_branch camss_csi_vfe0_clk = { 2452 .halt_reg = 0x3704, 2453 .clkr = { 2454 .enable_reg = 0x3704, 2455 .enable_mask = BIT(0), 2456 .hw.init = &(struct clk_init_data){ 2457 .name = "camss_csi_vfe0_clk", 2458 .parent_names = (const char *[]){ "vfe0_clk_src" }, 2459 .num_parents = 1, 2460 .flags = CLK_SET_RATE_PARENT, 2461 .ops = &clk_branch2_ops, 2462 }, 2463 }, 2464 }; 2465 2466 static struct clk_branch camss_csi_vfe1_clk = { 2467 .halt_reg = 0x3714, 2468 .clkr = { 2469 .enable_reg = 0x3714, 2470 .enable_mask = BIT(0), 2471 .hw.init = &(struct clk_init_data){ 2472 .name = "camss_csi_vfe1_clk", 2473 .parent_names = (const char *[]){ "vfe1_clk_src" }, 2474 .num_parents = 1, 2475 .flags = CLK_SET_RATE_PARENT, 2476 .ops = &clk_branch2_ops, 2477 }, 2478 }, 2479 }; 2480 2481 static struct clk_branch camss_cpp_vbif_ahb_clk = { 2482 .halt_reg = 0x36c8, 2483 .clkr = { 2484 .enable_reg = 0x36c8, 2485 .enable_mask = BIT(0), 2486 .hw.init = &(struct clk_init_data){ 2487 .name = "camss_cpp_vbif_ahb_clk", 2488 .parent_names = (const char *[]){ "ahb_clk_src" }, 2489 .num_parents = 1, 2490 .flags = CLK_SET_RATE_PARENT, 2491 .ops = &clk_branch2_ops, 2492 }, 2493 }, 2494 }; 2495 2496 static struct clk_branch camss_cpp_axi_clk = { 2497 .halt_reg = 0x36c4, 2498 .clkr = { 2499 .enable_reg = 0x36c4, 2500 .enable_mask = BIT(0), 2501 .hw.init = &(struct clk_init_data){ 2502 .name = "camss_cpp_axi_clk", 2503 .parent_names = (const char *[]){ "axi_clk_src" }, 2504 .num_parents = 1, 2505 .flags = CLK_SET_RATE_PARENT, 2506 .ops = &clk_branch2_ops, 2507 }, 2508 }, 2509 }; 2510 2511 static struct clk_branch camss_cpp_clk = { 2512 .halt_reg = 0x36b0, 2513 .clkr = { 2514 .enable_reg = 0x36b0, 2515 .enable_mask = BIT(0), 2516 .hw.init = &(struct clk_init_data){ 2517 .name = "camss_cpp_clk", 2518 .parent_names = (const char *[]){ "cpp_clk_src" }, 2519 .num_parents = 1, 2520 .flags = CLK_SET_RATE_PARENT, 2521 .ops = &clk_branch2_ops, 2522 }, 2523 }, 2524 }; 2525 2526 static struct clk_branch camss_cpp_ahb_clk = { 2527 .halt_reg = 0x36b4, 2528 .clkr = { 2529 .enable_reg = 0x36b4, 2530 .enable_mask = BIT(0), 2531 .hw.init = &(struct clk_init_data){ 2532 .name = "camss_cpp_ahb_clk", 2533 .parent_names = (const char *[]){ "ahb_clk_src" }, 2534 .num_parents = 1, 2535 .flags = CLK_SET_RATE_PARENT, 2536 .ops = &clk_branch2_ops, 2537 }, 2538 }, 2539 }; 2540 2541 static struct clk_branch camss_csi0_clk = { 2542 .halt_reg = 0x30b4, 2543 .clkr = { 2544 .enable_reg = 0x30b4, 2545 .enable_mask = BIT(0), 2546 .hw.init = &(struct clk_init_data){ 2547 .name = "camss_csi0_clk", 2548 .parent_names = (const char *[]){ "csi0_clk_src" }, 2549 .num_parents = 1, 2550 .flags = CLK_SET_RATE_PARENT, 2551 .ops = &clk_branch2_ops, 2552 }, 2553 }, 2554 }; 2555 2556 static struct clk_branch camss_csi0_ahb_clk = { 2557 .halt_reg = 0x30bc, 2558 .clkr = { 2559 .enable_reg = 0x30bc, 2560 .enable_mask = BIT(0), 2561 .hw.init = &(struct clk_init_data){ 2562 .name = "camss_csi0_ahb_clk", 2563 .parent_names = (const char *[]){ "ahb_clk_src" }, 2564 .num_parents = 1, 2565 .flags = CLK_SET_RATE_PARENT, 2566 .ops = &clk_branch2_ops, 2567 }, 2568 }, 2569 }; 2570 2571 static struct clk_branch camss_csi0phy_clk = { 2572 .halt_reg = 0x30c4, 2573 .clkr = { 2574 .enable_reg = 0x30c4, 2575 .enable_mask = BIT(0), 2576 .hw.init = &(struct clk_init_data){ 2577 .name = "camss_csi0phy_clk", 2578 .parent_names = (const char *[]){ "csi0_clk_src" }, 2579 .num_parents = 1, 2580 .flags = CLK_SET_RATE_PARENT, 2581 .ops = &clk_branch2_ops, 2582 }, 2583 }, 2584 }; 2585 2586 static struct clk_branch camss_csi0rdi_clk = { 2587 .halt_reg = 0x30d4, 2588 .clkr = { 2589 .enable_reg = 0x30d4, 2590 .enable_mask = BIT(0), 2591 .hw.init = &(struct clk_init_data){ 2592 .name = "camss_csi0rdi_clk", 2593 .parent_names = (const char *[]){ "csi0_clk_src" }, 2594 .num_parents = 1, 2595 .flags = CLK_SET_RATE_PARENT, 2596 .ops = &clk_branch2_ops, 2597 }, 2598 }, 2599 }; 2600 2601 static struct clk_branch camss_csi0pix_clk = { 2602 .halt_reg = 0x30e4, 2603 .clkr = { 2604 .enable_reg = 0x30e4, 2605 .enable_mask = BIT(0), 2606 .hw.init = &(struct clk_init_data){ 2607 .name = "camss_csi0pix_clk", 2608 .parent_names = (const char *[]){ "csi0_clk_src" }, 2609 .num_parents = 1, 2610 .flags = CLK_SET_RATE_PARENT, 2611 .ops = &clk_branch2_ops, 2612 }, 2613 }, 2614 }; 2615 2616 static struct clk_branch camss_csi1_clk = { 2617 .halt_reg = 0x3124, 2618 .clkr = { 2619 .enable_reg = 0x3124, 2620 .enable_mask = BIT(0), 2621 .hw.init = &(struct clk_init_data){ 2622 .name = "camss_csi1_clk", 2623 .parent_names = (const char *[]){ "csi1_clk_src" }, 2624 .num_parents = 1, 2625 .flags = CLK_SET_RATE_PARENT, 2626 .ops = &clk_branch2_ops, 2627 }, 2628 }, 2629 }; 2630 2631 static struct clk_branch camss_csi1_ahb_clk = { 2632 .halt_reg = 0x3128, 2633 .clkr = { 2634 .enable_reg = 0x3128, 2635 .enable_mask = BIT(0), 2636 .hw.init = &(struct clk_init_data){ 2637 .name = "camss_csi1_ahb_clk", 2638 .parent_names = (const char *[]){ "ahb_clk_src" }, 2639 .num_parents = 1, 2640 .flags = CLK_SET_RATE_PARENT, 2641 .ops = &clk_branch2_ops, 2642 }, 2643 }, 2644 }; 2645 2646 static struct clk_branch camss_csi1phy_clk = { 2647 .halt_reg = 0x3134, 2648 .clkr = { 2649 .enable_reg = 0x3134, 2650 .enable_mask = BIT(0), 2651 .hw.init = &(struct clk_init_data){ 2652 .name = "camss_csi1phy_clk", 2653 .parent_names = (const char *[]){ "csi1_clk_src" }, 2654 .num_parents = 1, 2655 .flags = CLK_SET_RATE_PARENT, 2656 .ops = &clk_branch2_ops, 2657 }, 2658 }, 2659 }; 2660 2661 static struct clk_branch camss_csi1rdi_clk = { 2662 .halt_reg = 0x3144, 2663 .clkr = { 2664 .enable_reg = 0x3144, 2665 .enable_mask = BIT(0), 2666 .hw.init = &(struct clk_init_data){ 2667 .name = "camss_csi1rdi_clk", 2668 .parent_names = (const char *[]){ "csi1_clk_src" }, 2669 .num_parents = 1, 2670 .flags = CLK_SET_RATE_PARENT, 2671 .ops = &clk_branch2_ops, 2672 }, 2673 }, 2674 }; 2675 2676 static struct clk_branch camss_csi1pix_clk = { 2677 .halt_reg = 0x3154, 2678 .clkr = { 2679 .enable_reg = 0x3154, 2680 .enable_mask = BIT(0), 2681 .hw.init = &(struct clk_init_data){ 2682 .name = "camss_csi1pix_clk", 2683 .parent_names = (const char *[]){ "csi1_clk_src" }, 2684 .num_parents = 1, 2685 .flags = CLK_SET_RATE_PARENT, 2686 .ops = &clk_branch2_ops, 2687 }, 2688 }, 2689 }; 2690 2691 static struct clk_branch camss_csi2_clk = { 2692 .halt_reg = 0x3184, 2693 .clkr = { 2694 .enable_reg = 0x3184, 2695 .enable_mask = BIT(0), 2696 .hw.init = &(struct clk_init_data){ 2697 .name = "camss_csi2_clk", 2698 .parent_names = (const char *[]){ "csi2_clk_src" }, 2699 .num_parents = 1, 2700 .flags = CLK_SET_RATE_PARENT, 2701 .ops = &clk_branch2_ops, 2702 }, 2703 }, 2704 }; 2705 2706 static struct clk_branch camss_csi2_ahb_clk = { 2707 .halt_reg = 0x3188, 2708 .clkr = { 2709 .enable_reg = 0x3188, 2710 .enable_mask = BIT(0), 2711 .hw.init = &(struct clk_init_data){ 2712 .name = "camss_csi2_ahb_clk", 2713 .parent_names = (const char *[]){ "ahb_clk_src" }, 2714 .num_parents = 1, 2715 .flags = CLK_SET_RATE_PARENT, 2716 .ops = &clk_branch2_ops, 2717 }, 2718 }, 2719 }; 2720 2721 static struct clk_branch camss_csi2phy_clk = { 2722 .halt_reg = 0x3194, 2723 .clkr = { 2724 .enable_reg = 0x3194, 2725 .enable_mask = BIT(0), 2726 .hw.init = &(struct clk_init_data){ 2727 .name = "camss_csi2phy_clk", 2728 .parent_names = (const char *[]){ "csi2_clk_src" }, 2729 .num_parents = 1, 2730 .flags = CLK_SET_RATE_PARENT, 2731 .ops = &clk_branch2_ops, 2732 }, 2733 }, 2734 }; 2735 2736 static struct clk_branch camss_csi2rdi_clk = { 2737 .halt_reg = 0x31a4, 2738 .clkr = { 2739 .enable_reg = 0x31a4, 2740 .enable_mask = BIT(0), 2741 .hw.init = &(struct clk_init_data){ 2742 .name = "camss_csi2rdi_clk", 2743 .parent_names = (const char *[]){ "csi2_clk_src" }, 2744 .num_parents = 1, 2745 .flags = CLK_SET_RATE_PARENT, 2746 .ops = &clk_branch2_ops, 2747 }, 2748 }, 2749 }; 2750 2751 static struct clk_branch camss_csi2pix_clk = { 2752 .halt_reg = 0x31b4, 2753 .clkr = { 2754 .enable_reg = 0x31b4, 2755 .enable_mask = BIT(0), 2756 .hw.init = &(struct clk_init_data){ 2757 .name = "camss_csi2pix_clk", 2758 .parent_names = (const char *[]){ "csi2_clk_src" }, 2759 .num_parents = 1, 2760 .flags = CLK_SET_RATE_PARENT, 2761 .ops = &clk_branch2_ops, 2762 }, 2763 }, 2764 }; 2765 2766 static struct clk_branch camss_csi3_clk = { 2767 .halt_reg = 0x31e4, 2768 .clkr = { 2769 .enable_reg = 0x31e4, 2770 .enable_mask = BIT(0), 2771 .hw.init = &(struct clk_init_data){ 2772 .name = "camss_csi3_clk", 2773 .parent_names = (const char *[]){ "csi3_clk_src" }, 2774 .num_parents = 1, 2775 .flags = CLK_SET_RATE_PARENT, 2776 .ops = &clk_branch2_ops, 2777 }, 2778 }, 2779 }; 2780 2781 static struct clk_branch camss_csi3_ahb_clk = { 2782 .halt_reg = 0x31e8, 2783 .clkr = { 2784 .enable_reg = 0x31e8, 2785 .enable_mask = BIT(0), 2786 .hw.init = &(struct clk_init_data){ 2787 .name = "camss_csi3_ahb_clk", 2788 .parent_names = (const char *[]){ "ahb_clk_src" }, 2789 .num_parents = 1, 2790 .flags = CLK_SET_RATE_PARENT, 2791 .ops = &clk_branch2_ops, 2792 }, 2793 }, 2794 }; 2795 2796 static struct clk_branch camss_csi3phy_clk = { 2797 .halt_reg = 0x31f4, 2798 .clkr = { 2799 .enable_reg = 0x31f4, 2800 .enable_mask = BIT(0), 2801 .hw.init = &(struct clk_init_data){ 2802 .name = "camss_csi3phy_clk", 2803 .parent_names = (const char *[]){ "csi3_clk_src" }, 2804 .num_parents = 1, 2805 .flags = CLK_SET_RATE_PARENT, 2806 .ops = &clk_branch2_ops, 2807 }, 2808 }, 2809 }; 2810 2811 static struct clk_branch camss_csi3rdi_clk = { 2812 .halt_reg = 0x3204, 2813 .clkr = { 2814 .enable_reg = 0x3204, 2815 .enable_mask = BIT(0), 2816 .hw.init = &(struct clk_init_data){ 2817 .name = "camss_csi3rdi_clk", 2818 .parent_names = (const char *[]){ "csi3_clk_src" }, 2819 .num_parents = 1, 2820 .flags = CLK_SET_RATE_PARENT, 2821 .ops = &clk_branch2_ops, 2822 }, 2823 }, 2824 }; 2825 2826 static struct clk_branch camss_csi3pix_clk = { 2827 .halt_reg = 0x3214, 2828 .clkr = { 2829 .enable_reg = 0x3214, 2830 .enable_mask = BIT(0), 2831 .hw.init = &(struct clk_init_data){ 2832 .name = "camss_csi3pix_clk", 2833 .parent_names = (const char *[]){ "csi3_clk_src" }, 2834 .num_parents = 1, 2835 .flags = CLK_SET_RATE_PARENT, 2836 .ops = &clk_branch2_ops, 2837 }, 2838 }, 2839 }; 2840 2841 static struct clk_branch camss_ispif_ahb_clk = { 2842 .halt_reg = 0x3224, 2843 .clkr = { 2844 .enable_reg = 0x3224, 2845 .enable_mask = BIT(0), 2846 .hw.init = &(struct clk_init_data){ 2847 .name = "camss_ispif_ahb_clk", 2848 .parent_names = (const char *[]){ "ahb_clk_src" }, 2849 .num_parents = 1, 2850 .flags = CLK_SET_RATE_PARENT, 2851 .ops = &clk_branch2_ops, 2852 }, 2853 }, 2854 }; 2855 2856 static struct clk_branch fd_core_clk = { 2857 .halt_reg = 0x3b68, 2858 .clkr = { 2859 .enable_reg = 0x3b68, 2860 .enable_mask = BIT(0), 2861 .hw.init = &(struct clk_init_data){ 2862 .name = "fd_core_clk", 2863 .parent_names = (const char *[]){ "fd_core_clk_src" }, 2864 .num_parents = 1, 2865 .flags = CLK_SET_RATE_PARENT, 2866 .ops = &clk_branch2_ops, 2867 }, 2868 }, 2869 }; 2870 2871 static struct clk_branch fd_core_uar_clk = { 2872 .halt_reg = 0x3b6c, 2873 .clkr = { 2874 .enable_reg = 0x3b6c, 2875 .enable_mask = BIT(0), 2876 .hw.init = &(struct clk_init_data){ 2877 .name = "fd_core_uar_clk", 2878 .parent_names = (const char *[]){ "fd_core_clk_src" }, 2879 .num_parents = 1, 2880 .flags = CLK_SET_RATE_PARENT, 2881 .ops = &clk_branch2_ops, 2882 }, 2883 }, 2884 }; 2885 2886 static struct clk_branch fd_ahb_clk = { 2887 .halt_reg = 0x3ba74, 2888 .clkr = { 2889 .enable_reg = 0x3ba74, 2890 .enable_mask = BIT(0), 2891 .hw.init = &(struct clk_init_data){ 2892 .name = "fd_ahb_clk", 2893 .parent_names = (const char *[]){ "ahb_clk_src" }, 2894 .num_parents = 1, 2895 .flags = CLK_SET_RATE_PARENT, 2896 .ops = &clk_branch2_ops, 2897 }, 2898 }, 2899 }; 2900 2901 static struct clk_hw *mmcc_msm8996_hws[] = { 2902 &gpll0_div.hw, 2903 }; 2904 2905 static struct gdsc mmagic_bimc_gdsc = { 2906 .gdscr = 0x529c, 2907 .pd = { 2908 .name = "mmagic_bimc", 2909 }, 2910 .pwrsts = PWRSTS_OFF_ON, 2911 .flags = ALWAYS_ON, 2912 }; 2913 2914 static struct gdsc mmagic_video_gdsc = { 2915 .gdscr = 0x119c, 2916 .gds_hw_ctrl = 0x120c, 2917 .pd = { 2918 .name = "mmagic_video", 2919 }, 2920 .pwrsts = PWRSTS_OFF_ON, 2921 .flags = VOTABLE | ALWAYS_ON, 2922 }; 2923 2924 static struct gdsc mmagic_mdss_gdsc = { 2925 .gdscr = 0x247c, 2926 .gds_hw_ctrl = 0x2480, 2927 .pd = { 2928 .name = "mmagic_mdss", 2929 }, 2930 .pwrsts = PWRSTS_OFF_ON, 2931 .flags = VOTABLE | ALWAYS_ON, 2932 }; 2933 2934 static struct gdsc mmagic_camss_gdsc = { 2935 .gdscr = 0x3c4c, 2936 .gds_hw_ctrl = 0x3c50, 2937 .pd = { 2938 .name = "mmagic_camss", 2939 }, 2940 .pwrsts = PWRSTS_OFF_ON, 2941 .flags = VOTABLE | ALWAYS_ON, 2942 }; 2943 2944 static struct gdsc venus_gdsc = { 2945 .gdscr = 0x1024, 2946 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 }, 2947 .cxc_count = 3, 2948 .pd = { 2949 .name = "venus", 2950 }, 2951 .parent = &mmagic_video_gdsc.pd, 2952 .pwrsts = PWRSTS_OFF_ON, 2953 }; 2954 2955 static struct gdsc venus_core0_gdsc = { 2956 .gdscr = 0x1040, 2957 .cxcs = (unsigned int []){ 0x1048 }, 2958 .cxc_count = 1, 2959 .pd = { 2960 .name = "venus_core0", 2961 }, 2962 .parent = &venus_gdsc.pd, 2963 .pwrsts = PWRSTS_OFF_ON, 2964 .flags = HW_CTRL, 2965 }; 2966 2967 static struct gdsc venus_core1_gdsc = { 2968 .gdscr = 0x1044, 2969 .cxcs = (unsigned int []){ 0x104c }, 2970 .cxc_count = 1, 2971 .pd = { 2972 .name = "venus_core1", 2973 }, 2974 .parent = &venus_gdsc.pd, 2975 .pwrsts = PWRSTS_OFF_ON, 2976 .flags = HW_CTRL, 2977 }; 2978 2979 static struct gdsc camss_gdsc = { 2980 .gdscr = 0x34a0, 2981 .cxcs = (unsigned int []){ 0x36bc, 0x36c4 }, 2982 .cxc_count = 2, 2983 .pd = { 2984 .name = "camss", 2985 }, 2986 .parent = &mmagic_camss_gdsc.pd, 2987 .pwrsts = PWRSTS_OFF_ON, 2988 }; 2989 2990 static struct gdsc vfe0_gdsc = { 2991 .gdscr = 0x3664, 2992 .cxcs = (unsigned int []){ 0x36a8 }, 2993 .cxc_count = 1, 2994 .pd = { 2995 .name = "vfe0", 2996 }, 2997 .parent = &camss_gdsc.pd, 2998 .pwrsts = PWRSTS_OFF_ON, 2999 }; 3000 3001 static struct gdsc vfe1_gdsc = { 3002 .gdscr = 0x3674, 3003 .cxcs = (unsigned int []){ 0x36ac }, 3004 .cxc_count = 1, 3005 .pd = { 3006 .name = "vfe1", 3007 }, 3008 .parent = &camss_gdsc.pd, 3009 .pwrsts = PWRSTS_OFF_ON, 3010 }; 3011 3012 static struct gdsc jpeg_gdsc = { 3013 .gdscr = 0x35a4, 3014 .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 }, 3015 .cxc_count = 4, 3016 .pd = { 3017 .name = "jpeg", 3018 }, 3019 .parent = &camss_gdsc.pd, 3020 .pwrsts = PWRSTS_OFF_ON, 3021 }; 3022 3023 static struct gdsc cpp_gdsc = { 3024 .gdscr = 0x36d4, 3025 .cxcs = (unsigned int []){ 0x36b0 }, 3026 .cxc_count = 1, 3027 .pd = { 3028 .name = "cpp", 3029 }, 3030 .parent = &camss_gdsc.pd, 3031 .pwrsts = PWRSTS_OFF_ON, 3032 }; 3033 3034 static struct gdsc fd_gdsc = { 3035 .gdscr = 0x3b64, 3036 .cxcs = (unsigned int []){ 0x3b68, 0x3b6c }, 3037 .cxc_count = 2, 3038 .pd = { 3039 .name = "fd", 3040 }, 3041 .parent = &camss_gdsc.pd, 3042 .pwrsts = PWRSTS_OFF_ON, 3043 }; 3044 3045 static struct gdsc mdss_gdsc = { 3046 .gdscr = 0x2304, 3047 .cxcs = (unsigned int []){ 0x2310, 0x231c }, 3048 .cxc_count = 2, 3049 .pd = { 3050 .name = "mdss", 3051 }, 3052 .parent = &mmagic_mdss_gdsc.pd, 3053 .pwrsts = PWRSTS_OFF_ON, 3054 }; 3055 3056 static struct gdsc gpu_gdsc = { 3057 .gdscr = 0x4034, 3058 .gds_hw_ctrl = 0x4038, 3059 .pd = { 3060 .name = "gpu", 3061 }, 3062 .pwrsts = PWRSTS_OFF_ON, 3063 .flags = VOTABLE, 3064 }; 3065 3066 static struct gdsc gpu_gx_gdsc = { 3067 .gdscr = 0x4024, 3068 .clamp_io_ctrl = 0x4300, 3069 .cxcs = (unsigned int []){ 0x4028 }, 3070 .cxc_count = 1, 3071 .pd = { 3072 .name = "gpu_gx", 3073 }, 3074 .pwrsts = PWRSTS_OFF_ON, 3075 .flags = CLAMP_IO, 3076 }; 3077 3078 static struct clk_regmap *mmcc_msm8996_clocks[] = { 3079 [MMPLL0_EARLY] = &mmpll0_early.clkr, 3080 [MMPLL0_PLL] = &mmpll0.clkr, 3081 [MMPLL1_EARLY] = &mmpll1_early.clkr, 3082 [MMPLL1_PLL] = &mmpll1.clkr, 3083 [MMPLL2_EARLY] = &mmpll2_early.clkr, 3084 [MMPLL2_PLL] = &mmpll2.clkr, 3085 [MMPLL3_EARLY] = &mmpll3_early.clkr, 3086 [MMPLL3_PLL] = &mmpll3.clkr, 3087 [MMPLL4_EARLY] = &mmpll4_early.clkr, 3088 [MMPLL4_PLL] = &mmpll4.clkr, 3089 [MMPLL5_EARLY] = &mmpll5_early.clkr, 3090 [MMPLL5_PLL] = &mmpll5.clkr, 3091 [MMPLL8_EARLY] = &mmpll8_early.clkr, 3092 [MMPLL8_PLL] = &mmpll8.clkr, 3093 [MMPLL9_EARLY] = &mmpll9_early.clkr, 3094 [MMPLL9_PLL] = &mmpll9.clkr, 3095 [AHB_CLK_SRC] = &ahb_clk_src.clkr, 3096 [AXI_CLK_SRC] = &axi_clk_src.clkr, 3097 [MAXI_CLK_SRC] = &maxi_clk_src.clkr, 3098 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 3099 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 3100 [ISENSE_CLK_SRC] = &isense_clk_src.clkr, 3101 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 3102 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, 3103 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr, 3104 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr, 3105 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3106 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 3107 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3108 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 3109 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3110 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 3111 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3112 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 3113 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3114 [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 3115 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3116 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3117 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3118 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3119 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 3120 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 3121 [CCI_CLK_SRC] = &cci_clk_src.clkr, 3122 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3123 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3124 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 3125 [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr, 3126 [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr, 3127 [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr, 3128 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3129 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, 3130 [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr, 3131 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3132 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 3133 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3134 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3135 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3136 [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 3137 [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 3138 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr, 3139 [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr, 3140 [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr, 3141 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, 3142 [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, 3143 [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr, 3144 [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr, 3145 [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr, 3146 [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr, 3147 [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr, 3148 [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr, 3149 [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr, 3150 [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr, 3151 [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr, 3152 [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr, 3153 [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr, 3154 [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr, 3155 [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr, 3156 [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr, 3157 [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr, 3158 [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr, 3159 [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr, 3160 [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr, 3161 [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr, 3162 [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr, 3163 [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr, 3164 [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr, 3165 [GPU_AHB_CLK] = &gpu_ahb_clk.clkr, 3166 [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr, 3167 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr, 3168 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr, 3169 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr, 3170 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr, 3171 [VIDEO_CORE_CLK] = &video_core_clk.clkr, 3172 [VIDEO_AXI_CLK] = &video_axi_clk.clkr, 3173 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr, 3174 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr, 3175 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr, 3176 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr, 3177 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 3178 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, 3179 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 3180 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 3181 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 3182 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 3183 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 3184 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 3185 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 3186 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 3187 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 3188 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 3189 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 3190 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 3191 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, 3192 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 3193 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 3194 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 3195 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 3196 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 3197 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 3198 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 3199 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr, 3200 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr, 3201 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr, 3202 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr, 3203 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr, 3204 [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr, 3205 [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr, 3206 [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr, 3207 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr, 3208 [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr, 3209 [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr, 3210 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr, 3211 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr, 3212 [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr, 3213 [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr, 3214 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr, 3215 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr, 3216 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr, 3217 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr, 3218 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr, 3219 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr, 3220 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 3221 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 3222 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr, 3223 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr, 3224 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr, 3225 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr, 3226 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 3227 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 3228 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, 3229 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 3230 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 3231 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 3232 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 3233 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, 3234 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 3235 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 3236 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 3237 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 3238 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, 3239 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 3240 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 3241 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 3242 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 3243 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, 3244 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 3245 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 3246 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 3247 [FD_CORE_CLK] = &fd_core_clk.clkr, 3248 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr, 3249 [FD_AHB_CLK] = &fd_ahb_clk.clkr, 3250 }; 3251 3252 static struct gdsc *mmcc_msm8996_gdscs[] = { 3253 [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc, 3254 [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc, 3255 [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc, 3256 [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc, 3257 [VENUS_GDSC] = &venus_gdsc, 3258 [VENUS_CORE0_GDSC] = &venus_core0_gdsc, 3259 [VENUS_CORE1_GDSC] = &venus_core1_gdsc, 3260 [CAMSS_GDSC] = &camss_gdsc, 3261 [VFE0_GDSC] = &vfe0_gdsc, 3262 [VFE1_GDSC] = &vfe1_gdsc, 3263 [JPEG_GDSC] = &jpeg_gdsc, 3264 [CPP_GDSC] = &cpp_gdsc, 3265 [FD_GDSC] = &fd_gdsc, 3266 [MDSS_GDSC] = &mdss_gdsc, 3267 [GPU_GDSC] = &gpu_gdsc, 3268 [GPU_GX_GDSC] = &gpu_gx_gdsc, 3269 }; 3270 3271 static const struct qcom_reset_map mmcc_msm8996_resets[] = { 3272 [MMAGICAHB_BCR] = { 0x5020 }, 3273 [MMAGIC_CFG_BCR] = { 0x5050 }, 3274 [MISC_BCR] = { 0x5010 }, 3275 [BTO_BCR] = { 0x5030 }, 3276 [MMAGICAXI_BCR] = { 0x5060 }, 3277 [MMAGICMAXI_BCR] = { 0x5070 }, 3278 [DSA_BCR] = { 0x50a0 }, 3279 [MMAGIC_CAMSS_BCR] = { 0x3c40 }, 3280 [THROTTLE_CAMSS_BCR] = { 0x3c30 }, 3281 [SMMU_VFE_BCR] = { 0x3c00 }, 3282 [SMMU_CPP_BCR] = { 0x3c10 }, 3283 [SMMU_JPEG_BCR] = { 0x3c20 }, 3284 [MMAGIC_MDSS_BCR] = { 0x2470 }, 3285 [THROTTLE_MDSS_BCR] = { 0x2460 }, 3286 [SMMU_ROT_BCR] = { 0x2440 }, 3287 [SMMU_MDP_BCR] = { 0x2450 }, 3288 [MMAGIC_VIDEO_BCR] = { 0x1190 }, 3289 [THROTTLE_VIDEO_BCR] = { 0x1180 }, 3290 [SMMU_VIDEO_BCR] = { 0x1170 }, 3291 [MMAGIC_BIMC_BCR] = { 0x5290 }, 3292 [GPU_GX_BCR] = { 0x4020 }, 3293 [GPU_BCR] = { 0x4030 }, 3294 [GPU_AON_BCR] = { 0x4040 }, 3295 [VMEM_BCR] = { 0x1200 }, 3296 [MMSS_RBCPR_BCR] = { 0x4080 }, 3297 [VIDEO_BCR] = { 0x1020 }, 3298 [MDSS_BCR] = { 0x2300 }, 3299 [CAMSS_TOP_BCR] = { 0x3480 }, 3300 [CAMSS_AHB_BCR] = { 0x3488 }, 3301 [CAMSS_MICRO_BCR] = { 0x3490 }, 3302 [CAMSS_CCI_BCR] = { 0x3340 }, 3303 [CAMSS_PHY0_BCR] = { 0x3020 }, 3304 [CAMSS_PHY1_BCR] = { 0x3050 }, 3305 [CAMSS_PHY2_BCR] = { 0x3080 }, 3306 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 }, 3307 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 }, 3308 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 }, 3309 [CAMSS_JPEG_BCR] = { 0x35a0 }, 3310 [CAMSS_VFE_BCR] = { 0x36a0 }, 3311 [CAMSS_VFE0_BCR] = { 0x3660 }, 3312 [CAMSS_VFE1_BCR] = { 0x3670 }, 3313 [CAMSS_CSI_VFE0_BCR] = { 0x3700 }, 3314 [CAMSS_CSI_VFE1_BCR] = { 0x3710 }, 3315 [CAMSS_CPP_TOP_BCR] = { 0x36c0 }, 3316 [CAMSS_CPP_BCR] = { 0x36d0 }, 3317 [CAMSS_CSI0_BCR] = { 0x30b0 }, 3318 [CAMSS_CSI0RDI_BCR] = { 0x30d0 }, 3319 [CAMSS_CSI0PIX_BCR] = { 0x30e0 }, 3320 [CAMSS_CSI1_BCR] = { 0x3120 }, 3321 [CAMSS_CSI1RDI_BCR] = { 0x3140 }, 3322 [CAMSS_CSI1PIX_BCR] = { 0x3150 }, 3323 [CAMSS_CSI2_BCR] = { 0x3180 }, 3324 [CAMSS_CSI2RDI_BCR] = { 0x31a0 }, 3325 [CAMSS_CSI2PIX_BCR] = { 0x31b0 }, 3326 [CAMSS_CSI3_BCR] = { 0x31e0 }, 3327 [CAMSS_CSI3RDI_BCR] = { 0x3200 }, 3328 [CAMSS_CSI3PIX_BCR] = { 0x3210 }, 3329 [CAMSS_ISPIF_BCR] = { 0x3220 }, 3330 [FD_BCR] = { 0x3b60 }, 3331 [MMSS_SPDM_RM_BCR] = { 0x300 }, 3332 }; 3333 3334 static const struct regmap_config mmcc_msm8996_regmap_config = { 3335 .reg_bits = 32, 3336 .reg_stride = 4, 3337 .val_bits = 32, 3338 .max_register = 0xb008, 3339 .fast_io = true, 3340 }; 3341 3342 static const struct qcom_cc_desc mmcc_msm8996_desc = { 3343 .config = &mmcc_msm8996_regmap_config, 3344 .clks = mmcc_msm8996_clocks, 3345 .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks), 3346 .resets = mmcc_msm8996_resets, 3347 .num_resets = ARRAY_SIZE(mmcc_msm8996_resets), 3348 .gdscs = mmcc_msm8996_gdscs, 3349 .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs), 3350 .clk_hws = mmcc_msm8996_hws, 3351 .num_clk_hws = ARRAY_SIZE(mmcc_msm8996_hws), 3352 }; 3353 3354 static const struct of_device_id mmcc_msm8996_match_table[] = { 3355 { .compatible = "qcom,mmcc-msm8996" }, 3356 { } 3357 }; 3358 MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table); 3359 3360 static int mmcc_msm8996_probe(struct platform_device *pdev) 3361 { 3362 struct regmap *regmap; 3363 3364 regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc); 3365 if (IS_ERR(regmap)) 3366 return PTR_ERR(regmap); 3367 3368 /* Disable the AHB DCD */ 3369 regmap_update_bits(regmap, 0x50d8, BIT(31), 0); 3370 /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */ 3371 regmap_update_bits(regmap, 0x5054, BIT(15), 0); 3372 3373 return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap); 3374 } 3375 3376 static struct platform_driver mmcc_msm8996_driver = { 3377 .probe = mmcc_msm8996_probe, 3378 .driver = { 3379 .name = "mmcc-msm8996", 3380 .of_match_table = mmcc_msm8996_match_table, 3381 }, 3382 }; 3383 module_platform_driver(mmcc_msm8996_driver); 3384 3385 MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver"); 3386 MODULE_LICENSE("GPL v2"); 3387 MODULE_ALIAS("platform:mmcc-msm8996"); 3388