19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2c2526597SStephen Boyd /*x 3c2526597SStephen Boyd * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4c2526597SStephen Boyd */ 5c2526597SStephen Boyd 6c2526597SStephen Boyd #include <linux/kernel.h> 7c2526597SStephen Boyd #include <linux/bitops.h> 8c2526597SStephen Boyd #include <linux/err.h> 9c2526597SStephen Boyd #include <linux/platform_device.h> 10c2526597SStephen Boyd #include <linux/module.h> 11c2526597SStephen Boyd #include <linux/of.h> 12c2526597SStephen Boyd #include <linux/of_device.h> 13c2526597SStephen Boyd #include <linux/clk-provider.h> 14c2526597SStephen Boyd #include <linux/regmap.h> 15c2526597SStephen Boyd #include <linux/reset-controller.h> 16c2526597SStephen Boyd #include <linux/clk.h> 17c2526597SStephen Boyd 18c2526597SStephen Boyd #include <dt-bindings/clock/qcom,mmcc-msm8996.h> 19c2526597SStephen Boyd 20c2526597SStephen Boyd #include "common.h" 21c2526597SStephen Boyd #include "clk-regmap.h" 22c2526597SStephen Boyd #include "clk-regmap-divider.h" 23c2526597SStephen Boyd #include "clk-alpha-pll.h" 24c2526597SStephen Boyd #include "clk-rcg.h" 25c2526597SStephen Boyd #include "clk-branch.h" 26c2526597SStephen Boyd #include "reset.h" 277e824d50SRajendra Nayak #include "gdsc.h" 28c2526597SStephen Boyd 29c2526597SStephen Boyd enum { 30c2526597SStephen Boyd P_XO, 31c2526597SStephen Boyd P_MMPLL0, 32c2526597SStephen Boyd P_GPLL0, 33c2526597SStephen Boyd P_GPLL0_DIV, 34c2526597SStephen Boyd P_MMPLL1, 35c2526597SStephen Boyd P_MMPLL9, 36c2526597SStephen Boyd P_MMPLL2, 37c2526597SStephen Boyd P_MMPLL8, 38c2526597SStephen Boyd P_MMPLL3, 39c2526597SStephen Boyd P_DSI0PLL, 40c2526597SStephen Boyd P_DSI1PLL, 41c2526597SStephen Boyd P_MMPLL5, 42c2526597SStephen Boyd P_HDMIPLL, 43c2526597SStephen Boyd P_DSI0PLL_BYTE, 44c2526597SStephen Boyd P_DSI1PLL_BYTE, 45c2526597SStephen Boyd P_MMPLL4, 46c2526597SStephen Boyd }; 47c2526597SStephen Boyd 48c2526597SStephen Boyd static struct clk_fixed_factor gpll0_div = { 49c2526597SStephen Boyd .mult = 1, 50c2526597SStephen Boyd .div = 2, 51c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 52c2526597SStephen Boyd .name = "gpll0_div", 53*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 54*e7c65912SDmitry Baryshkov { .fw_name = "gpll0", .name = "gpll0" }, 55*e7c65912SDmitry Baryshkov }, 56c2526597SStephen Boyd .num_parents = 1, 57c2526597SStephen Boyd .ops = &clk_fixed_factor_ops, 58c2526597SStephen Boyd }, 59c2526597SStephen Boyd }; 60c2526597SStephen Boyd 61c2526597SStephen Boyd static struct pll_vco mmpll_p_vco[] = { 62c2526597SStephen Boyd { 250000000, 500000000, 3 }, 63c2526597SStephen Boyd { 500000000, 1000000000, 2 }, 64c2526597SStephen Boyd { 1000000000, 1500000000, 1 }, 65c2526597SStephen Boyd { 1500000000, 2000000000, 0 }, 66c2526597SStephen Boyd }; 67c2526597SStephen Boyd 68c2526597SStephen Boyd static struct pll_vco mmpll_gfx_vco[] = { 69c2526597SStephen Boyd { 400000000, 1000000000, 2 }, 70c2526597SStephen Boyd { 1000000000, 1500000000, 1 }, 71c2526597SStephen Boyd { 1500000000, 2000000000, 0 }, 72c2526597SStephen Boyd }; 73c2526597SStephen Boyd 74c2526597SStephen Boyd static struct pll_vco mmpll_t_vco[] = { 75c2526597SStephen Boyd { 500000000, 1500000000, 0 }, 76c2526597SStephen Boyd }; 77c2526597SStephen Boyd 78c2526597SStephen Boyd static struct clk_alpha_pll mmpll0_early = { 79c2526597SStephen Boyd .offset = 0x0, 8028d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 81c2526597SStephen Boyd .vco_table = mmpll_p_vco, 82c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 83c2526597SStephen Boyd .clkr = { 84c2526597SStephen Boyd .enable_reg = 0x100, 85c2526597SStephen Boyd .enable_mask = BIT(0), 86c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 87c2526597SStephen Boyd .name = "mmpll0_early", 88*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 89*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 90*e7c65912SDmitry Baryshkov }, 91c2526597SStephen Boyd .num_parents = 1, 92c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 93c2526597SStephen Boyd }, 94c2526597SStephen Boyd }, 95c2526597SStephen Boyd }; 96c2526597SStephen Boyd 97c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll0 = { 98c2526597SStephen Boyd .offset = 0x0, 9928d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 100c2526597SStephen Boyd .width = 4, 101c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 102c2526597SStephen Boyd .name = "mmpll0", 103*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 104*e7c65912SDmitry Baryshkov &mmpll0_early.clkr.hw 105*e7c65912SDmitry Baryshkov }, 106c2526597SStephen Boyd .num_parents = 1, 107c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 108c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 109c2526597SStephen Boyd }, 110c2526597SStephen Boyd }; 111c2526597SStephen Boyd 112c2526597SStephen Boyd static struct clk_alpha_pll mmpll1_early = { 113c2526597SStephen Boyd .offset = 0x30, 11428d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 115c2526597SStephen Boyd .vco_table = mmpll_p_vco, 116c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 117c2526597SStephen Boyd .clkr = { 118c2526597SStephen Boyd .enable_reg = 0x100, 119c2526597SStephen Boyd .enable_mask = BIT(1), 120c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 121c2526597SStephen Boyd .name = "mmpll1_early", 122*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 123*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 124*e7c65912SDmitry Baryshkov }, 125c2526597SStephen Boyd .num_parents = 1, 126c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 127c2526597SStephen Boyd } 128c2526597SStephen Boyd }, 129c2526597SStephen Boyd }; 130c2526597SStephen Boyd 131c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll1 = { 132c2526597SStephen Boyd .offset = 0x30, 13328d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 134c2526597SStephen Boyd .width = 4, 135c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 136c2526597SStephen Boyd .name = "mmpll1", 137*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 138*e7c65912SDmitry Baryshkov &mmpll1_early.clkr.hw 139*e7c65912SDmitry Baryshkov }, 140c2526597SStephen Boyd .num_parents = 1, 141c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 142c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 143c2526597SStephen Boyd }, 144c2526597SStephen Boyd }; 145c2526597SStephen Boyd 146c2526597SStephen Boyd static struct clk_alpha_pll mmpll2_early = { 147c2526597SStephen Boyd .offset = 0x4100, 14828d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 149c2526597SStephen Boyd .vco_table = mmpll_gfx_vco, 150c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 151c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 152c2526597SStephen Boyd .name = "mmpll2_early", 153*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 154*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 155*e7c65912SDmitry Baryshkov }, 156c2526597SStephen Boyd .num_parents = 1, 157c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 158c2526597SStephen Boyd }, 159c2526597SStephen Boyd }; 160c2526597SStephen Boyd 161c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll2 = { 162c2526597SStephen Boyd .offset = 0x4100, 16328d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 164c2526597SStephen Boyd .width = 4, 165c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 166c2526597SStephen Boyd .name = "mmpll2", 167*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 168*e7c65912SDmitry Baryshkov &mmpll2_early.clkr.hw 169*e7c65912SDmitry Baryshkov }, 170c2526597SStephen Boyd .num_parents = 1, 171c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 172c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 173c2526597SStephen Boyd }, 174c2526597SStephen Boyd }; 175c2526597SStephen Boyd 176c2526597SStephen Boyd static struct clk_alpha_pll mmpll3_early = { 177c2526597SStephen Boyd .offset = 0x60, 17828d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 179c2526597SStephen Boyd .vco_table = mmpll_p_vco, 180c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 181c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 182c2526597SStephen Boyd .name = "mmpll3_early", 183*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 184*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 185*e7c65912SDmitry Baryshkov }, 186c2526597SStephen Boyd .num_parents = 1, 187c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 188c2526597SStephen Boyd }, 189c2526597SStephen Boyd }; 190c2526597SStephen Boyd 191c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll3 = { 192c2526597SStephen Boyd .offset = 0x60, 19328d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 194c2526597SStephen Boyd .width = 4, 195c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 196c2526597SStephen Boyd .name = "mmpll3", 197*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 198*e7c65912SDmitry Baryshkov &mmpll3_early.clkr.hw 199*e7c65912SDmitry Baryshkov }, 200c2526597SStephen Boyd .num_parents = 1, 201c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 202c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 203c2526597SStephen Boyd }, 204c2526597SStephen Boyd }; 205c2526597SStephen Boyd 206c2526597SStephen Boyd static struct clk_alpha_pll mmpll4_early = { 207c2526597SStephen Boyd .offset = 0x90, 20828d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 209c2526597SStephen Boyd .vco_table = mmpll_t_vco, 210c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_t_vco), 211c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 212c2526597SStephen Boyd .name = "mmpll4_early", 213*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 214*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 215*e7c65912SDmitry Baryshkov }, 216c2526597SStephen Boyd .num_parents = 1, 217c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 218c2526597SStephen Boyd }, 219c2526597SStephen Boyd }; 220c2526597SStephen Boyd 221c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll4 = { 222c2526597SStephen Boyd .offset = 0x90, 22328d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 224c2526597SStephen Boyd .width = 2, 225c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 226c2526597SStephen Boyd .name = "mmpll4", 227*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 228*e7c65912SDmitry Baryshkov &mmpll4_early.clkr.hw 229*e7c65912SDmitry Baryshkov }, 230c2526597SStephen Boyd .num_parents = 1, 231c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 232c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 233c2526597SStephen Boyd }, 234c2526597SStephen Boyd }; 235c2526597SStephen Boyd 236c2526597SStephen Boyd static struct clk_alpha_pll mmpll5_early = { 237c2526597SStephen Boyd .offset = 0xc0, 23828d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 239c2526597SStephen Boyd .vco_table = mmpll_p_vco, 240c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 241c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 242c2526597SStephen Boyd .name = "mmpll5_early", 243*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 244*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 245*e7c65912SDmitry Baryshkov }, 246c2526597SStephen Boyd .num_parents = 1, 247c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 248c2526597SStephen Boyd }, 249c2526597SStephen Boyd }; 250c2526597SStephen Boyd 251c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll5 = { 252c2526597SStephen Boyd .offset = 0xc0, 25328d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 254c2526597SStephen Boyd .width = 4, 255c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 256c2526597SStephen Boyd .name = "mmpll5", 257*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 258*e7c65912SDmitry Baryshkov &mmpll5_early.clkr.hw 259*e7c65912SDmitry Baryshkov }, 260c2526597SStephen Boyd .num_parents = 1, 261c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 262c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 263c2526597SStephen Boyd }, 264c2526597SStephen Boyd }; 265c2526597SStephen Boyd 266c2526597SStephen Boyd static struct clk_alpha_pll mmpll8_early = { 267c2526597SStephen Boyd .offset = 0x4130, 26828d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 269c2526597SStephen Boyd .vco_table = mmpll_gfx_vco, 270c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 271c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 272c2526597SStephen Boyd .name = "mmpll8_early", 273*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 274*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 275*e7c65912SDmitry Baryshkov }, 276c2526597SStephen Boyd .num_parents = 1, 277c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 278c2526597SStephen Boyd }, 279c2526597SStephen Boyd }; 280c2526597SStephen Boyd 281c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll8 = { 282c2526597SStephen Boyd .offset = 0x4130, 28328d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 284c2526597SStephen Boyd .width = 4, 285c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 286c2526597SStephen Boyd .name = "mmpll8", 287*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 288*e7c65912SDmitry Baryshkov &mmpll8_early.clkr.hw 289*e7c65912SDmitry Baryshkov }, 290c2526597SStephen Boyd .num_parents = 1, 291c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 292c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 293c2526597SStephen Boyd }, 294c2526597SStephen Boyd }; 295c2526597SStephen Boyd 296c2526597SStephen Boyd static struct clk_alpha_pll mmpll9_early = { 297c2526597SStephen Boyd .offset = 0x4200, 29828d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 299c2526597SStephen Boyd .vco_table = mmpll_t_vco, 300c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_t_vco), 301c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 302c2526597SStephen Boyd .name = "mmpll9_early", 303*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 304*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 305*e7c65912SDmitry Baryshkov }, 306c2526597SStephen Boyd .num_parents = 1, 307c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 308c2526597SStephen Boyd }, 309c2526597SStephen Boyd }; 310c2526597SStephen Boyd 311c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll9 = { 312c2526597SStephen Boyd .offset = 0x4200, 31328d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 314c2526597SStephen Boyd .width = 2, 315c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 316c2526597SStephen Boyd .name = "mmpll9", 317*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 318*e7c65912SDmitry Baryshkov &mmpll9_early.clkr.hw 319*e7c65912SDmitry Baryshkov }, 320c2526597SStephen Boyd .num_parents = 1, 321c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 322c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 323c2526597SStephen Boyd }, 324c2526597SStephen Boyd }; 325c2526597SStephen Boyd 326208c564fSDmitry Baryshkov static const struct parent_map mmss_xo_hdmi_map[] = { 327208c564fSDmitry Baryshkov { P_XO, 0 }, 328208c564fSDmitry Baryshkov { P_HDMIPLL, 1 } 329208c564fSDmitry Baryshkov }; 330208c564fSDmitry Baryshkov 331*e7c65912SDmitry Baryshkov static const struct clk_parent_data mmss_xo_hdmi[] = { 332*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 333*e7c65912SDmitry Baryshkov { .fw_name = "hdmipll", .name = "hdmipll" } 334208c564fSDmitry Baryshkov }; 335208c564fSDmitry Baryshkov 336208c564fSDmitry Baryshkov static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { 337208c564fSDmitry Baryshkov { P_XO, 0 }, 338208c564fSDmitry Baryshkov { P_DSI0PLL, 1 }, 339208c564fSDmitry Baryshkov { P_DSI1PLL, 2 } 340208c564fSDmitry Baryshkov }; 341208c564fSDmitry Baryshkov 342*e7c65912SDmitry Baryshkov static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = { 343*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 344*e7c65912SDmitry Baryshkov { .fw_name = "dsi0pll", .name = "dsi0pll" }, 345*e7c65912SDmitry Baryshkov { .fw_name = "dsi1pll", .name = "dsi1pll" } 346208c564fSDmitry Baryshkov }; 347208c564fSDmitry Baryshkov 348208c564fSDmitry Baryshkov static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { 349208c564fSDmitry Baryshkov { P_XO, 0 }, 350208c564fSDmitry Baryshkov { P_GPLL0, 5 }, 351208c564fSDmitry Baryshkov { P_GPLL0_DIV, 6 } 352208c564fSDmitry Baryshkov }; 353208c564fSDmitry Baryshkov 354*e7c65912SDmitry Baryshkov static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = { 355*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 356*e7c65912SDmitry Baryshkov { .fw_name = "gpll0", .name = "gpll0" }, 357*e7c65912SDmitry Baryshkov { .hw = &gpll0_div.hw } 358208c564fSDmitry Baryshkov }; 359208c564fSDmitry Baryshkov 360208c564fSDmitry Baryshkov static const struct parent_map mmss_xo_dsibyte_map[] = { 361208c564fSDmitry Baryshkov { P_XO, 0 }, 362208c564fSDmitry Baryshkov { P_DSI0PLL_BYTE, 1 }, 363208c564fSDmitry Baryshkov { P_DSI1PLL_BYTE, 2 } 364208c564fSDmitry Baryshkov }; 365208c564fSDmitry Baryshkov 366*e7c65912SDmitry Baryshkov static const struct clk_parent_data mmss_xo_dsibyte[] = { 367*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 368*e7c65912SDmitry Baryshkov { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, 369*e7c65912SDmitry Baryshkov { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" } 370208c564fSDmitry Baryshkov }; 371208c564fSDmitry Baryshkov 372208c564fSDmitry Baryshkov static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { 373208c564fSDmitry Baryshkov { P_XO, 0 }, 374208c564fSDmitry Baryshkov { P_MMPLL0, 1 }, 375208c564fSDmitry Baryshkov { P_GPLL0, 5 }, 376208c564fSDmitry Baryshkov { P_GPLL0_DIV, 6 } 377208c564fSDmitry Baryshkov }; 378208c564fSDmitry Baryshkov 379*e7c65912SDmitry Baryshkov static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = { 380*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 381*e7c65912SDmitry Baryshkov { .hw = &mmpll0.clkr.hw }, 382*e7c65912SDmitry Baryshkov { .fw_name = "gpll0", .name = "gpll0" }, 383*e7c65912SDmitry Baryshkov { .hw = &gpll0_div.hw } 384208c564fSDmitry Baryshkov }; 385208c564fSDmitry Baryshkov 386208c564fSDmitry Baryshkov static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { 387208c564fSDmitry Baryshkov { P_XO, 0 }, 388208c564fSDmitry Baryshkov { P_MMPLL0, 1 }, 389208c564fSDmitry Baryshkov { P_MMPLL1, 2 }, 390208c564fSDmitry Baryshkov { P_GPLL0, 5 }, 391208c564fSDmitry Baryshkov { P_GPLL0_DIV, 6 } 392208c564fSDmitry Baryshkov }; 393208c564fSDmitry Baryshkov 394*e7c65912SDmitry Baryshkov static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { 395*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 396*e7c65912SDmitry Baryshkov { .hw = &mmpll0.clkr.hw }, 397*e7c65912SDmitry Baryshkov { .hw = &mmpll1.clkr.hw }, 398*e7c65912SDmitry Baryshkov { .fw_name = "gpll0", .name = "gpll0" }, 399*e7c65912SDmitry Baryshkov { .hw = &gpll0_div.hw } 400208c564fSDmitry Baryshkov }; 401208c564fSDmitry Baryshkov 402208c564fSDmitry Baryshkov static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { 403208c564fSDmitry Baryshkov { P_XO, 0 }, 404208c564fSDmitry Baryshkov { P_MMPLL0, 1 }, 405208c564fSDmitry Baryshkov { P_MMPLL3, 3 }, 406208c564fSDmitry Baryshkov { P_GPLL0, 5 }, 407208c564fSDmitry Baryshkov { P_GPLL0_DIV, 6 } 408208c564fSDmitry Baryshkov }; 409208c564fSDmitry Baryshkov 410*e7c65912SDmitry Baryshkov static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { 411*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 412*e7c65912SDmitry Baryshkov { .hw = &mmpll0.clkr.hw }, 413*e7c65912SDmitry Baryshkov { .hw = &mmpll3.clkr.hw }, 414*e7c65912SDmitry Baryshkov { .fw_name = "gpll0", .name = "gpll0" }, 415*e7c65912SDmitry Baryshkov { .hw = &gpll0_div.hw } 416208c564fSDmitry Baryshkov }; 417208c564fSDmitry Baryshkov 418208c564fSDmitry Baryshkov static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { 419208c564fSDmitry Baryshkov { P_XO, 0 }, 420208c564fSDmitry Baryshkov { P_MMPLL0, 1 }, 421208c564fSDmitry Baryshkov { P_MMPLL5, 2 }, 422208c564fSDmitry Baryshkov { P_GPLL0, 5 }, 423208c564fSDmitry Baryshkov { P_GPLL0_DIV, 6 } 424208c564fSDmitry Baryshkov }; 425208c564fSDmitry Baryshkov 426*e7c65912SDmitry Baryshkov static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { 427*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 428*e7c65912SDmitry Baryshkov { .hw = &mmpll0.clkr.hw }, 429*e7c65912SDmitry Baryshkov { .hw = &mmpll5.clkr.hw }, 430*e7c65912SDmitry Baryshkov { .fw_name = "gpll0", .name = "gpll0" }, 431*e7c65912SDmitry Baryshkov { .hw = &gpll0_div.hw } 432208c564fSDmitry Baryshkov }; 433208c564fSDmitry Baryshkov 434208c564fSDmitry Baryshkov static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { 435208c564fSDmitry Baryshkov { P_XO, 0 }, 436208c564fSDmitry Baryshkov { P_MMPLL0, 1 }, 437208c564fSDmitry Baryshkov { P_MMPLL4, 3 }, 438208c564fSDmitry Baryshkov { P_GPLL0, 5 }, 439208c564fSDmitry Baryshkov { P_GPLL0_DIV, 6 } 440208c564fSDmitry Baryshkov }; 441208c564fSDmitry Baryshkov 442*e7c65912SDmitry Baryshkov static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { 443*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 444*e7c65912SDmitry Baryshkov { .hw = &mmpll0.clkr.hw }, 445*e7c65912SDmitry Baryshkov { .hw = &mmpll4.clkr.hw }, 446*e7c65912SDmitry Baryshkov { .fw_name = "gpll0", .name = "gpll0" }, 447*e7c65912SDmitry Baryshkov { .hw = &gpll0_div.hw } 448208c564fSDmitry Baryshkov }; 449208c564fSDmitry Baryshkov 450208c564fSDmitry Baryshkov static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { 451208c564fSDmitry Baryshkov { P_XO, 0 }, 452208c564fSDmitry Baryshkov { P_MMPLL0, 1 }, 453208c564fSDmitry Baryshkov { P_MMPLL9, 2 }, 454208c564fSDmitry Baryshkov { P_MMPLL2, 3 }, 455208c564fSDmitry Baryshkov { P_MMPLL8, 4 }, 456208c564fSDmitry Baryshkov { P_GPLL0, 5 } 457208c564fSDmitry Baryshkov }; 458208c564fSDmitry Baryshkov 459*e7c65912SDmitry Baryshkov static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { 460*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 461*e7c65912SDmitry Baryshkov { .hw = &mmpll0.clkr.hw }, 462*e7c65912SDmitry Baryshkov { .hw = &mmpll9.clkr.hw }, 463*e7c65912SDmitry Baryshkov { .hw = &mmpll2.clkr.hw }, 464*e7c65912SDmitry Baryshkov { .hw = &mmpll8.clkr.hw }, 465*e7c65912SDmitry Baryshkov { .fw_name = "gpll0", .name = "gpll0" }, 466208c564fSDmitry Baryshkov }; 467208c564fSDmitry Baryshkov 468208c564fSDmitry Baryshkov static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { 469208c564fSDmitry Baryshkov { P_XO, 0 }, 470208c564fSDmitry Baryshkov { P_MMPLL0, 1 }, 471208c564fSDmitry Baryshkov { P_MMPLL9, 2 }, 472208c564fSDmitry Baryshkov { P_MMPLL2, 3 }, 473208c564fSDmitry Baryshkov { P_MMPLL8, 4 }, 474208c564fSDmitry Baryshkov { P_GPLL0, 5 }, 475208c564fSDmitry Baryshkov { P_GPLL0_DIV, 6 } 476208c564fSDmitry Baryshkov }; 477208c564fSDmitry Baryshkov 478*e7c65912SDmitry Baryshkov static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { 479*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 480*e7c65912SDmitry Baryshkov { .hw = &mmpll0.clkr.hw }, 481*e7c65912SDmitry Baryshkov { .hw = &mmpll9.clkr.hw }, 482*e7c65912SDmitry Baryshkov { .hw = &mmpll2.clkr.hw }, 483*e7c65912SDmitry Baryshkov { .hw = &mmpll8.clkr.hw }, 484*e7c65912SDmitry Baryshkov { .fw_name = "gpll0", .name = "gpll0" }, 485*e7c65912SDmitry Baryshkov { .hw = &gpll0_div.hw } 486208c564fSDmitry Baryshkov }; 487208c564fSDmitry Baryshkov 488208c564fSDmitry Baryshkov static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { 489208c564fSDmitry Baryshkov { P_XO, 0 }, 490208c564fSDmitry Baryshkov { P_MMPLL0, 1 }, 491208c564fSDmitry Baryshkov { P_MMPLL1, 2 }, 492208c564fSDmitry Baryshkov { P_MMPLL4, 3 }, 493208c564fSDmitry Baryshkov { P_MMPLL3, 4 }, 494208c564fSDmitry Baryshkov { P_GPLL0, 5 }, 495208c564fSDmitry Baryshkov { P_GPLL0_DIV, 6 } 496208c564fSDmitry Baryshkov }; 497208c564fSDmitry Baryshkov 498*e7c65912SDmitry Baryshkov static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { 499*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 500*e7c65912SDmitry Baryshkov { .hw = &mmpll0.clkr.hw }, 501*e7c65912SDmitry Baryshkov { .hw = &mmpll1.clkr.hw }, 502*e7c65912SDmitry Baryshkov { .hw = &mmpll4.clkr.hw }, 503*e7c65912SDmitry Baryshkov { .hw = &mmpll3.clkr.hw }, 504*e7c65912SDmitry Baryshkov { .fw_name = "gpll0", .name = "gpll0" }, 505*e7c65912SDmitry Baryshkov { .hw = &gpll0_div.hw } 506208c564fSDmitry Baryshkov }; 507208c564fSDmitry Baryshkov 508c2526597SStephen Boyd static const struct freq_tbl ftbl_ahb_clk_src[] = { 509c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 510c2526597SStephen Boyd F(40000000, P_GPLL0_DIV, 7.5, 0, 0), 511c2526597SStephen Boyd F(80000000, P_MMPLL0, 10, 0, 0), 512c2526597SStephen Boyd { } 513c2526597SStephen Boyd }; 514c2526597SStephen Boyd 515c2526597SStephen Boyd static struct clk_rcg2 ahb_clk_src = { 516c2526597SStephen Boyd .cmd_rcgr = 0x5000, 517c2526597SStephen Boyd .hid_width = 5, 518c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 519c2526597SStephen Boyd .freq_tbl = ftbl_ahb_clk_src, 520c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 521c2526597SStephen Boyd .name = "ahb_clk_src", 522*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div, 523a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div), 524c2526597SStephen Boyd .ops = &clk_rcg2_ops, 525c2526597SStephen Boyd }, 526c2526597SStephen Boyd }; 527c2526597SStephen Boyd 528c2526597SStephen Boyd static const struct freq_tbl ftbl_axi_clk_src[] = { 529c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 530c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 531c2526597SStephen Boyd F(100000000, P_GPLL0, 6, 0, 0), 532c2526597SStephen Boyd F(171430000, P_GPLL0, 3.5, 0, 0), 533c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 534c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 535c2526597SStephen Boyd F(400000000, P_MMPLL0, 2, 0, 0), 536c2526597SStephen Boyd { } 537c2526597SStephen Boyd }; 538c2526597SStephen Boyd 539c2526597SStephen Boyd static struct clk_rcg2 axi_clk_src = { 540c2526597SStephen Boyd .cmd_rcgr = 0x5040, 541c2526597SStephen Boyd .hid_width = 5, 542c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 543c2526597SStephen Boyd .freq_tbl = ftbl_axi_clk_src, 544c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 545c2526597SStephen Boyd .name = "axi_clk_src", 546*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 547a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div), 548c2526597SStephen Boyd .ops = &clk_rcg2_ops, 549c2526597SStephen Boyd }, 550c2526597SStephen Boyd }; 551c2526597SStephen Boyd 552c2526597SStephen Boyd static struct clk_rcg2 maxi_clk_src = { 553c2526597SStephen Boyd .cmd_rcgr = 0x5090, 554c2526597SStephen Boyd .hid_width = 5, 555c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 556c2526597SStephen Boyd .freq_tbl = ftbl_axi_clk_src, 557c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 558c2526597SStephen Boyd .name = "maxi_clk_src", 559*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 560a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div), 561c2526597SStephen Boyd .ops = &clk_rcg2_ops, 562c2526597SStephen Boyd }, 563c2526597SStephen Boyd }; 564c2526597SStephen Boyd 565eaf87e56SAngeloGioacchino Del Regno static struct clk_rcg2_gfx3d gfx3d_clk_src = { 566eaf87e56SAngeloGioacchino Del Regno .rcg = { 567c2526597SStephen Boyd .cmd_rcgr = 0x4000, 568c2526597SStephen Boyd .hid_width = 5, 569c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map, 570c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 571c2526597SStephen Boyd .name = "gfx3d_clk_src", 572*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, 573a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0), 574c2526597SStephen Boyd .ops = &clk_gfx3d_ops, 575c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 576c2526597SStephen Boyd }, 577eaf87e56SAngeloGioacchino Del Regno }, 578eaf87e56SAngeloGioacchino Del Regno .hws = (struct clk_hw*[]) { 579eaf87e56SAngeloGioacchino Del Regno &mmpll9.clkr.hw, 580eaf87e56SAngeloGioacchino Del Regno &mmpll2.clkr.hw, 581eaf87e56SAngeloGioacchino Del Regno &mmpll8.clkr.hw 582eaf87e56SAngeloGioacchino Del Regno }, 583c2526597SStephen Boyd }; 584c2526597SStephen Boyd 585c2526597SStephen Boyd static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { 586c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 587c2526597SStephen Boyd { } 588c2526597SStephen Boyd }; 589c2526597SStephen Boyd 590c2526597SStephen Boyd static struct clk_rcg2 rbbmtimer_clk_src = { 591c2526597SStephen Boyd .cmd_rcgr = 0x4090, 592c2526597SStephen Boyd .hid_width = 5, 593c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 594c2526597SStephen Boyd .freq_tbl = ftbl_rbbmtimer_clk_src, 595c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 596c2526597SStephen Boyd .name = "rbbmtimer_clk_src", 597*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div, 598a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div), 599c2526597SStephen Boyd .ops = &clk_rcg2_ops, 600c2526597SStephen Boyd }, 601c2526597SStephen Boyd }; 602c2526597SStephen Boyd 603c2526597SStephen Boyd static struct clk_rcg2 isense_clk_src = { 604c2526597SStephen Boyd .cmd_rcgr = 0x4010, 605c2526597SStephen Boyd .hid_width = 5, 606c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map, 607c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 608c2526597SStephen Boyd .name = "isense_clk_src", 609*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div, 610a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div), 611c2526597SStephen Boyd .ops = &clk_rcg2_ops, 612c2526597SStephen Boyd }, 613c2526597SStephen Boyd }; 614c2526597SStephen Boyd 615c2526597SStephen Boyd static const struct freq_tbl ftbl_rbcpr_clk_src[] = { 616c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 617c2526597SStephen Boyd F(50000000, P_GPLL0, 12, 0, 0), 618c2526597SStephen Boyd { } 619c2526597SStephen Boyd }; 620c2526597SStephen Boyd 621c2526597SStephen Boyd static struct clk_rcg2 rbcpr_clk_src = { 622c2526597SStephen Boyd .cmd_rcgr = 0x4060, 623c2526597SStephen Boyd .hid_width = 5, 624c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 625c2526597SStephen Boyd .freq_tbl = ftbl_rbcpr_clk_src, 626c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 627c2526597SStephen Boyd .name = "rbcpr_clk_src", 628*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div, 629a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div), 630c2526597SStephen Boyd .ops = &clk_rcg2_ops, 631c2526597SStephen Boyd }, 632c2526597SStephen Boyd }; 633c2526597SStephen Boyd 634c2526597SStephen Boyd static const struct freq_tbl ftbl_video_core_clk_src[] = { 635c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 636c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 637c2526597SStephen Boyd F(346666667, P_MMPLL3, 3, 0, 0), 638c2526597SStephen Boyd F(520000000, P_MMPLL3, 2, 0, 0), 639c2526597SStephen Boyd { } 640c2526597SStephen Boyd }; 641c2526597SStephen Boyd 642c2526597SStephen Boyd static struct clk_rcg2 video_core_clk_src = { 643c2526597SStephen Boyd .cmd_rcgr = 0x1000, 644c2526597SStephen Boyd .mnd_width = 8, 645c2526597SStephen Boyd .hid_width = 5, 646c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 647c2526597SStephen Boyd .freq_tbl = ftbl_video_core_clk_src, 648c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 649c2526597SStephen Boyd .name = "video_core_clk_src", 650*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 651a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div), 652c2526597SStephen Boyd .ops = &clk_rcg2_ops, 653c2526597SStephen Boyd }, 654c2526597SStephen Boyd }; 655c2526597SStephen Boyd 656c2526597SStephen Boyd static struct clk_rcg2 video_subcore0_clk_src = { 657c2526597SStephen Boyd .cmd_rcgr = 0x1060, 658c2526597SStephen Boyd .mnd_width = 8, 659c2526597SStephen Boyd .hid_width = 5, 660c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 661c2526597SStephen Boyd .freq_tbl = ftbl_video_core_clk_src, 662c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 663c2526597SStephen Boyd .name = "video_subcore0_clk_src", 664*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 665a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div), 666c2526597SStephen Boyd .ops = &clk_rcg2_ops, 667c2526597SStephen Boyd }, 668c2526597SStephen Boyd }; 669c2526597SStephen Boyd 670c2526597SStephen Boyd static struct clk_rcg2 video_subcore1_clk_src = { 671c2526597SStephen Boyd .cmd_rcgr = 0x1080, 672c2526597SStephen Boyd .mnd_width = 8, 673c2526597SStephen Boyd .hid_width = 5, 674c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 675c2526597SStephen Boyd .freq_tbl = ftbl_video_core_clk_src, 676c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 677c2526597SStephen Boyd .name = "video_subcore1_clk_src", 678*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 679a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div), 680c2526597SStephen Boyd .ops = &clk_rcg2_ops, 681c2526597SStephen Boyd }, 682c2526597SStephen Boyd }; 683c2526597SStephen Boyd 684c2526597SStephen Boyd static struct clk_rcg2 pclk0_clk_src = { 685c2526597SStephen Boyd .cmd_rcgr = 0x2000, 686c2526597SStephen Boyd .mnd_width = 8, 687c2526597SStephen Boyd .hid_width = 5, 688c2526597SStephen Boyd .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 689c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 690c2526597SStephen Boyd .name = "pclk0_clk_src", 691*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_dsi0pll_dsi1pll, 692a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll), 693c2526597SStephen Boyd .ops = &clk_pixel_ops, 694c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 695c2526597SStephen Boyd }, 696c2526597SStephen Boyd }; 697c2526597SStephen Boyd 698c2526597SStephen Boyd static struct clk_rcg2 pclk1_clk_src = { 699c2526597SStephen Boyd .cmd_rcgr = 0x2020, 700c2526597SStephen Boyd .mnd_width = 8, 701c2526597SStephen Boyd .hid_width = 5, 702c2526597SStephen Boyd .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 703c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 704c2526597SStephen Boyd .name = "pclk1_clk_src", 705*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_dsi0pll_dsi1pll, 706a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll), 707c2526597SStephen Boyd .ops = &clk_pixel_ops, 708c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 709c2526597SStephen Boyd }, 710c2526597SStephen Boyd }; 711c2526597SStephen Boyd 712c2526597SStephen Boyd static const struct freq_tbl ftbl_mdp_clk_src[] = { 713c2526597SStephen Boyd F(85714286, P_GPLL0, 7, 0, 0), 714c2526597SStephen Boyd F(100000000, P_GPLL0, 6, 0, 0), 715c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 716c2526597SStephen Boyd F(171428571, P_GPLL0, 3.5, 0, 0), 717c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 718c2526597SStephen Boyd F(275000000, P_MMPLL5, 3, 0, 0), 719c2526597SStephen Boyd F(300000000, P_GPLL0, 2, 0, 0), 720c2526597SStephen Boyd F(330000000, P_MMPLL5, 2.5, 0, 0), 721c2526597SStephen Boyd F(412500000, P_MMPLL5, 2, 0, 0), 722c2526597SStephen Boyd { } 723c2526597SStephen Boyd }; 724c2526597SStephen Boyd 725c2526597SStephen Boyd static struct clk_rcg2 mdp_clk_src = { 726c2526597SStephen Boyd .cmd_rcgr = 0x2040, 727c2526597SStephen Boyd .hid_width = 5, 728c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map, 729c2526597SStephen Boyd .freq_tbl = ftbl_mdp_clk_src, 730c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 731c2526597SStephen Boyd .name = "mdp_clk_src", 732*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, 733a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div), 734c2526597SStephen Boyd .ops = &clk_rcg2_ops, 735c2526597SStephen Boyd }, 736c2526597SStephen Boyd }; 737c2526597SStephen Boyd 738c2526597SStephen Boyd static struct freq_tbl extpclk_freq_tbl[] = { 739c2526597SStephen Boyd { .src = P_HDMIPLL }, 740c2526597SStephen Boyd { } 741c2526597SStephen Boyd }; 742c2526597SStephen Boyd 743c2526597SStephen Boyd static struct clk_rcg2 extpclk_clk_src = { 744c2526597SStephen Boyd .cmd_rcgr = 0x2060, 745c2526597SStephen Boyd .hid_width = 5, 746c2526597SStephen Boyd .parent_map = mmss_xo_hdmi_map, 747c2526597SStephen Boyd .freq_tbl = extpclk_freq_tbl, 748c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 749c2526597SStephen Boyd .name = "extpclk_clk_src", 750*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_hdmi, 751a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_hdmi), 752c2526597SStephen Boyd .ops = &clk_byte_ops, 753c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 754c2526597SStephen Boyd }, 755c2526597SStephen Boyd }; 756c2526597SStephen Boyd 757c2526597SStephen Boyd static struct freq_tbl ftbl_mdss_vsync_clk[] = { 758c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 759c2526597SStephen Boyd { } 760c2526597SStephen Boyd }; 761c2526597SStephen Boyd 762c2526597SStephen Boyd static struct clk_rcg2 vsync_clk_src = { 763c2526597SStephen Boyd .cmd_rcgr = 0x2080, 764c2526597SStephen Boyd .hid_width = 5, 765c2526597SStephen Boyd .parent_map = mmss_xo_gpll0_gpll0_div_map, 766c2526597SStephen Boyd .freq_tbl = ftbl_mdss_vsync_clk, 767c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 768c2526597SStephen Boyd .name = "vsync_clk_src", 769*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_gpll0_gpll0_div, 770a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div), 771c2526597SStephen Boyd .ops = &clk_rcg2_ops, 772c2526597SStephen Boyd }, 773c2526597SStephen Boyd }; 774c2526597SStephen Boyd 775c2526597SStephen Boyd static struct freq_tbl ftbl_mdss_hdmi_clk[] = { 776c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 777c2526597SStephen Boyd { } 778c2526597SStephen Boyd }; 779c2526597SStephen Boyd 780c2526597SStephen Boyd static struct clk_rcg2 hdmi_clk_src = { 781c2526597SStephen Boyd .cmd_rcgr = 0x2100, 782c2526597SStephen Boyd .hid_width = 5, 783c2526597SStephen Boyd .parent_map = mmss_xo_gpll0_gpll0_div_map, 784c2526597SStephen Boyd .freq_tbl = ftbl_mdss_hdmi_clk, 785c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 786c2526597SStephen Boyd .name = "hdmi_clk_src", 787*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_gpll0_gpll0_div, 788a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div), 789c2526597SStephen Boyd .ops = &clk_rcg2_ops, 790c2526597SStephen Boyd }, 791c2526597SStephen Boyd }; 792c2526597SStephen Boyd 793c2526597SStephen Boyd static struct clk_rcg2 byte0_clk_src = { 794c2526597SStephen Boyd .cmd_rcgr = 0x2120, 795c2526597SStephen Boyd .hid_width = 5, 796c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 797c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 798c2526597SStephen Boyd .name = "byte0_clk_src", 799*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_dsibyte, 800a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), 801c2526597SStephen Boyd .ops = &clk_byte2_ops, 802c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 803c2526597SStephen Boyd }, 804c2526597SStephen Boyd }; 805c2526597SStephen Boyd 806c2526597SStephen Boyd static struct clk_rcg2 byte1_clk_src = { 807c2526597SStephen Boyd .cmd_rcgr = 0x2140, 808c2526597SStephen Boyd .hid_width = 5, 809c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 810c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 811c2526597SStephen Boyd .name = "byte1_clk_src", 812*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_dsibyte, 813a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), 814c2526597SStephen Boyd .ops = &clk_byte2_ops, 815c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 816c2526597SStephen Boyd }, 817c2526597SStephen Boyd }; 818c2526597SStephen Boyd 819c2526597SStephen Boyd static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { 820c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 821c2526597SStephen Boyd { } 822c2526597SStephen Boyd }; 823c2526597SStephen Boyd 824c2526597SStephen Boyd static struct clk_rcg2 esc0_clk_src = { 825c2526597SStephen Boyd .cmd_rcgr = 0x2160, 826c2526597SStephen Boyd .hid_width = 5, 827c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 828c2526597SStephen Boyd .freq_tbl = ftbl_mdss_esc0_1_clk, 829c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 830c2526597SStephen Boyd .name = "esc0_clk_src", 831*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_dsibyte, 832a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), 833c2526597SStephen Boyd .ops = &clk_rcg2_ops, 834c2526597SStephen Boyd }, 835c2526597SStephen Boyd }; 836c2526597SStephen Boyd 837c2526597SStephen Boyd static struct clk_rcg2 esc1_clk_src = { 838c2526597SStephen Boyd .cmd_rcgr = 0x2180, 839c2526597SStephen Boyd .hid_width = 5, 840c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 841c2526597SStephen Boyd .freq_tbl = ftbl_mdss_esc0_1_clk, 842c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 843c2526597SStephen Boyd .name = "esc1_clk_src", 844*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_dsibyte, 845a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), 846c2526597SStephen Boyd .ops = &clk_rcg2_ops, 847c2526597SStephen Boyd }, 848c2526597SStephen Boyd }; 849c2526597SStephen Boyd 850c2526597SStephen Boyd static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { 851c2526597SStephen Boyd F(10000, P_XO, 16, 1, 120), 852c2526597SStephen Boyd F(24000, P_XO, 16, 1, 50), 853c2526597SStephen Boyd F(6000000, P_GPLL0_DIV, 10, 1, 5), 854c2526597SStephen Boyd F(12000000, P_GPLL0_DIV, 1, 1, 25), 855c2526597SStephen Boyd F(13000000, P_GPLL0_DIV, 2, 13, 150), 856c2526597SStephen Boyd F(24000000, P_GPLL0_DIV, 1, 2, 25), 857c2526597SStephen Boyd { } 858c2526597SStephen Boyd }; 859c2526597SStephen Boyd 860c2526597SStephen Boyd static struct clk_rcg2 camss_gp0_clk_src = { 861c2526597SStephen Boyd .cmd_rcgr = 0x3420, 862c2526597SStephen Boyd .mnd_width = 8, 863c2526597SStephen Boyd .hid_width = 5, 864c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 865c2526597SStephen Boyd .freq_tbl = ftbl_camss_gp0_clk_src, 866c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 867c2526597SStephen Boyd .name = "camss_gp0_clk_src", 868*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 869a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), 870c2526597SStephen Boyd .ops = &clk_rcg2_ops, 871c2526597SStephen Boyd }, 872c2526597SStephen Boyd }; 873c2526597SStephen Boyd 874c2526597SStephen Boyd static struct clk_rcg2 camss_gp1_clk_src = { 875c2526597SStephen Boyd .cmd_rcgr = 0x3450, 876c2526597SStephen Boyd .mnd_width = 8, 877c2526597SStephen Boyd .hid_width = 5, 878c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 879c2526597SStephen Boyd .freq_tbl = ftbl_camss_gp0_clk_src, 880c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 881c2526597SStephen Boyd .name = "camss_gp1_clk_src", 882*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 883a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), 884c2526597SStephen Boyd .ops = &clk_rcg2_ops, 885c2526597SStephen Boyd }, 886c2526597SStephen Boyd }; 887c2526597SStephen Boyd 888c2526597SStephen Boyd static const struct freq_tbl ftbl_mclk0_clk_src[] = { 889c2526597SStephen Boyd F(4800000, P_XO, 4, 0, 0), 890c2526597SStephen Boyd F(6000000, P_GPLL0_DIV, 10, 1, 5), 891c2526597SStephen Boyd F(8000000, P_GPLL0_DIV, 1, 2, 75), 892c2526597SStephen Boyd F(9600000, P_XO, 2, 0, 0), 893c2526597SStephen Boyd F(16666667, P_GPLL0_DIV, 2, 1, 9), 894c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 895c2526597SStephen Boyd F(24000000, P_GPLL0_DIV, 1, 2, 25), 896c2526597SStephen Boyd F(33333333, P_GPLL0_DIV, 1, 1, 9), 897c2526597SStephen Boyd F(48000000, P_GPLL0, 1, 2, 25), 898c2526597SStephen Boyd F(66666667, P_GPLL0, 1, 1, 9), 899c2526597SStephen Boyd { } 900c2526597SStephen Boyd }; 901c2526597SStephen Boyd 902c2526597SStephen Boyd static struct clk_rcg2 mclk0_clk_src = { 903c2526597SStephen Boyd .cmd_rcgr = 0x3360, 904c2526597SStephen Boyd .mnd_width = 8, 905c2526597SStephen Boyd .hid_width = 5, 906c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 907c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 908c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 909c2526597SStephen Boyd .name = "mclk0_clk_src", 910*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 911a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), 912c2526597SStephen Boyd .ops = &clk_rcg2_ops, 913c2526597SStephen Boyd }, 914c2526597SStephen Boyd }; 915c2526597SStephen Boyd 916c2526597SStephen Boyd static struct clk_rcg2 mclk1_clk_src = { 917c2526597SStephen Boyd .cmd_rcgr = 0x3390, 918c2526597SStephen Boyd .mnd_width = 8, 919c2526597SStephen Boyd .hid_width = 5, 920c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 921c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 922c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 923c2526597SStephen Boyd .name = "mclk1_clk_src", 924*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 925a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), 926c2526597SStephen Boyd .ops = &clk_rcg2_ops, 927c2526597SStephen Boyd }, 928c2526597SStephen Boyd }; 929c2526597SStephen Boyd 930c2526597SStephen Boyd static struct clk_rcg2 mclk2_clk_src = { 931c2526597SStephen Boyd .cmd_rcgr = 0x33c0, 932c2526597SStephen Boyd .mnd_width = 8, 933c2526597SStephen Boyd .hid_width = 5, 934c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 935c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 936c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 937c2526597SStephen Boyd .name = "mclk2_clk_src", 938*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 939a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), 940c2526597SStephen Boyd .ops = &clk_rcg2_ops, 941c2526597SStephen Boyd }, 942c2526597SStephen Boyd }; 943c2526597SStephen Boyd 944c2526597SStephen Boyd static struct clk_rcg2 mclk3_clk_src = { 945c2526597SStephen Boyd .cmd_rcgr = 0x33f0, 946c2526597SStephen Boyd .mnd_width = 8, 947c2526597SStephen Boyd .hid_width = 5, 948c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 949c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 950c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 951c2526597SStephen Boyd .name = "mclk3_clk_src", 952*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 953a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), 954c2526597SStephen Boyd .ops = &clk_rcg2_ops, 955c2526597SStephen Boyd }, 956c2526597SStephen Boyd }; 957c2526597SStephen Boyd 958c2526597SStephen Boyd static const struct freq_tbl ftbl_cci_clk_src[] = { 959c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 960c2526597SStephen Boyd F(37500000, P_GPLL0, 16, 0, 0), 961c2526597SStephen Boyd F(50000000, P_GPLL0, 12, 0, 0), 962c2526597SStephen Boyd F(100000000, P_GPLL0, 6, 0, 0), 963c2526597SStephen Boyd { } 964c2526597SStephen Boyd }; 965c2526597SStephen Boyd 966c2526597SStephen Boyd static struct clk_rcg2 cci_clk_src = { 967c2526597SStephen Boyd .cmd_rcgr = 0x3300, 968c2526597SStephen Boyd .mnd_width = 8, 969c2526597SStephen Boyd .hid_width = 5, 970c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 971c2526597SStephen Boyd .freq_tbl = ftbl_cci_clk_src, 972c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 973c2526597SStephen Boyd .name = "cci_clk_src", 974*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 975a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), 976c2526597SStephen Boyd .ops = &clk_rcg2_ops, 977c2526597SStephen Boyd }, 978c2526597SStephen Boyd }; 979c2526597SStephen Boyd 980c2526597SStephen Boyd static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { 981c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 982c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 983c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 984c2526597SStephen Boyd { } 985c2526597SStephen Boyd }; 986c2526597SStephen Boyd 987c2526597SStephen Boyd static struct clk_rcg2 csi0phytimer_clk_src = { 988c2526597SStephen Boyd .cmd_rcgr = 0x3000, 989c2526597SStephen Boyd .hid_width = 5, 990c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 991c2526597SStephen Boyd .freq_tbl = ftbl_csi0phytimer_clk_src, 992c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 993c2526597SStephen Boyd .name = "csi0phytimer_clk_src", 994*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 995a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 996c2526597SStephen Boyd .ops = &clk_rcg2_ops, 997c2526597SStephen Boyd }, 998c2526597SStephen Boyd }; 999c2526597SStephen Boyd 1000c2526597SStephen Boyd static struct clk_rcg2 csi1phytimer_clk_src = { 1001c2526597SStephen Boyd .cmd_rcgr = 0x3030, 1002c2526597SStephen Boyd .hid_width = 5, 1003c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1004c2526597SStephen Boyd .freq_tbl = ftbl_csi0phytimer_clk_src, 1005c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1006c2526597SStephen Boyd .name = "csi1phytimer_clk_src", 1007*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1008a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1009c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1010c2526597SStephen Boyd }, 1011c2526597SStephen Boyd }; 1012c2526597SStephen Boyd 1013c2526597SStephen Boyd static struct clk_rcg2 csi2phytimer_clk_src = { 1014c2526597SStephen Boyd .cmd_rcgr = 0x3060, 1015c2526597SStephen Boyd .hid_width = 5, 1016c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1017c2526597SStephen Boyd .freq_tbl = ftbl_csi0phytimer_clk_src, 1018c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1019c2526597SStephen Boyd .name = "csi2phytimer_clk_src", 1020*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1021a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1022c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1023c2526597SStephen Boyd }, 1024c2526597SStephen Boyd }; 1025c2526597SStephen Boyd 1026c2526597SStephen Boyd static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = { 1027c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1028c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1029c2526597SStephen Boyd F(320000000, P_MMPLL4, 3, 0, 0), 1030c2526597SStephen Boyd F(384000000, P_MMPLL4, 2.5, 0, 0), 1031c2526597SStephen Boyd { } 1032c2526597SStephen Boyd }; 1033c2526597SStephen Boyd 1034c2526597SStephen Boyd static struct clk_rcg2 csiphy0_3p_clk_src = { 1035c2526597SStephen Boyd .cmd_rcgr = 0x3240, 1036c2526597SStephen Boyd .hid_width = 5, 1037c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1038c2526597SStephen Boyd .freq_tbl = ftbl_csiphy0_3p_clk_src, 1039c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1040c2526597SStephen Boyd .name = "csiphy0_3p_clk_src", 1041*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1042a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1043c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1044c2526597SStephen Boyd }, 1045c2526597SStephen Boyd }; 1046c2526597SStephen Boyd 1047c2526597SStephen Boyd static struct clk_rcg2 csiphy1_3p_clk_src = { 1048c2526597SStephen Boyd .cmd_rcgr = 0x3260, 1049c2526597SStephen Boyd .hid_width = 5, 1050c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1051c2526597SStephen Boyd .freq_tbl = ftbl_csiphy0_3p_clk_src, 1052c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1053c2526597SStephen Boyd .name = "csiphy1_3p_clk_src", 1054*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1055a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1056c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1057c2526597SStephen Boyd }, 1058c2526597SStephen Boyd }; 1059c2526597SStephen Boyd 1060c2526597SStephen Boyd static struct clk_rcg2 csiphy2_3p_clk_src = { 1061c2526597SStephen Boyd .cmd_rcgr = 0x3280, 1062c2526597SStephen Boyd .hid_width = 5, 1063c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1064c2526597SStephen Boyd .freq_tbl = ftbl_csiphy0_3p_clk_src, 1065c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1066c2526597SStephen Boyd .name = "csiphy2_3p_clk_src", 1067*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1068a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1069c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1070c2526597SStephen Boyd }, 1071c2526597SStephen Boyd }; 1072c2526597SStephen Boyd 1073c2526597SStephen Boyd static const struct freq_tbl ftbl_jpeg0_clk_src[] = { 1074c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 1075c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 1076c2526597SStephen Boyd F(228571429, P_MMPLL0, 3.5, 0, 0), 1077c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 1078c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1079c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1080c2526597SStephen Boyd { } 1081c2526597SStephen Boyd }; 1082c2526597SStephen Boyd 1083c2526597SStephen Boyd static struct clk_rcg2 jpeg0_clk_src = { 1084c2526597SStephen Boyd .cmd_rcgr = 0x3500, 1085c2526597SStephen Boyd .hid_width = 5, 1086c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1087c2526597SStephen Boyd .freq_tbl = ftbl_jpeg0_clk_src, 1088c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1089c2526597SStephen Boyd .name = "jpeg0_clk_src", 1090*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1091a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1092c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1093c2526597SStephen Boyd }, 1094c2526597SStephen Boyd }; 1095c2526597SStephen Boyd 1096c2526597SStephen Boyd static const struct freq_tbl ftbl_jpeg2_clk_src[] = { 1097c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 1098c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 1099c2526597SStephen Boyd F(228571429, P_MMPLL0, 3.5, 0, 0), 1100c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 1101c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1102c2526597SStephen Boyd { } 1103c2526597SStephen Boyd }; 1104c2526597SStephen Boyd 1105c2526597SStephen Boyd static struct clk_rcg2 jpeg2_clk_src = { 1106c2526597SStephen Boyd .cmd_rcgr = 0x3540, 1107c2526597SStephen Boyd .hid_width = 5, 1108c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1109c2526597SStephen Boyd .freq_tbl = ftbl_jpeg2_clk_src, 1110c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1111c2526597SStephen Boyd .name = "jpeg2_clk_src", 1112*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1113a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1114c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1115c2526597SStephen Boyd }, 1116c2526597SStephen Boyd }; 1117c2526597SStephen Boyd 1118c2526597SStephen Boyd static struct clk_rcg2 jpeg_dma_clk_src = { 1119c2526597SStephen Boyd .cmd_rcgr = 0x3560, 1120c2526597SStephen Boyd .hid_width = 5, 1121c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1122c2526597SStephen Boyd .freq_tbl = ftbl_jpeg0_clk_src, 1123c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1124c2526597SStephen Boyd .name = "jpeg_dma_clk_src", 1125*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1126a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1127c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1128c2526597SStephen Boyd }, 1129c2526597SStephen Boyd }; 1130c2526597SStephen Boyd 1131c2526597SStephen Boyd static const struct freq_tbl ftbl_vfe0_clk_src[] = { 1132c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 1133c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1134c2526597SStephen Boyd F(300000000, P_GPLL0, 2, 0, 0), 1135c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1136c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1137c2526597SStephen Boyd F(600000000, P_GPLL0, 1, 0, 0), 1138c2526597SStephen Boyd { } 1139c2526597SStephen Boyd }; 1140c2526597SStephen Boyd 1141c2526597SStephen Boyd static struct clk_rcg2 vfe0_clk_src = { 1142c2526597SStephen Boyd .cmd_rcgr = 0x3600, 1143c2526597SStephen Boyd .hid_width = 5, 1144c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1145c2526597SStephen Boyd .freq_tbl = ftbl_vfe0_clk_src, 1146c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1147c2526597SStephen Boyd .name = "vfe0_clk_src", 1148*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1149a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1150c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1151c2526597SStephen Boyd }, 1152c2526597SStephen Boyd }; 1153c2526597SStephen Boyd 1154c2526597SStephen Boyd static struct clk_rcg2 vfe1_clk_src = { 1155c2526597SStephen Boyd .cmd_rcgr = 0x3620, 1156c2526597SStephen Boyd .hid_width = 5, 1157c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1158c2526597SStephen Boyd .freq_tbl = ftbl_vfe0_clk_src, 1159c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1160c2526597SStephen Boyd .name = "vfe1_clk_src", 1161*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1162a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1163c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1164c2526597SStephen Boyd }, 1165c2526597SStephen Boyd }; 1166c2526597SStephen Boyd 1167c2526597SStephen Boyd static const struct freq_tbl ftbl_cpp_clk_src[] = { 1168c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1169c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1170c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1171c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1172c2526597SStephen Boyd F(640000000, P_MMPLL4, 1.5, 0, 0), 1173c2526597SStephen Boyd { } 1174c2526597SStephen Boyd }; 1175c2526597SStephen Boyd 1176c2526597SStephen Boyd static struct clk_rcg2 cpp_clk_src = { 1177c2526597SStephen Boyd .cmd_rcgr = 0x3640, 1178c2526597SStephen Boyd .hid_width = 5, 1179c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1180c2526597SStephen Boyd .freq_tbl = ftbl_cpp_clk_src, 1181c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1182c2526597SStephen Boyd .name = "cpp_clk_src", 1183*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1184a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1185c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1186c2526597SStephen Boyd }, 1187c2526597SStephen Boyd }; 1188c2526597SStephen Boyd 1189c2526597SStephen Boyd static const struct freq_tbl ftbl_csi0_clk_src[] = { 1190c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1191c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1192c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 1193c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1194c2526597SStephen Boyd F(600000000, P_GPLL0, 1, 0, 0), 1195c2526597SStephen Boyd { } 1196c2526597SStephen Boyd }; 1197c2526597SStephen Boyd 1198c2526597SStephen Boyd static struct clk_rcg2 csi0_clk_src = { 1199c2526597SStephen Boyd .cmd_rcgr = 0x3090, 1200c2526597SStephen Boyd .hid_width = 5, 1201c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1202c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1203c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1204c2526597SStephen Boyd .name = "csi0_clk_src", 1205*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1206a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1207c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1208c2526597SStephen Boyd }, 1209c2526597SStephen Boyd }; 1210c2526597SStephen Boyd 1211c2526597SStephen Boyd static struct clk_rcg2 csi1_clk_src = { 1212c2526597SStephen Boyd .cmd_rcgr = 0x3100, 1213c2526597SStephen Boyd .hid_width = 5, 1214c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1215c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1216c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1217c2526597SStephen Boyd .name = "csi1_clk_src", 1218*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1219a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1220c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1221c2526597SStephen Boyd }, 1222c2526597SStephen Boyd }; 1223c2526597SStephen Boyd 1224c2526597SStephen Boyd static struct clk_rcg2 csi2_clk_src = { 1225c2526597SStephen Boyd .cmd_rcgr = 0x3160, 1226c2526597SStephen Boyd .hid_width = 5, 1227c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1228c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1229c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1230c2526597SStephen Boyd .name = "csi2_clk_src", 1231*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1232a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1233c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1234c2526597SStephen Boyd }, 1235c2526597SStephen Boyd }; 1236c2526597SStephen Boyd 1237c2526597SStephen Boyd static struct clk_rcg2 csi3_clk_src = { 1238c2526597SStephen Boyd .cmd_rcgr = 0x31c0, 1239c2526597SStephen Boyd .hid_width = 5, 1240c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1241c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1242c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1243c2526597SStephen Boyd .name = "csi3_clk_src", 1244*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1245a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), 1246c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1247c2526597SStephen Boyd }, 1248c2526597SStephen Boyd }; 1249c2526597SStephen Boyd 1250c2526597SStephen Boyd static const struct freq_tbl ftbl_fd_core_clk_src[] = { 1251c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1252c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1253c2526597SStephen Boyd F(400000000, P_MMPLL0, 2, 0, 0), 1254c2526597SStephen Boyd { } 1255c2526597SStephen Boyd }; 1256c2526597SStephen Boyd 1257c2526597SStephen Boyd static struct clk_rcg2 fd_core_clk_src = { 1258c2526597SStephen Boyd .cmd_rcgr = 0x3b00, 1259c2526597SStephen Boyd .hid_width = 5, 1260c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 1261c2526597SStephen Boyd .freq_tbl = ftbl_fd_core_clk_src, 1262c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1263c2526597SStephen Boyd .name = "fd_core_clk_src", 1264*e7c65912SDmitry Baryshkov .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 1265a7a4fc94SDmitry Baryshkov .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), 1266c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1267c2526597SStephen Boyd }, 1268c2526597SStephen Boyd }; 1269c2526597SStephen Boyd 1270c2526597SStephen Boyd static struct clk_branch mmss_mmagic_ahb_clk = { 1271c2526597SStephen Boyd .halt_reg = 0x5024, 1272c2526597SStephen Boyd .clkr = { 1273c2526597SStephen Boyd .enable_reg = 0x5024, 1274c2526597SStephen Boyd .enable_mask = BIT(0), 1275c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1276c2526597SStephen Boyd .name = "mmss_mmagic_ahb_clk", 1277*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1278*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1279*e7c65912SDmitry Baryshkov }, 1280c2526597SStephen Boyd .num_parents = 1, 12817705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1282c2526597SStephen Boyd .ops = &clk_branch2_ops, 1283c2526597SStephen Boyd }, 1284c2526597SStephen Boyd }, 1285c2526597SStephen Boyd }; 1286c2526597SStephen Boyd 1287c2526597SStephen Boyd static struct clk_branch mmss_mmagic_cfg_ahb_clk = { 1288c2526597SStephen Boyd .halt_reg = 0x5054, 1289c2526597SStephen Boyd .clkr = { 1290c2526597SStephen Boyd .enable_reg = 0x5054, 1291c2526597SStephen Boyd .enable_mask = BIT(0), 1292c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1293c2526597SStephen Boyd .name = "mmss_mmagic_cfg_ahb_clk", 1294*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1295*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1296*e7c65912SDmitry Baryshkov }, 1297c2526597SStephen Boyd .num_parents = 1, 12987705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1299c2526597SStephen Boyd .ops = &clk_branch2_ops, 1300c2526597SStephen Boyd }, 1301c2526597SStephen Boyd }, 1302c2526597SStephen Boyd }; 1303c2526597SStephen Boyd 1304c2526597SStephen Boyd static struct clk_branch mmss_misc_ahb_clk = { 1305c2526597SStephen Boyd .halt_reg = 0x5018, 1306c2526597SStephen Boyd .clkr = { 1307c2526597SStephen Boyd .enable_reg = 0x5018, 1308c2526597SStephen Boyd .enable_mask = BIT(0), 1309c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1310c2526597SStephen Boyd .name = "mmss_misc_ahb_clk", 1311*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1312*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1313*e7c65912SDmitry Baryshkov }, 1314c2526597SStephen Boyd .num_parents = 1, 1315c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1316c2526597SStephen Boyd .ops = &clk_branch2_ops, 1317c2526597SStephen Boyd }, 1318c2526597SStephen Boyd }, 1319c2526597SStephen Boyd }; 1320c2526597SStephen Boyd 1321c2526597SStephen Boyd static struct clk_branch mmss_misc_cxo_clk = { 1322c2526597SStephen Boyd .halt_reg = 0x5014, 1323c2526597SStephen Boyd .clkr = { 1324c2526597SStephen Boyd .enable_reg = 0x5014, 1325c2526597SStephen Boyd .enable_mask = BIT(0), 1326c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1327c2526597SStephen Boyd .name = "mmss_misc_cxo_clk", 1328*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 1329*e7c65912SDmitry Baryshkov { .fw_name = "xo", .name = "xo_board" }, 1330*e7c65912SDmitry Baryshkov }, 1331c2526597SStephen Boyd .num_parents = 1, 1332c2526597SStephen Boyd .ops = &clk_branch2_ops, 1333c2526597SStephen Boyd }, 1334c2526597SStephen Boyd }, 1335c2526597SStephen Boyd }; 1336c2526597SStephen Boyd 1337c2526597SStephen Boyd static struct clk_branch mmss_mmagic_maxi_clk = { 1338c2526597SStephen Boyd .halt_reg = 0x5074, 1339c2526597SStephen Boyd .clkr = { 1340c2526597SStephen Boyd .enable_reg = 0x5074, 1341c2526597SStephen Boyd .enable_mask = BIT(0), 1342c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1343c2526597SStephen Boyd .name = "mmss_mmagic_maxi_clk", 1344*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1345*e7c65912SDmitry Baryshkov &maxi_clk_src.clkr.hw 1346*e7c65912SDmitry Baryshkov }, 1347c2526597SStephen Boyd .num_parents = 1, 1348c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1349c2526597SStephen Boyd .ops = &clk_branch2_ops, 1350c2526597SStephen Boyd }, 1351c2526597SStephen Boyd }, 1352c2526597SStephen Boyd }; 1353c2526597SStephen Boyd 1354c2526597SStephen Boyd static struct clk_branch mmagic_camss_axi_clk = { 1355c2526597SStephen Boyd .halt_reg = 0x3c44, 1356c2526597SStephen Boyd .clkr = { 1357c2526597SStephen Boyd .enable_reg = 0x3c44, 1358c2526597SStephen Boyd .enable_mask = BIT(0), 1359c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1360c2526597SStephen Boyd .name = "mmagic_camss_axi_clk", 1361*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1362*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 1363*e7c65912SDmitry Baryshkov }, 1364c2526597SStephen Boyd .num_parents = 1, 13657705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1366c2526597SStephen Boyd .ops = &clk_branch2_ops, 1367c2526597SStephen Boyd }, 1368c2526597SStephen Boyd }, 1369c2526597SStephen Boyd }; 1370c2526597SStephen Boyd 1371c2526597SStephen Boyd static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = { 1372c2526597SStephen Boyd .halt_reg = 0x3c48, 1373c2526597SStephen Boyd .clkr = { 1374c2526597SStephen Boyd .enable_reg = 0x3c48, 1375c2526597SStephen Boyd .enable_mask = BIT(0), 1376c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1377c2526597SStephen Boyd .name = "mmagic_camss_noc_cfg_ahb_clk", 1378*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 1379*e7c65912SDmitry Baryshkov { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" }, 1380*e7c65912SDmitry Baryshkov }, 1381c2526597SStephen Boyd .num_parents = 1, 13827705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1383c2526597SStephen Boyd .ops = &clk_branch2_ops, 1384c2526597SStephen Boyd }, 1385c2526597SStephen Boyd }, 1386c2526597SStephen Boyd }; 1387c2526597SStephen Boyd 1388c2526597SStephen Boyd static struct clk_branch smmu_vfe_ahb_clk = { 1389c2526597SStephen Boyd .halt_reg = 0x3c04, 1390c2526597SStephen Boyd .clkr = { 1391c2526597SStephen Boyd .enable_reg = 0x3c04, 1392c2526597SStephen Boyd .enable_mask = BIT(0), 1393c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1394c2526597SStephen Boyd .name = "smmu_vfe_ahb_clk", 1395*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1396*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1397*e7c65912SDmitry Baryshkov }, 1398c2526597SStephen Boyd .num_parents = 1, 1399c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1400c2526597SStephen Boyd .ops = &clk_branch2_ops, 1401c2526597SStephen Boyd }, 1402c2526597SStephen Boyd }, 1403c2526597SStephen Boyd }; 1404c2526597SStephen Boyd 1405c2526597SStephen Boyd static struct clk_branch smmu_vfe_axi_clk = { 1406c2526597SStephen Boyd .halt_reg = 0x3c08, 1407c2526597SStephen Boyd .clkr = { 1408c2526597SStephen Boyd .enable_reg = 0x3c08, 1409c2526597SStephen Boyd .enable_mask = BIT(0), 1410c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1411c2526597SStephen Boyd .name = "smmu_vfe_axi_clk", 1412*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1413*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 1414*e7c65912SDmitry Baryshkov }, 1415c2526597SStephen Boyd .num_parents = 1, 1416c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1417c2526597SStephen Boyd .ops = &clk_branch2_ops, 1418c2526597SStephen Boyd }, 1419c2526597SStephen Boyd }, 1420c2526597SStephen Boyd }; 1421c2526597SStephen Boyd 1422c2526597SStephen Boyd static struct clk_branch smmu_cpp_ahb_clk = { 1423c2526597SStephen Boyd .halt_reg = 0x3c14, 1424c2526597SStephen Boyd .clkr = { 1425c2526597SStephen Boyd .enable_reg = 0x3c14, 1426c2526597SStephen Boyd .enable_mask = BIT(0), 1427c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1428c2526597SStephen Boyd .name = "smmu_cpp_ahb_clk", 1429*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1430*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1431*e7c65912SDmitry Baryshkov }, 1432c2526597SStephen Boyd .num_parents = 1, 1433c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1434c2526597SStephen Boyd .ops = &clk_branch2_ops, 1435c2526597SStephen Boyd }, 1436c2526597SStephen Boyd }, 1437c2526597SStephen Boyd }; 1438c2526597SStephen Boyd 1439c2526597SStephen Boyd static struct clk_branch smmu_cpp_axi_clk = { 1440c2526597SStephen Boyd .halt_reg = 0x3c18, 1441c2526597SStephen Boyd .clkr = { 1442c2526597SStephen Boyd .enable_reg = 0x3c18, 1443c2526597SStephen Boyd .enable_mask = BIT(0), 1444c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1445c2526597SStephen Boyd .name = "smmu_cpp_axi_clk", 1446*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1447*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 1448*e7c65912SDmitry Baryshkov }, 1449c2526597SStephen Boyd .num_parents = 1, 1450c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1451c2526597SStephen Boyd .ops = &clk_branch2_ops, 1452c2526597SStephen Boyd }, 1453c2526597SStephen Boyd }, 1454c2526597SStephen Boyd }; 1455c2526597SStephen Boyd 1456c2526597SStephen Boyd static struct clk_branch smmu_jpeg_ahb_clk = { 1457c2526597SStephen Boyd .halt_reg = 0x3c24, 1458c2526597SStephen Boyd .clkr = { 1459c2526597SStephen Boyd .enable_reg = 0x3c24, 1460c2526597SStephen Boyd .enable_mask = BIT(0), 1461c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1462c2526597SStephen Boyd .name = "smmu_jpeg_ahb_clk", 1463*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1464*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1465*e7c65912SDmitry Baryshkov }, 1466c2526597SStephen Boyd .num_parents = 1, 1467c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1468c2526597SStephen Boyd .ops = &clk_branch2_ops, 1469c2526597SStephen Boyd }, 1470c2526597SStephen Boyd }, 1471c2526597SStephen Boyd }; 1472c2526597SStephen Boyd 1473c2526597SStephen Boyd static struct clk_branch smmu_jpeg_axi_clk = { 1474c2526597SStephen Boyd .halt_reg = 0x3c28, 1475c2526597SStephen Boyd .clkr = { 1476c2526597SStephen Boyd .enable_reg = 0x3c28, 1477c2526597SStephen Boyd .enable_mask = BIT(0), 1478c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1479c2526597SStephen Boyd .name = "smmu_jpeg_axi_clk", 1480*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1481*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 1482*e7c65912SDmitry Baryshkov }, 1483c2526597SStephen Boyd .num_parents = 1, 1484c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1485c2526597SStephen Boyd .ops = &clk_branch2_ops, 1486c2526597SStephen Boyd }, 1487c2526597SStephen Boyd }, 1488c2526597SStephen Boyd }; 1489c2526597SStephen Boyd 1490c2526597SStephen Boyd static struct clk_branch mmagic_mdss_axi_clk = { 1491c2526597SStephen Boyd .halt_reg = 0x2474, 1492c2526597SStephen Boyd .clkr = { 1493c2526597SStephen Boyd .enable_reg = 0x2474, 1494c2526597SStephen Boyd .enable_mask = BIT(0), 1495c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1496c2526597SStephen Boyd .name = "mmagic_mdss_axi_clk", 1497*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1498*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 1499*e7c65912SDmitry Baryshkov }, 1500c2526597SStephen Boyd .num_parents = 1, 15017705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1502c2526597SStephen Boyd .ops = &clk_branch2_ops, 1503c2526597SStephen Boyd }, 1504c2526597SStephen Boyd }, 1505c2526597SStephen Boyd }; 1506c2526597SStephen Boyd 1507c2526597SStephen Boyd static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = { 1508c2526597SStephen Boyd .halt_reg = 0x2478, 1509c2526597SStephen Boyd .clkr = { 1510c2526597SStephen Boyd .enable_reg = 0x2478, 1511c2526597SStephen Boyd .enable_mask = BIT(0), 1512c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1513c2526597SStephen Boyd .name = "mmagic_mdss_noc_cfg_ahb_clk", 1514*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 1515*e7c65912SDmitry Baryshkov { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" }, 1516*e7c65912SDmitry Baryshkov }, 1517c2526597SStephen Boyd .num_parents = 1, 15187705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1519c2526597SStephen Boyd .ops = &clk_branch2_ops, 1520c2526597SStephen Boyd }, 1521c2526597SStephen Boyd }, 1522c2526597SStephen Boyd }; 1523c2526597SStephen Boyd 1524c2526597SStephen Boyd static struct clk_branch smmu_rot_ahb_clk = { 1525c2526597SStephen Boyd .halt_reg = 0x2444, 1526c2526597SStephen Boyd .clkr = { 1527c2526597SStephen Boyd .enable_reg = 0x2444, 1528c2526597SStephen Boyd .enable_mask = BIT(0), 1529c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1530c2526597SStephen Boyd .name = "smmu_rot_ahb_clk", 1531*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1532*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1533*e7c65912SDmitry Baryshkov }, 1534c2526597SStephen Boyd .num_parents = 1, 1535c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1536c2526597SStephen Boyd .ops = &clk_branch2_ops, 1537c2526597SStephen Boyd }, 1538c2526597SStephen Boyd }, 1539c2526597SStephen Boyd }; 1540c2526597SStephen Boyd 1541c2526597SStephen Boyd static struct clk_branch smmu_rot_axi_clk = { 1542c2526597SStephen Boyd .halt_reg = 0x2448, 1543c2526597SStephen Boyd .clkr = { 1544c2526597SStephen Boyd .enable_reg = 0x2448, 1545c2526597SStephen Boyd .enable_mask = BIT(0), 1546c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1547c2526597SStephen Boyd .name = "smmu_rot_axi_clk", 1548*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1549*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 1550*e7c65912SDmitry Baryshkov }, 1551c2526597SStephen Boyd .num_parents = 1, 1552c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1553c2526597SStephen Boyd .ops = &clk_branch2_ops, 1554c2526597SStephen Boyd }, 1555c2526597SStephen Boyd }, 1556c2526597SStephen Boyd }; 1557c2526597SStephen Boyd 1558c2526597SStephen Boyd static struct clk_branch smmu_mdp_ahb_clk = { 1559c2526597SStephen Boyd .halt_reg = 0x2454, 1560c2526597SStephen Boyd .clkr = { 1561c2526597SStephen Boyd .enable_reg = 0x2454, 1562c2526597SStephen Boyd .enable_mask = BIT(0), 1563c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1564c2526597SStephen Boyd .name = "smmu_mdp_ahb_clk", 1565*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1566*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1567*e7c65912SDmitry Baryshkov }, 1568c2526597SStephen Boyd .num_parents = 1, 1569c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1570c2526597SStephen Boyd .ops = &clk_branch2_ops, 1571c2526597SStephen Boyd }, 1572c2526597SStephen Boyd }, 1573c2526597SStephen Boyd }; 1574c2526597SStephen Boyd 1575c2526597SStephen Boyd static struct clk_branch smmu_mdp_axi_clk = { 1576c2526597SStephen Boyd .halt_reg = 0x2458, 1577c2526597SStephen Boyd .clkr = { 1578c2526597SStephen Boyd .enable_reg = 0x2458, 1579c2526597SStephen Boyd .enable_mask = BIT(0), 1580c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1581c2526597SStephen Boyd .name = "smmu_mdp_axi_clk", 1582*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1583*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 1584*e7c65912SDmitry Baryshkov }, 1585c2526597SStephen Boyd .num_parents = 1, 1586c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1587c2526597SStephen Boyd .ops = &clk_branch2_ops, 1588c2526597SStephen Boyd }, 1589c2526597SStephen Boyd }, 1590c2526597SStephen Boyd }; 1591c2526597SStephen Boyd 1592c2526597SStephen Boyd static struct clk_branch mmagic_video_axi_clk = { 1593c2526597SStephen Boyd .halt_reg = 0x1194, 1594c2526597SStephen Boyd .clkr = { 1595c2526597SStephen Boyd .enable_reg = 0x1194, 1596c2526597SStephen Boyd .enable_mask = BIT(0), 1597c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1598c2526597SStephen Boyd .name = "mmagic_video_axi_clk", 1599*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1600*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 1601*e7c65912SDmitry Baryshkov }, 1602c2526597SStephen Boyd .num_parents = 1, 16037705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1604c2526597SStephen Boyd .ops = &clk_branch2_ops, 1605c2526597SStephen Boyd }, 1606c2526597SStephen Boyd }, 1607c2526597SStephen Boyd }; 1608c2526597SStephen Boyd 1609c2526597SStephen Boyd static struct clk_branch mmagic_video_noc_cfg_ahb_clk = { 1610c2526597SStephen Boyd .halt_reg = 0x1198, 1611c2526597SStephen Boyd .clkr = { 1612c2526597SStephen Boyd .enable_reg = 0x1198, 1613c2526597SStephen Boyd .enable_mask = BIT(0), 1614c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1615c2526597SStephen Boyd .name = "mmagic_video_noc_cfg_ahb_clk", 1616*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 1617*e7c65912SDmitry Baryshkov { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" }, 1618*e7c65912SDmitry Baryshkov }, 1619c2526597SStephen Boyd .num_parents = 1, 16207705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1621c2526597SStephen Boyd .ops = &clk_branch2_ops, 1622c2526597SStephen Boyd }, 1623c2526597SStephen Boyd }, 1624c2526597SStephen Boyd }; 1625c2526597SStephen Boyd 1626c2526597SStephen Boyd static struct clk_branch smmu_video_ahb_clk = { 1627c2526597SStephen Boyd .halt_reg = 0x1174, 1628c2526597SStephen Boyd .clkr = { 1629c2526597SStephen Boyd .enable_reg = 0x1174, 1630c2526597SStephen Boyd .enable_mask = BIT(0), 1631c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1632c2526597SStephen Boyd .name = "smmu_video_ahb_clk", 1633*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1634*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1635*e7c65912SDmitry Baryshkov }, 1636c2526597SStephen Boyd .num_parents = 1, 1637c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1638c2526597SStephen Boyd .ops = &clk_branch2_ops, 1639c2526597SStephen Boyd }, 1640c2526597SStephen Boyd }, 1641c2526597SStephen Boyd }; 1642c2526597SStephen Boyd 1643c2526597SStephen Boyd static struct clk_branch smmu_video_axi_clk = { 1644c2526597SStephen Boyd .halt_reg = 0x1178, 1645c2526597SStephen Boyd .clkr = { 1646c2526597SStephen Boyd .enable_reg = 0x1178, 1647c2526597SStephen Boyd .enable_mask = BIT(0), 1648c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1649c2526597SStephen Boyd .name = "smmu_video_axi_clk", 1650*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1651*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 1652*e7c65912SDmitry Baryshkov }, 1653c2526597SStephen Boyd .num_parents = 1, 1654c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1655c2526597SStephen Boyd .ops = &clk_branch2_ops, 1656c2526597SStephen Boyd }, 1657c2526597SStephen Boyd }, 1658c2526597SStephen Boyd }; 1659c2526597SStephen Boyd 1660c2526597SStephen Boyd static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { 1661c2526597SStephen Boyd .halt_reg = 0x5298, 1662c2526597SStephen Boyd .clkr = { 1663c2526597SStephen Boyd .enable_reg = 0x5298, 1664c2526597SStephen Boyd .enable_mask = BIT(0), 1665c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1666c2526597SStephen Boyd .name = "mmagic_bimc_noc_cfg_ahb_clk", 1667*e7c65912SDmitry Baryshkov .parent_data = (const struct clk_parent_data[]){ 1668*e7c65912SDmitry Baryshkov { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" }, 1669*e7c65912SDmitry Baryshkov }, 1670c2526597SStephen Boyd .num_parents = 1, 1671c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1672c2526597SStephen Boyd .ops = &clk_branch2_ops, 1673c2526597SStephen Boyd }, 1674c2526597SStephen Boyd }, 1675c2526597SStephen Boyd }; 1676c2526597SStephen Boyd 1677c2526597SStephen Boyd static struct clk_branch gpu_gx_gfx3d_clk = { 1678c2526597SStephen Boyd .halt_reg = 0x4028, 1679c2526597SStephen Boyd .clkr = { 1680c2526597SStephen Boyd .enable_reg = 0x4028, 1681c2526597SStephen Boyd .enable_mask = BIT(0), 1682c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1683c2526597SStephen Boyd .name = "gpu_gx_gfx3d_clk", 1684*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1685*e7c65912SDmitry Baryshkov &gfx3d_clk_src.rcg.clkr.hw 1686*e7c65912SDmitry Baryshkov }, 1687c2526597SStephen Boyd .num_parents = 1, 1688c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1689c2526597SStephen Boyd .ops = &clk_branch2_ops, 1690c2526597SStephen Boyd }, 1691c2526597SStephen Boyd }, 1692c2526597SStephen Boyd }; 1693c2526597SStephen Boyd 1694c2526597SStephen Boyd static struct clk_branch gpu_gx_rbbmtimer_clk = { 1695c2526597SStephen Boyd .halt_reg = 0x40b0, 1696c2526597SStephen Boyd .clkr = { 1697c2526597SStephen Boyd .enable_reg = 0x40b0, 1698c2526597SStephen Boyd .enable_mask = BIT(0), 1699c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1700c2526597SStephen Boyd .name = "gpu_gx_rbbmtimer_clk", 1701*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1702*e7c65912SDmitry Baryshkov &rbbmtimer_clk_src.clkr.hw 1703*e7c65912SDmitry Baryshkov }, 1704c2526597SStephen Boyd .num_parents = 1, 1705c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1706c2526597SStephen Boyd .ops = &clk_branch2_ops, 1707c2526597SStephen Boyd }, 1708c2526597SStephen Boyd }, 1709c2526597SStephen Boyd }; 1710c2526597SStephen Boyd 1711c2526597SStephen Boyd static struct clk_branch gpu_ahb_clk = { 1712c2526597SStephen Boyd .halt_reg = 0x403c, 1713c2526597SStephen Boyd .clkr = { 1714c2526597SStephen Boyd .enable_reg = 0x403c, 1715c2526597SStephen Boyd .enable_mask = BIT(0), 1716c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1717c2526597SStephen Boyd .name = "gpu_ahb_clk", 1718*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1719*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1720*e7c65912SDmitry Baryshkov }, 1721c2526597SStephen Boyd .num_parents = 1, 1722c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1723c2526597SStephen Boyd .ops = &clk_branch2_ops, 1724c2526597SStephen Boyd }, 1725c2526597SStephen Boyd }, 1726c2526597SStephen Boyd }; 1727c2526597SStephen Boyd 1728c2526597SStephen Boyd static struct clk_branch gpu_aon_isense_clk = { 1729c2526597SStephen Boyd .halt_reg = 0x4044, 1730c2526597SStephen Boyd .clkr = { 1731c2526597SStephen Boyd .enable_reg = 0x4044, 1732c2526597SStephen Boyd .enable_mask = BIT(0), 1733c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1734c2526597SStephen Boyd .name = "gpu_aon_isense_clk", 1735*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1736*e7c65912SDmitry Baryshkov &isense_clk_src.clkr.hw 1737*e7c65912SDmitry Baryshkov }, 1738c2526597SStephen Boyd .num_parents = 1, 1739c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1740c2526597SStephen Boyd .ops = &clk_branch2_ops, 1741c2526597SStephen Boyd }, 1742c2526597SStephen Boyd }, 1743c2526597SStephen Boyd }; 1744c2526597SStephen Boyd 1745c2526597SStephen Boyd static struct clk_branch vmem_maxi_clk = { 1746c2526597SStephen Boyd .halt_reg = 0x1204, 1747c2526597SStephen Boyd .clkr = { 1748c2526597SStephen Boyd .enable_reg = 0x1204, 1749c2526597SStephen Boyd .enable_mask = BIT(0), 1750c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1751c2526597SStephen Boyd .name = "vmem_maxi_clk", 1752*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1753*e7c65912SDmitry Baryshkov &maxi_clk_src.clkr.hw 1754*e7c65912SDmitry Baryshkov }, 1755c2526597SStephen Boyd .num_parents = 1, 1756c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1757c2526597SStephen Boyd .ops = &clk_branch2_ops, 1758c2526597SStephen Boyd }, 1759c2526597SStephen Boyd }, 1760c2526597SStephen Boyd }; 1761c2526597SStephen Boyd 1762c2526597SStephen Boyd static struct clk_branch vmem_ahb_clk = { 1763c2526597SStephen Boyd .halt_reg = 0x1208, 1764c2526597SStephen Boyd .clkr = { 1765c2526597SStephen Boyd .enable_reg = 0x1208, 1766c2526597SStephen Boyd .enable_mask = BIT(0), 1767c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1768c2526597SStephen Boyd .name = "vmem_ahb_clk", 1769*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1770*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1771*e7c65912SDmitry Baryshkov }, 1772c2526597SStephen Boyd .num_parents = 1, 1773c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1774c2526597SStephen Boyd .ops = &clk_branch2_ops, 1775c2526597SStephen Boyd }, 1776c2526597SStephen Boyd }, 1777c2526597SStephen Boyd }; 1778c2526597SStephen Boyd 1779c2526597SStephen Boyd static struct clk_branch mmss_rbcpr_clk = { 1780c2526597SStephen Boyd .halt_reg = 0x4084, 1781c2526597SStephen Boyd .clkr = { 1782c2526597SStephen Boyd .enable_reg = 0x4084, 1783c2526597SStephen Boyd .enable_mask = BIT(0), 1784c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1785c2526597SStephen Boyd .name = "mmss_rbcpr_clk", 1786*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1787*e7c65912SDmitry Baryshkov &rbcpr_clk_src.clkr.hw 1788*e7c65912SDmitry Baryshkov }, 1789c2526597SStephen Boyd .num_parents = 1, 1790c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1791c2526597SStephen Boyd .ops = &clk_branch2_ops, 1792c2526597SStephen Boyd }, 1793c2526597SStephen Boyd }, 1794c2526597SStephen Boyd }; 1795c2526597SStephen Boyd 1796c2526597SStephen Boyd static struct clk_branch mmss_rbcpr_ahb_clk = { 1797c2526597SStephen Boyd .halt_reg = 0x4088, 1798c2526597SStephen Boyd .clkr = { 1799c2526597SStephen Boyd .enable_reg = 0x4088, 1800c2526597SStephen Boyd .enable_mask = BIT(0), 1801c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1802c2526597SStephen Boyd .name = "mmss_rbcpr_ahb_clk", 1803*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1804*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1805*e7c65912SDmitry Baryshkov }, 1806c2526597SStephen Boyd .num_parents = 1, 1807c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1808c2526597SStephen Boyd .ops = &clk_branch2_ops, 1809c2526597SStephen Boyd }, 1810c2526597SStephen Boyd }, 1811c2526597SStephen Boyd }; 1812c2526597SStephen Boyd 1813c2526597SStephen Boyd static struct clk_branch video_core_clk = { 1814c2526597SStephen Boyd .halt_reg = 0x1028, 1815c2526597SStephen Boyd .clkr = { 1816c2526597SStephen Boyd .enable_reg = 0x1028, 1817c2526597SStephen Boyd .enable_mask = BIT(0), 1818c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1819c2526597SStephen Boyd .name = "video_core_clk", 1820*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1821*e7c65912SDmitry Baryshkov &video_core_clk_src.clkr.hw 1822*e7c65912SDmitry Baryshkov }, 1823c2526597SStephen Boyd .num_parents = 1, 1824c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1825c2526597SStephen Boyd .ops = &clk_branch2_ops, 1826c2526597SStephen Boyd }, 1827c2526597SStephen Boyd }, 1828c2526597SStephen Boyd }; 1829c2526597SStephen Boyd 1830c2526597SStephen Boyd static struct clk_branch video_axi_clk = { 1831c2526597SStephen Boyd .halt_reg = 0x1034, 1832c2526597SStephen Boyd .clkr = { 1833c2526597SStephen Boyd .enable_reg = 0x1034, 1834c2526597SStephen Boyd .enable_mask = BIT(0), 1835c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1836c2526597SStephen Boyd .name = "video_axi_clk", 1837*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1838*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 1839*e7c65912SDmitry Baryshkov }, 1840c2526597SStephen Boyd .num_parents = 1, 1841c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1842c2526597SStephen Boyd .ops = &clk_branch2_ops, 1843c2526597SStephen Boyd }, 1844c2526597SStephen Boyd }, 1845c2526597SStephen Boyd }; 1846c2526597SStephen Boyd 1847c2526597SStephen Boyd static struct clk_branch video_maxi_clk = { 1848c2526597SStephen Boyd .halt_reg = 0x1038, 1849c2526597SStephen Boyd .clkr = { 1850c2526597SStephen Boyd .enable_reg = 0x1038, 1851c2526597SStephen Boyd .enable_mask = BIT(0), 1852c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1853c2526597SStephen Boyd .name = "video_maxi_clk", 1854*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1855*e7c65912SDmitry Baryshkov &maxi_clk_src.clkr.hw 1856*e7c65912SDmitry Baryshkov }, 1857c2526597SStephen Boyd .num_parents = 1, 1858c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1859c2526597SStephen Boyd .ops = &clk_branch2_ops, 1860c2526597SStephen Boyd }, 1861c2526597SStephen Boyd }, 1862c2526597SStephen Boyd }; 1863c2526597SStephen Boyd 1864c2526597SStephen Boyd static struct clk_branch video_ahb_clk = { 1865c2526597SStephen Boyd .halt_reg = 0x1030, 1866c2526597SStephen Boyd .clkr = { 1867c2526597SStephen Boyd .enable_reg = 0x1030, 1868c2526597SStephen Boyd .enable_mask = BIT(0), 1869c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1870c2526597SStephen Boyd .name = "video_ahb_clk", 1871*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1872*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1873*e7c65912SDmitry Baryshkov }, 1874c2526597SStephen Boyd .num_parents = 1, 1875c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1876c2526597SStephen Boyd .ops = &clk_branch2_ops, 1877c2526597SStephen Boyd }, 1878c2526597SStephen Boyd }, 1879c2526597SStephen Boyd }; 1880c2526597SStephen Boyd 1881c2526597SStephen Boyd static struct clk_branch video_subcore0_clk = { 1882c2526597SStephen Boyd .halt_reg = 0x1048, 1883c2526597SStephen Boyd .clkr = { 1884c2526597SStephen Boyd .enable_reg = 0x1048, 1885c2526597SStephen Boyd .enable_mask = BIT(0), 1886c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1887c2526597SStephen Boyd .name = "video_subcore0_clk", 1888*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1889*e7c65912SDmitry Baryshkov &video_subcore0_clk_src.clkr.hw 1890*e7c65912SDmitry Baryshkov }, 1891c2526597SStephen Boyd .num_parents = 1, 1892c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1893c2526597SStephen Boyd .ops = &clk_branch2_ops, 1894c2526597SStephen Boyd }, 1895c2526597SStephen Boyd }, 1896c2526597SStephen Boyd }; 1897c2526597SStephen Boyd 1898c2526597SStephen Boyd static struct clk_branch video_subcore1_clk = { 1899c2526597SStephen Boyd .halt_reg = 0x104c, 1900c2526597SStephen Boyd .clkr = { 1901c2526597SStephen Boyd .enable_reg = 0x104c, 1902c2526597SStephen Boyd .enable_mask = BIT(0), 1903c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1904c2526597SStephen Boyd .name = "video_subcore1_clk", 1905*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1906*e7c65912SDmitry Baryshkov &video_subcore1_clk_src.clkr.hw 1907*e7c65912SDmitry Baryshkov }, 1908c2526597SStephen Boyd .num_parents = 1, 1909c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1910c2526597SStephen Boyd .ops = &clk_branch2_ops, 1911c2526597SStephen Boyd }, 1912c2526597SStephen Boyd }, 1913c2526597SStephen Boyd }; 1914c2526597SStephen Boyd 1915c2526597SStephen Boyd static struct clk_branch mdss_ahb_clk = { 1916c2526597SStephen Boyd .halt_reg = 0x2308, 1917c2526597SStephen Boyd .clkr = { 1918c2526597SStephen Boyd .enable_reg = 0x2308, 1919c2526597SStephen Boyd .enable_mask = BIT(0), 1920c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1921c2526597SStephen Boyd .name = "mdss_ahb_clk", 1922*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1923*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1924*e7c65912SDmitry Baryshkov }, 1925c2526597SStephen Boyd .num_parents = 1, 1926c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1927c2526597SStephen Boyd .ops = &clk_branch2_ops, 1928c2526597SStephen Boyd }, 1929c2526597SStephen Boyd }, 1930c2526597SStephen Boyd }; 1931c2526597SStephen Boyd 1932c2526597SStephen Boyd static struct clk_branch mdss_hdmi_ahb_clk = { 1933c2526597SStephen Boyd .halt_reg = 0x230c, 1934c2526597SStephen Boyd .clkr = { 1935c2526597SStephen Boyd .enable_reg = 0x230c, 1936c2526597SStephen Boyd .enable_mask = BIT(0), 1937c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1938c2526597SStephen Boyd .name = "mdss_hdmi_ahb_clk", 1939*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1940*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 1941*e7c65912SDmitry Baryshkov }, 1942c2526597SStephen Boyd .num_parents = 1, 1943c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1944c2526597SStephen Boyd .ops = &clk_branch2_ops, 1945c2526597SStephen Boyd }, 1946c2526597SStephen Boyd }, 1947c2526597SStephen Boyd }; 1948c2526597SStephen Boyd 1949c2526597SStephen Boyd static struct clk_branch mdss_axi_clk = { 1950c2526597SStephen Boyd .halt_reg = 0x2310, 1951c2526597SStephen Boyd .clkr = { 1952c2526597SStephen Boyd .enable_reg = 0x2310, 1953c2526597SStephen Boyd .enable_mask = BIT(0), 1954c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1955c2526597SStephen Boyd .name = "mdss_axi_clk", 1956*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1957*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 1958*e7c65912SDmitry Baryshkov }, 1959c2526597SStephen Boyd .num_parents = 1, 1960c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1961c2526597SStephen Boyd .ops = &clk_branch2_ops, 1962c2526597SStephen Boyd }, 1963c2526597SStephen Boyd }, 1964c2526597SStephen Boyd }; 1965c2526597SStephen Boyd 1966c2526597SStephen Boyd static struct clk_branch mdss_pclk0_clk = { 1967c2526597SStephen Boyd .halt_reg = 0x2314, 1968c2526597SStephen Boyd .clkr = { 1969c2526597SStephen Boyd .enable_reg = 0x2314, 1970c2526597SStephen Boyd .enable_mask = BIT(0), 1971c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1972c2526597SStephen Boyd .name = "mdss_pclk0_clk", 1973*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1974*e7c65912SDmitry Baryshkov &pclk0_clk_src.clkr.hw 1975*e7c65912SDmitry Baryshkov }, 1976c2526597SStephen Boyd .num_parents = 1, 1977c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1978c2526597SStephen Boyd .ops = &clk_branch2_ops, 1979c2526597SStephen Boyd }, 1980c2526597SStephen Boyd }, 1981c2526597SStephen Boyd }; 1982c2526597SStephen Boyd 1983c2526597SStephen Boyd static struct clk_branch mdss_pclk1_clk = { 1984c2526597SStephen Boyd .halt_reg = 0x2318, 1985c2526597SStephen Boyd .clkr = { 1986c2526597SStephen Boyd .enable_reg = 0x2318, 1987c2526597SStephen Boyd .enable_mask = BIT(0), 1988c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1989c2526597SStephen Boyd .name = "mdss_pclk1_clk", 1990*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 1991*e7c65912SDmitry Baryshkov &pclk1_clk_src.clkr.hw 1992*e7c65912SDmitry Baryshkov }, 1993c2526597SStephen Boyd .num_parents = 1, 1994c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1995c2526597SStephen Boyd .ops = &clk_branch2_ops, 1996c2526597SStephen Boyd }, 1997c2526597SStephen Boyd }, 1998c2526597SStephen Boyd }; 1999c2526597SStephen Boyd 2000c2526597SStephen Boyd static struct clk_branch mdss_mdp_clk = { 2001c2526597SStephen Boyd .halt_reg = 0x231c, 2002c2526597SStephen Boyd .clkr = { 2003c2526597SStephen Boyd .enable_reg = 0x231c, 2004c2526597SStephen Boyd .enable_mask = BIT(0), 2005c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2006c2526597SStephen Boyd .name = "mdss_mdp_clk", 2007*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2008*e7c65912SDmitry Baryshkov &mdp_clk_src.clkr.hw 2009*e7c65912SDmitry Baryshkov }, 2010c2526597SStephen Boyd .num_parents = 1, 2011c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2012c2526597SStephen Boyd .ops = &clk_branch2_ops, 2013c2526597SStephen Boyd }, 2014c2526597SStephen Boyd }, 2015c2526597SStephen Boyd }; 2016c2526597SStephen Boyd 2017c2526597SStephen Boyd static struct clk_branch mdss_extpclk_clk = { 2018c2526597SStephen Boyd .halt_reg = 0x2324, 2019c2526597SStephen Boyd .clkr = { 2020c2526597SStephen Boyd .enable_reg = 0x2324, 2021c2526597SStephen Boyd .enable_mask = BIT(0), 2022c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2023c2526597SStephen Boyd .name = "mdss_extpclk_clk", 2024*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2025*e7c65912SDmitry Baryshkov &extpclk_clk_src.clkr.hw 2026*e7c65912SDmitry Baryshkov }, 2027c2526597SStephen Boyd .num_parents = 1, 2028c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2029c2526597SStephen Boyd .ops = &clk_branch2_ops, 2030c2526597SStephen Boyd }, 2031c2526597SStephen Boyd }, 2032c2526597SStephen Boyd }; 2033c2526597SStephen Boyd 2034c2526597SStephen Boyd static struct clk_branch mdss_vsync_clk = { 2035c2526597SStephen Boyd .halt_reg = 0x2328, 2036c2526597SStephen Boyd .clkr = { 2037c2526597SStephen Boyd .enable_reg = 0x2328, 2038c2526597SStephen Boyd .enable_mask = BIT(0), 2039c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2040c2526597SStephen Boyd .name = "mdss_vsync_clk", 2041*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2042*e7c65912SDmitry Baryshkov &vsync_clk_src.clkr.hw 2043*e7c65912SDmitry Baryshkov }, 2044c2526597SStephen Boyd .num_parents = 1, 2045c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2046c2526597SStephen Boyd .ops = &clk_branch2_ops, 2047c2526597SStephen Boyd }, 2048c2526597SStephen Boyd }, 2049c2526597SStephen Boyd }; 2050c2526597SStephen Boyd 2051c2526597SStephen Boyd static struct clk_branch mdss_hdmi_clk = { 2052c2526597SStephen Boyd .halt_reg = 0x2338, 2053c2526597SStephen Boyd .clkr = { 2054c2526597SStephen Boyd .enable_reg = 0x2338, 2055c2526597SStephen Boyd .enable_mask = BIT(0), 2056c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2057c2526597SStephen Boyd .name = "mdss_hdmi_clk", 2058*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2059*e7c65912SDmitry Baryshkov &hdmi_clk_src.clkr.hw 2060*e7c65912SDmitry Baryshkov }, 2061c2526597SStephen Boyd .num_parents = 1, 2062c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2063c2526597SStephen Boyd .ops = &clk_branch2_ops, 2064c2526597SStephen Boyd }, 2065c2526597SStephen Boyd }, 2066c2526597SStephen Boyd }; 2067c2526597SStephen Boyd 2068c2526597SStephen Boyd static struct clk_branch mdss_byte0_clk = { 2069c2526597SStephen Boyd .halt_reg = 0x233c, 2070c2526597SStephen Boyd .clkr = { 2071c2526597SStephen Boyd .enable_reg = 0x233c, 2072c2526597SStephen Boyd .enable_mask = BIT(0), 2073c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2074c2526597SStephen Boyd .name = "mdss_byte0_clk", 2075*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2076*e7c65912SDmitry Baryshkov &byte0_clk_src.clkr.hw 2077*e7c65912SDmitry Baryshkov }, 2078c2526597SStephen Boyd .num_parents = 1, 2079c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2080c2526597SStephen Boyd .ops = &clk_branch2_ops, 2081c2526597SStephen Boyd }, 2082c2526597SStephen Boyd }, 2083c2526597SStephen Boyd }; 2084c2526597SStephen Boyd 2085c2526597SStephen Boyd static struct clk_branch mdss_byte1_clk = { 2086c2526597SStephen Boyd .halt_reg = 0x2340, 2087c2526597SStephen Boyd .clkr = { 2088c2526597SStephen Boyd .enable_reg = 0x2340, 2089c2526597SStephen Boyd .enable_mask = BIT(0), 2090c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2091c2526597SStephen Boyd .name = "mdss_byte1_clk", 2092*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2093*e7c65912SDmitry Baryshkov &byte1_clk_src.clkr.hw 2094*e7c65912SDmitry Baryshkov }, 2095c2526597SStephen Boyd .num_parents = 1, 2096c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2097c2526597SStephen Boyd .ops = &clk_branch2_ops, 2098c2526597SStephen Boyd }, 2099c2526597SStephen Boyd }, 2100c2526597SStephen Boyd }; 2101c2526597SStephen Boyd 2102c2526597SStephen Boyd static struct clk_branch mdss_esc0_clk = { 2103c2526597SStephen Boyd .halt_reg = 0x2344, 2104c2526597SStephen Boyd .clkr = { 2105c2526597SStephen Boyd .enable_reg = 0x2344, 2106c2526597SStephen Boyd .enable_mask = BIT(0), 2107c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2108c2526597SStephen Boyd .name = "mdss_esc0_clk", 2109*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2110*e7c65912SDmitry Baryshkov &esc0_clk_src.clkr.hw 2111*e7c65912SDmitry Baryshkov }, 2112c2526597SStephen Boyd .num_parents = 1, 2113c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2114c2526597SStephen Boyd .ops = &clk_branch2_ops, 2115c2526597SStephen Boyd }, 2116c2526597SStephen Boyd }, 2117c2526597SStephen Boyd }; 2118c2526597SStephen Boyd 2119c2526597SStephen Boyd static struct clk_branch mdss_esc1_clk = { 2120c2526597SStephen Boyd .halt_reg = 0x2348, 2121c2526597SStephen Boyd .clkr = { 2122c2526597SStephen Boyd .enable_reg = 0x2348, 2123c2526597SStephen Boyd .enable_mask = BIT(0), 2124c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2125c2526597SStephen Boyd .name = "mdss_esc1_clk", 2126*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2127*e7c65912SDmitry Baryshkov &esc1_clk_src.clkr.hw 2128*e7c65912SDmitry Baryshkov }, 2129c2526597SStephen Boyd .num_parents = 1, 2130c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2131c2526597SStephen Boyd .ops = &clk_branch2_ops, 2132c2526597SStephen Boyd }, 2133c2526597SStephen Boyd }, 2134c2526597SStephen Boyd }; 2135c2526597SStephen Boyd 2136c2526597SStephen Boyd static struct clk_branch camss_top_ahb_clk = { 2137c2526597SStephen Boyd .halt_reg = 0x3484, 2138c2526597SStephen Boyd .clkr = { 2139c2526597SStephen Boyd .enable_reg = 0x3484, 2140c2526597SStephen Boyd .enable_mask = BIT(0), 2141c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2142c2526597SStephen Boyd .name = "camss_top_ahb_clk", 2143*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2144*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2145*e7c65912SDmitry Baryshkov }, 2146c2526597SStephen Boyd .num_parents = 1, 2147c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2148c2526597SStephen Boyd .ops = &clk_branch2_ops, 2149c2526597SStephen Boyd }, 2150c2526597SStephen Boyd }, 2151c2526597SStephen Boyd }; 2152c2526597SStephen Boyd 2153c2526597SStephen Boyd static struct clk_branch camss_ahb_clk = { 2154c2526597SStephen Boyd .halt_reg = 0x348c, 2155c2526597SStephen Boyd .clkr = { 2156c2526597SStephen Boyd .enable_reg = 0x348c, 2157c2526597SStephen Boyd .enable_mask = BIT(0), 2158c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2159c2526597SStephen Boyd .name = "camss_ahb_clk", 2160*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2161*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2162*e7c65912SDmitry Baryshkov }, 2163c2526597SStephen Boyd .num_parents = 1, 2164c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2165c2526597SStephen Boyd .ops = &clk_branch2_ops, 2166c2526597SStephen Boyd }, 2167c2526597SStephen Boyd }, 2168c2526597SStephen Boyd }; 2169c2526597SStephen Boyd 2170c2526597SStephen Boyd static struct clk_branch camss_micro_ahb_clk = { 2171c2526597SStephen Boyd .halt_reg = 0x3494, 2172c2526597SStephen Boyd .clkr = { 2173c2526597SStephen Boyd .enable_reg = 0x3494, 2174c2526597SStephen Boyd .enable_mask = BIT(0), 2175c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2176c2526597SStephen Boyd .name = "camss_micro_ahb_clk", 2177*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2178*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2179*e7c65912SDmitry Baryshkov }, 2180c2526597SStephen Boyd .num_parents = 1, 2181c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2182c2526597SStephen Boyd .ops = &clk_branch2_ops, 2183c2526597SStephen Boyd }, 2184c2526597SStephen Boyd }, 2185c2526597SStephen Boyd }; 2186c2526597SStephen Boyd 2187c2526597SStephen Boyd static struct clk_branch camss_gp0_clk = { 2188c2526597SStephen Boyd .halt_reg = 0x3444, 2189c2526597SStephen Boyd .clkr = { 2190c2526597SStephen Boyd .enable_reg = 0x3444, 2191c2526597SStephen Boyd .enable_mask = BIT(0), 2192c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2193c2526597SStephen Boyd .name = "camss_gp0_clk", 2194*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2195*e7c65912SDmitry Baryshkov &camss_gp0_clk_src.clkr.hw 2196*e7c65912SDmitry Baryshkov }, 2197c2526597SStephen Boyd .num_parents = 1, 2198c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2199c2526597SStephen Boyd .ops = &clk_branch2_ops, 2200c2526597SStephen Boyd }, 2201c2526597SStephen Boyd }, 2202c2526597SStephen Boyd }; 2203c2526597SStephen Boyd 2204c2526597SStephen Boyd static struct clk_branch camss_gp1_clk = { 2205c2526597SStephen Boyd .halt_reg = 0x3474, 2206c2526597SStephen Boyd .clkr = { 2207c2526597SStephen Boyd .enable_reg = 0x3474, 2208c2526597SStephen Boyd .enable_mask = BIT(0), 2209c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2210c2526597SStephen Boyd .name = "camss_gp1_clk", 2211*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2212*e7c65912SDmitry Baryshkov &camss_gp1_clk_src.clkr.hw 2213*e7c65912SDmitry Baryshkov }, 2214c2526597SStephen Boyd .num_parents = 1, 2215c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2216c2526597SStephen Boyd .ops = &clk_branch2_ops, 2217c2526597SStephen Boyd }, 2218c2526597SStephen Boyd }, 2219c2526597SStephen Boyd }; 2220c2526597SStephen Boyd 2221c2526597SStephen Boyd static struct clk_branch camss_mclk0_clk = { 2222c2526597SStephen Boyd .halt_reg = 0x3384, 2223c2526597SStephen Boyd .clkr = { 2224c2526597SStephen Boyd .enable_reg = 0x3384, 2225c2526597SStephen Boyd .enable_mask = BIT(0), 2226c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2227c2526597SStephen Boyd .name = "camss_mclk0_clk", 2228*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2229*e7c65912SDmitry Baryshkov &mclk0_clk_src.clkr.hw 2230*e7c65912SDmitry Baryshkov }, 2231c2526597SStephen Boyd .num_parents = 1, 2232c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2233c2526597SStephen Boyd .ops = &clk_branch2_ops, 2234c2526597SStephen Boyd }, 2235c2526597SStephen Boyd }, 2236c2526597SStephen Boyd }; 2237c2526597SStephen Boyd 2238c2526597SStephen Boyd static struct clk_branch camss_mclk1_clk = { 2239c2526597SStephen Boyd .halt_reg = 0x33b4, 2240c2526597SStephen Boyd .clkr = { 2241c2526597SStephen Boyd .enable_reg = 0x33b4, 2242c2526597SStephen Boyd .enable_mask = BIT(0), 2243c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2244c2526597SStephen Boyd .name = "camss_mclk1_clk", 2245*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2246*e7c65912SDmitry Baryshkov &mclk1_clk_src.clkr.hw 2247*e7c65912SDmitry Baryshkov }, 2248c2526597SStephen Boyd .num_parents = 1, 2249c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2250c2526597SStephen Boyd .ops = &clk_branch2_ops, 2251c2526597SStephen Boyd }, 2252c2526597SStephen Boyd }, 2253c2526597SStephen Boyd }; 2254c2526597SStephen Boyd 2255c2526597SStephen Boyd static struct clk_branch camss_mclk2_clk = { 2256c2526597SStephen Boyd .halt_reg = 0x33e4, 2257c2526597SStephen Boyd .clkr = { 2258c2526597SStephen Boyd .enable_reg = 0x33e4, 2259c2526597SStephen Boyd .enable_mask = BIT(0), 2260c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2261c2526597SStephen Boyd .name = "camss_mclk2_clk", 2262*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2263*e7c65912SDmitry Baryshkov &mclk2_clk_src.clkr.hw 2264*e7c65912SDmitry Baryshkov }, 2265c2526597SStephen Boyd .num_parents = 1, 2266c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2267c2526597SStephen Boyd .ops = &clk_branch2_ops, 2268c2526597SStephen Boyd }, 2269c2526597SStephen Boyd }, 2270c2526597SStephen Boyd }; 2271c2526597SStephen Boyd 2272c2526597SStephen Boyd static struct clk_branch camss_mclk3_clk = { 2273c2526597SStephen Boyd .halt_reg = 0x3414, 2274c2526597SStephen Boyd .clkr = { 2275c2526597SStephen Boyd .enable_reg = 0x3414, 2276c2526597SStephen Boyd .enable_mask = BIT(0), 2277c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2278c2526597SStephen Boyd .name = "camss_mclk3_clk", 2279*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2280*e7c65912SDmitry Baryshkov &mclk3_clk_src.clkr.hw 2281*e7c65912SDmitry Baryshkov }, 2282c2526597SStephen Boyd .num_parents = 1, 2283c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2284c2526597SStephen Boyd .ops = &clk_branch2_ops, 2285c2526597SStephen Boyd }, 2286c2526597SStephen Boyd }, 2287c2526597SStephen Boyd }; 2288c2526597SStephen Boyd 2289c2526597SStephen Boyd static struct clk_branch camss_cci_clk = { 2290c2526597SStephen Boyd .halt_reg = 0x3344, 2291c2526597SStephen Boyd .clkr = { 2292c2526597SStephen Boyd .enable_reg = 0x3344, 2293c2526597SStephen Boyd .enable_mask = BIT(0), 2294c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2295c2526597SStephen Boyd .name = "camss_cci_clk", 2296*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2297*e7c65912SDmitry Baryshkov &cci_clk_src.clkr.hw 2298*e7c65912SDmitry Baryshkov }, 2299c2526597SStephen Boyd .num_parents = 1, 2300c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2301c2526597SStephen Boyd .ops = &clk_branch2_ops, 2302c2526597SStephen Boyd }, 2303c2526597SStephen Boyd }, 2304c2526597SStephen Boyd }; 2305c2526597SStephen Boyd 2306c2526597SStephen Boyd static struct clk_branch camss_cci_ahb_clk = { 2307c2526597SStephen Boyd .halt_reg = 0x3348, 2308c2526597SStephen Boyd .clkr = { 2309c2526597SStephen Boyd .enable_reg = 0x3348, 2310c2526597SStephen Boyd .enable_mask = BIT(0), 2311c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2312c2526597SStephen Boyd .name = "camss_cci_ahb_clk", 2313*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2314*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2315*e7c65912SDmitry Baryshkov }, 2316c2526597SStephen Boyd .num_parents = 1, 2317c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2318c2526597SStephen Boyd .ops = &clk_branch2_ops, 2319c2526597SStephen Boyd }, 2320c2526597SStephen Boyd }, 2321c2526597SStephen Boyd }; 2322c2526597SStephen Boyd 2323c2526597SStephen Boyd static struct clk_branch camss_csi0phytimer_clk = { 2324c2526597SStephen Boyd .halt_reg = 0x3024, 2325c2526597SStephen Boyd .clkr = { 2326c2526597SStephen Boyd .enable_reg = 0x3024, 2327c2526597SStephen Boyd .enable_mask = BIT(0), 2328c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2329c2526597SStephen Boyd .name = "camss_csi0phytimer_clk", 2330*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2331*e7c65912SDmitry Baryshkov &csi0phytimer_clk_src.clkr.hw 2332*e7c65912SDmitry Baryshkov }, 2333c2526597SStephen Boyd .num_parents = 1, 2334c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2335c2526597SStephen Boyd .ops = &clk_branch2_ops, 2336c2526597SStephen Boyd }, 2337c2526597SStephen Boyd }, 2338c2526597SStephen Boyd }; 2339c2526597SStephen Boyd 2340c2526597SStephen Boyd static struct clk_branch camss_csi1phytimer_clk = { 2341c2526597SStephen Boyd .halt_reg = 0x3054, 2342c2526597SStephen Boyd .clkr = { 2343c2526597SStephen Boyd .enable_reg = 0x3054, 2344c2526597SStephen Boyd .enable_mask = BIT(0), 2345c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2346c2526597SStephen Boyd .name = "camss_csi1phytimer_clk", 2347*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2348*e7c65912SDmitry Baryshkov &csi1phytimer_clk_src.clkr.hw 2349*e7c65912SDmitry Baryshkov }, 2350c2526597SStephen Boyd .num_parents = 1, 2351c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2352c2526597SStephen Boyd .ops = &clk_branch2_ops, 2353c2526597SStephen Boyd }, 2354c2526597SStephen Boyd }, 2355c2526597SStephen Boyd }; 2356c2526597SStephen Boyd 2357c2526597SStephen Boyd static struct clk_branch camss_csi2phytimer_clk = { 2358c2526597SStephen Boyd .halt_reg = 0x3084, 2359c2526597SStephen Boyd .clkr = { 2360c2526597SStephen Boyd .enable_reg = 0x3084, 2361c2526597SStephen Boyd .enable_mask = BIT(0), 2362c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2363c2526597SStephen Boyd .name = "camss_csi2phytimer_clk", 2364*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2365*e7c65912SDmitry Baryshkov &csi2phytimer_clk_src.clkr.hw 2366*e7c65912SDmitry Baryshkov }, 2367c2526597SStephen Boyd .num_parents = 1, 2368c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2369c2526597SStephen Boyd .ops = &clk_branch2_ops, 2370c2526597SStephen Boyd }, 2371c2526597SStephen Boyd }, 2372c2526597SStephen Boyd }; 2373c2526597SStephen Boyd 2374c2526597SStephen Boyd static struct clk_branch camss_csiphy0_3p_clk = { 2375c2526597SStephen Boyd .halt_reg = 0x3234, 2376c2526597SStephen Boyd .clkr = { 2377c2526597SStephen Boyd .enable_reg = 0x3234, 2378c2526597SStephen Boyd .enable_mask = BIT(0), 2379c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2380c2526597SStephen Boyd .name = "camss_csiphy0_3p_clk", 2381*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2382*e7c65912SDmitry Baryshkov &csiphy0_3p_clk_src.clkr.hw 2383*e7c65912SDmitry Baryshkov }, 2384c2526597SStephen Boyd .num_parents = 1, 2385c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2386c2526597SStephen Boyd .ops = &clk_branch2_ops, 2387c2526597SStephen Boyd }, 2388c2526597SStephen Boyd }, 2389c2526597SStephen Boyd }; 2390c2526597SStephen Boyd 2391c2526597SStephen Boyd static struct clk_branch camss_csiphy1_3p_clk = { 2392c2526597SStephen Boyd .halt_reg = 0x3254, 2393c2526597SStephen Boyd .clkr = { 2394c2526597SStephen Boyd .enable_reg = 0x3254, 2395c2526597SStephen Boyd .enable_mask = BIT(0), 2396c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2397c2526597SStephen Boyd .name = "camss_csiphy1_3p_clk", 2398*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2399*e7c65912SDmitry Baryshkov &csiphy1_3p_clk_src.clkr.hw 2400*e7c65912SDmitry Baryshkov }, 2401c2526597SStephen Boyd .num_parents = 1, 2402c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2403c2526597SStephen Boyd .ops = &clk_branch2_ops, 2404c2526597SStephen Boyd }, 2405c2526597SStephen Boyd }, 2406c2526597SStephen Boyd }; 2407c2526597SStephen Boyd 2408c2526597SStephen Boyd static struct clk_branch camss_csiphy2_3p_clk = { 2409c2526597SStephen Boyd .halt_reg = 0x3274, 2410c2526597SStephen Boyd .clkr = { 2411c2526597SStephen Boyd .enable_reg = 0x3274, 2412c2526597SStephen Boyd .enable_mask = BIT(0), 2413c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2414c2526597SStephen Boyd .name = "camss_csiphy2_3p_clk", 2415*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2416*e7c65912SDmitry Baryshkov &csiphy2_3p_clk_src.clkr.hw 2417*e7c65912SDmitry Baryshkov }, 2418c2526597SStephen Boyd .num_parents = 1, 2419c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2420c2526597SStephen Boyd .ops = &clk_branch2_ops, 2421c2526597SStephen Boyd }, 2422c2526597SStephen Boyd }, 2423c2526597SStephen Boyd }; 2424c2526597SStephen Boyd 2425c2526597SStephen Boyd static struct clk_branch camss_jpeg0_clk = { 2426c2526597SStephen Boyd .halt_reg = 0x35a8, 2427c2526597SStephen Boyd .clkr = { 2428c2526597SStephen Boyd .enable_reg = 0x35a8, 2429c2526597SStephen Boyd .enable_mask = BIT(0), 2430c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2431c2526597SStephen Boyd .name = "camss_jpeg0_clk", 2432*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2433*e7c65912SDmitry Baryshkov &jpeg0_clk_src.clkr.hw 2434*e7c65912SDmitry Baryshkov }, 2435c2526597SStephen Boyd .num_parents = 1, 2436c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2437c2526597SStephen Boyd .ops = &clk_branch2_ops, 2438c2526597SStephen Boyd }, 2439c2526597SStephen Boyd }, 2440c2526597SStephen Boyd }; 2441c2526597SStephen Boyd 2442c2526597SStephen Boyd static struct clk_branch camss_jpeg2_clk = { 2443c2526597SStephen Boyd .halt_reg = 0x35b0, 2444c2526597SStephen Boyd .clkr = { 2445c2526597SStephen Boyd .enable_reg = 0x35b0, 2446c2526597SStephen Boyd .enable_mask = BIT(0), 2447c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2448c2526597SStephen Boyd .name = "camss_jpeg2_clk", 2449*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2450*e7c65912SDmitry Baryshkov &jpeg2_clk_src.clkr.hw 2451*e7c65912SDmitry Baryshkov }, 2452c2526597SStephen Boyd .num_parents = 1, 2453c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2454c2526597SStephen Boyd .ops = &clk_branch2_ops, 2455c2526597SStephen Boyd }, 2456c2526597SStephen Boyd }, 2457c2526597SStephen Boyd }; 2458c2526597SStephen Boyd 2459c2526597SStephen Boyd static struct clk_branch camss_jpeg_dma_clk = { 2460c2526597SStephen Boyd .halt_reg = 0x35c0, 2461c2526597SStephen Boyd .clkr = { 2462c2526597SStephen Boyd .enable_reg = 0x35c0, 2463c2526597SStephen Boyd .enable_mask = BIT(0), 2464c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2465c2526597SStephen Boyd .name = "camss_jpeg_dma_clk", 2466*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2467*e7c65912SDmitry Baryshkov &jpeg_dma_clk_src.clkr.hw 2468*e7c65912SDmitry Baryshkov }, 2469c2526597SStephen Boyd .num_parents = 1, 2470c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2471c2526597SStephen Boyd .ops = &clk_branch2_ops, 2472c2526597SStephen Boyd }, 2473c2526597SStephen Boyd }, 2474c2526597SStephen Boyd }; 2475c2526597SStephen Boyd 2476c2526597SStephen Boyd static struct clk_branch camss_jpeg_ahb_clk = { 2477c2526597SStephen Boyd .halt_reg = 0x35b4, 2478c2526597SStephen Boyd .clkr = { 2479c2526597SStephen Boyd .enable_reg = 0x35b4, 2480c2526597SStephen Boyd .enable_mask = BIT(0), 2481c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2482c2526597SStephen Boyd .name = "camss_jpeg_ahb_clk", 2483*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2484*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2485*e7c65912SDmitry Baryshkov }, 2486c2526597SStephen Boyd .num_parents = 1, 2487c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2488c2526597SStephen Boyd .ops = &clk_branch2_ops, 2489c2526597SStephen Boyd }, 2490c2526597SStephen Boyd }, 2491c2526597SStephen Boyd }; 2492c2526597SStephen Boyd 2493c2526597SStephen Boyd static struct clk_branch camss_jpeg_axi_clk = { 2494c2526597SStephen Boyd .halt_reg = 0x35b8, 2495c2526597SStephen Boyd .clkr = { 2496c2526597SStephen Boyd .enable_reg = 0x35b8, 2497c2526597SStephen Boyd .enable_mask = BIT(0), 2498c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2499c2526597SStephen Boyd .name = "camss_jpeg_axi_clk", 2500*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2501*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 2502*e7c65912SDmitry Baryshkov }, 2503c2526597SStephen Boyd .num_parents = 1, 2504c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2505c2526597SStephen Boyd .ops = &clk_branch2_ops, 2506c2526597SStephen Boyd }, 2507c2526597SStephen Boyd }, 2508c2526597SStephen Boyd }; 2509c2526597SStephen Boyd 2510c2526597SStephen Boyd static struct clk_branch camss_vfe_ahb_clk = { 2511c2526597SStephen Boyd .halt_reg = 0x36b8, 2512c2526597SStephen Boyd .clkr = { 2513c2526597SStephen Boyd .enable_reg = 0x36b8, 2514c2526597SStephen Boyd .enable_mask = BIT(0), 2515c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2516c2526597SStephen Boyd .name = "camss_vfe_ahb_clk", 2517*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2518*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2519*e7c65912SDmitry Baryshkov }, 2520c2526597SStephen Boyd .num_parents = 1, 2521c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2522c2526597SStephen Boyd .ops = &clk_branch2_ops, 2523c2526597SStephen Boyd }, 2524c2526597SStephen Boyd }, 2525c2526597SStephen Boyd }; 2526c2526597SStephen Boyd 2527c2526597SStephen Boyd static struct clk_branch camss_vfe_axi_clk = { 2528c2526597SStephen Boyd .halt_reg = 0x36bc, 2529c2526597SStephen Boyd .clkr = { 2530c2526597SStephen Boyd .enable_reg = 0x36bc, 2531c2526597SStephen Boyd .enable_mask = BIT(0), 2532c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2533c2526597SStephen Boyd .name = "camss_vfe_axi_clk", 2534*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2535*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 2536*e7c65912SDmitry Baryshkov }, 2537c2526597SStephen Boyd .num_parents = 1, 2538c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2539c2526597SStephen Boyd .ops = &clk_branch2_ops, 2540c2526597SStephen Boyd }, 2541c2526597SStephen Boyd }, 2542c2526597SStephen Boyd }; 2543c2526597SStephen Boyd 2544c2526597SStephen Boyd static struct clk_branch camss_vfe0_clk = { 2545c2526597SStephen Boyd .halt_reg = 0x36a8, 2546c2526597SStephen Boyd .clkr = { 2547c2526597SStephen Boyd .enable_reg = 0x36a8, 2548c2526597SStephen Boyd .enable_mask = BIT(0), 2549c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2550c2526597SStephen Boyd .name = "camss_vfe0_clk", 2551*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2552*e7c65912SDmitry Baryshkov &vfe0_clk_src.clkr.hw 2553*e7c65912SDmitry Baryshkov }, 2554c2526597SStephen Boyd .num_parents = 1, 2555c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2556c2526597SStephen Boyd .ops = &clk_branch2_ops, 2557c2526597SStephen Boyd }, 2558c2526597SStephen Boyd }, 2559c2526597SStephen Boyd }; 2560c2526597SStephen Boyd 2561c2526597SStephen Boyd static struct clk_branch camss_vfe0_stream_clk = { 2562c2526597SStephen Boyd .halt_reg = 0x3720, 2563c2526597SStephen Boyd .clkr = { 2564c2526597SStephen Boyd .enable_reg = 0x3720, 2565c2526597SStephen Boyd .enable_mask = BIT(0), 2566c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2567c2526597SStephen Boyd .name = "camss_vfe0_stream_clk", 2568*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2569*e7c65912SDmitry Baryshkov &vfe0_clk_src.clkr.hw 2570*e7c65912SDmitry Baryshkov }, 2571c2526597SStephen Boyd .num_parents = 1, 2572c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2573c2526597SStephen Boyd .ops = &clk_branch2_ops, 2574c2526597SStephen Boyd }, 2575c2526597SStephen Boyd }, 2576c2526597SStephen Boyd }; 2577c2526597SStephen Boyd 2578c2526597SStephen Boyd static struct clk_branch camss_vfe0_ahb_clk = { 2579c2526597SStephen Boyd .halt_reg = 0x3668, 2580c2526597SStephen Boyd .clkr = { 2581c2526597SStephen Boyd .enable_reg = 0x3668, 2582c2526597SStephen Boyd .enable_mask = BIT(0), 2583c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2584c2526597SStephen Boyd .name = "camss_vfe0_ahb_clk", 2585*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2586*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2587*e7c65912SDmitry Baryshkov }, 2588c2526597SStephen Boyd .num_parents = 1, 2589c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2590c2526597SStephen Boyd .ops = &clk_branch2_ops, 2591c2526597SStephen Boyd }, 2592c2526597SStephen Boyd }, 2593c2526597SStephen Boyd }; 2594c2526597SStephen Boyd 2595c2526597SStephen Boyd static struct clk_branch camss_vfe1_clk = { 2596c2526597SStephen Boyd .halt_reg = 0x36ac, 2597c2526597SStephen Boyd .clkr = { 2598c2526597SStephen Boyd .enable_reg = 0x36ac, 2599c2526597SStephen Boyd .enable_mask = BIT(0), 2600c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2601c2526597SStephen Boyd .name = "camss_vfe1_clk", 2602*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2603*e7c65912SDmitry Baryshkov &vfe1_clk_src.clkr.hw 2604*e7c65912SDmitry Baryshkov }, 2605c2526597SStephen Boyd .num_parents = 1, 2606c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2607c2526597SStephen Boyd .ops = &clk_branch2_ops, 2608c2526597SStephen Boyd }, 2609c2526597SStephen Boyd }, 2610c2526597SStephen Boyd }; 2611c2526597SStephen Boyd 2612c2526597SStephen Boyd static struct clk_branch camss_vfe1_stream_clk = { 2613c2526597SStephen Boyd .halt_reg = 0x3724, 2614c2526597SStephen Boyd .clkr = { 2615c2526597SStephen Boyd .enable_reg = 0x3724, 2616c2526597SStephen Boyd .enable_mask = BIT(0), 2617c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2618c2526597SStephen Boyd .name = "camss_vfe1_stream_clk", 2619*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2620*e7c65912SDmitry Baryshkov &vfe1_clk_src.clkr.hw 2621*e7c65912SDmitry Baryshkov }, 2622c2526597SStephen Boyd .num_parents = 1, 2623c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2624c2526597SStephen Boyd .ops = &clk_branch2_ops, 2625c2526597SStephen Boyd }, 2626c2526597SStephen Boyd }, 2627c2526597SStephen Boyd }; 2628c2526597SStephen Boyd 2629c2526597SStephen Boyd static struct clk_branch camss_vfe1_ahb_clk = { 2630c2526597SStephen Boyd .halt_reg = 0x3678, 2631c2526597SStephen Boyd .clkr = { 2632c2526597SStephen Boyd .enable_reg = 0x3678, 2633c2526597SStephen Boyd .enable_mask = BIT(0), 2634c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2635c2526597SStephen Boyd .name = "camss_vfe1_ahb_clk", 2636*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2637*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2638*e7c65912SDmitry Baryshkov }, 2639c2526597SStephen Boyd .num_parents = 1, 2640c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2641c2526597SStephen Boyd .ops = &clk_branch2_ops, 2642c2526597SStephen Boyd }, 2643c2526597SStephen Boyd }, 2644c2526597SStephen Boyd }; 2645c2526597SStephen Boyd 2646c2526597SStephen Boyd static struct clk_branch camss_csi_vfe0_clk = { 2647c2526597SStephen Boyd .halt_reg = 0x3704, 2648c2526597SStephen Boyd .clkr = { 2649c2526597SStephen Boyd .enable_reg = 0x3704, 2650c2526597SStephen Boyd .enable_mask = BIT(0), 2651c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2652c2526597SStephen Boyd .name = "camss_csi_vfe0_clk", 2653*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2654*e7c65912SDmitry Baryshkov &vfe0_clk_src.clkr.hw 2655*e7c65912SDmitry Baryshkov }, 2656c2526597SStephen Boyd .num_parents = 1, 2657c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2658c2526597SStephen Boyd .ops = &clk_branch2_ops, 2659c2526597SStephen Boyd }, 2660c2526597SStephen Boyd }, 2661c2526597SStephen Boyd }; 2662c2526597SStephen Boyd 2663c2526597SStephen Boyd static struct clk_branch camss_csi_vfe1_clk = { 2664c2526597SStephen Boyd .halt_reg = 0x3714, 2665c2526597SStephen Boyd .clkr = { 2666c2526597SStephen Boyd .enable_reg = 0x3714, 2667c2526597SStephen Boyd .enable_mask = BIT(0), 2668c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2669c2526597SStephen Boyd .name = "camss_csi_vfe1_clk", 2670*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2671*e7c65912SDmitry Baryshkov &vfe1_clk_src.clkr.hw 2672*e7c65912SDmitry Baryshkov }, 2673c2526597SStephen Boyd .num_parents = 1, 2674c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2675c2526597SStephen Boyd .ops = &clk_branch2_ops, 2676c2526597SStephen Boyd }, 2677c2526597SStephen Boyd }, 2678c2526597SStephen Boyd }; 2679c2526597SStephen Boyd 2680c2526597SStephen Boyd static struct clk_branch camss_cpp_vbif_ahb_clk = { 2681c2526597SStephen Boyd .halt_reg = 0x36c8, 2682c2526597SStephen Boyd .clkr = { 2683c2526597SStephen Boyd .enable_reg = 0x36c8, 2684c2526597SStephen Boyd .enable_mask = BIT(0), 2685c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2686c2526597SStephen Boyd .name = "camss_cpp_vbif_ahb_clk", 2687*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2688*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2689*e7c65912SDmitry Baryshkov }, 2690c2526597SStephen Boyd .num_parents = 1, 2691c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2692c2526597SStephen Boyd .ops = &clk_branch2_ops, 2693c2526597SStephen Boyd }, 2694c2526597SStephen Boyd }, 2695c2526597SStephen Boyd }; 2696c2526597SStephen Boyd 2697c2526597SStephen Boyd static struct clk_branch camss_cpp_axi_clk = { 2698c2526597SStephen Boyd .halt_reg = 0x36c4, 2699c2526597SStephen Boyd .clkr = { 2700c2526597SStephen Boyd .enable_reg = 0x36c4, 2701c2526597SStephen Boyd .enable_mask = BIT(0), 2702c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2703c2526597SStephen Boyd .name = "camss_cpp_axi_clk", 2704*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2705*e7c65912SDmitry Baryshkov &axi_clk_src.clkr.hw 2706*e7c65912SDmitry Baryshkov }, 2707c2526597SStephen Boyd .num_parents = 1, 2708c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2709c2526597SStephen Boyd .ops = &clk_branch2_ops, 2710c2526597SStephen Boyd }, 2711c2526597SStephen Boyd }, 2712c2526597SStephen Boyd }; 2713c2526597SStephen Boyd 2714c2526597SStephen Boyd static struct clk_branch camss_cpp_clk = { 2715c2526597SStephen Boyd .halt_reg = 0x36b0, 2716c2526597SStephen Boyd .clkr = { 2717c2526597SStephen Boyd .enable_reg = 0x36b0, 2718c2526597SStephen Boyd .enable_mask = BIT(0), 2719c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2720c2526597SStephen Boyd .name = "camss_cpp_clk", 2721*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2722*e7c65912SDmitry Baryshkov &cpp_clk_src.clkr.hw 2723*e7c65912SDmitry Baryshkov }, 2724c2526597SStephen Boyd .num_parents = 1, 2725c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2726c2526597SStephen Boyd .ops = &clk_branch2_ops, 2727c2526597SStephen Boyd }, 2728c2526597SStephen Boyd }, 2729c2526597SStephen Boyd }; 2730c2526597SStephen Boyd 2731c2526597SStephen Boyd static struct clk_branch camss_cpp_ahb_clk = { 2732c2526597SStephen Boyd .halt_reg = 0x36b4, 2733c2526597SStephen Boyd .clkr = { 2734c2526597SStephen Boyd .enable_reg = 0x36b4, 2735c2526597SStephen Boyd .enable_mask = BIT(0), 2736c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2737c2526597SStephen Boyd .name = "camss_cpp_ahb_clk", 2738*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2739*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2740*e7c65912SDmitry Baryshkov }, 2741c2526597SStephen Boyd .num_parents = 1, 2742c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2743c2526597SStephen Boyd .ops = &clk_branch2_ops, 2744c2526597SStephen Boyd }, 2745c2526597SStephen Boyd }, 2746c2526597SStephen Boyd }; 2747c2526597SStephen Boyd 2748c2526597SStephen Boyd static struct clk_branch camss_csi0_clk = { 2749c2526597SStephen Boyd .halt_reg = 0x30b4, 2750c2526597SStephen Boyd .clkr = { 2751c2526597SStephen Boyd .enable_reg = 0x30b4, 2752c2526597SStephen Boyd .enable_mask = BIT(0), 2753c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2754c2526597SStephen Boyd .name = "camss_csi0_clk", 2755*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2756*e7c65912SDmitry Baryshkov &csi0_clk_src.clkr.hw 2757*e7c65912SDmitry Baryshkov }, 2758c2526597SStephen Boyd .num_parents = 1, 2759c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2760c2526597SStephen Boyd .ops = &clk_branch2_ops, 2761c2526597SStephen Boyd }, 2762c2526597SStephen Boyd }, 2763c2526597SStephen Boyd }; 2764c2526597SStephen Boyd 2765c2526597SStephen Boyd static struct clk_branch camss_csi0_ahb_clk = { 2766c2526597SStephen Boyd .halt_reg = 0x30bc, 2767c2526597SStephen Boyd .clkr = { 2768c2526597SStephen Boyd .enable_reg = 0x30bc, 2769c2526597SStephen Boyd .enable_mask = BIT(0), 2770c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2771c2526597SStephen Boyd .name = "camss_csi0_ahb_clk", 2772*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2773*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2774*e7c65912SDmitry Baryshkov }, 2775c2526597SStephen Boyd .num_parents = 1, 2776c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2777c2526597SStephen Boyd .ops = &clk_branch2_ops, 2778c2526597SStephen Boyd }, 2779c2526597SStephen Boyd }, 2780c2526597SStephen Boyd }; 2781c2526597SStephen Boyd 2782c2526597SStephen Boyd static struct clk_branch camss_csi0phy_clk = { 2783c2526597SStephen Boyd .halt_reg = 0x30c4, 2784c2526597SStephen Boyd .clkr = { 2785c2526597SStephen Boyd .enable_reg = 0x30c4, 2786c2526597SStephen Boyd .enable_mask = BIT(0), 2787c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2788c2526597SStephen Boyd .name = "camss_csi0phy_clk", 2789*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2790*e7c65912SDmitry Baryshkov &csi0_clk_src.clkr.hw 2791*e7c65912SDmitry Baryshkov }, 2792c2526597SStephen Boyd .num_parents = 1, 2793c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2794c2526597SStephen Boyd .ops = &clk_branch2_ops, 2795c2526597SStephen Boyd }, 2796c2526597SStephen Boyd }, 2797c2526597SStephen Boyd }; 2798c2526597SStephen Boyd 2799c2526597SStephen Boyd static struct clk_branch camss_csi0rdi_clk = { 2800c2526597SStephen Boyd .halt_reg = 0x30d4, 2801c2526597SStephen Boyd .clkr = { 2802c2526597SStephen Boyd .enable_reg = 0x30d4, 2803c2526597SStephen Boyd .enable_mask = BIT(0), 2804c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2805c2526597SStephen Boyd .name = "camss_csi0rdi_clk", 2806*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2807*e7c65912SDmitry Baryshkov &csi0_clk_src.clkr.hw 2808*e7c65912SDmitry Baryshkov }, 2809c2526597SStephen Boyd .num_parents = 1, 2810c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2811c2526597SStephen Boyd .ops = &clk_branch2_ops, 2812c2526597SStephen Boyd }, 2813c2526597SStephen Boyd }, 2814c2526597SStephen Boyd }; 2815c2526597SStephen Boyd 2816c2526597SStephen Boyd static struct clk_branch camss_csi0pix_clk = { 2817c2526597SStephen Boyd .halt_reg = 0x30e4, 2818c2526597SStephen Boyd .clkr = { 2819c2526597SStephen Boyd .enable_reg = 0x30e4, 2820c2526597SStephen Boyd .enable_mask = BIT(0), 2821c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2822c2526597SStephen Boyd .name = "camss_csi0pix_clk", 2823*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2824*e7c65912SDmitry Baryshkov &csi0_clk_src.clkr.hw 2825*e7c65912SDmitry Baryshkov }, 2826c2526597SStephen Boyd .num_parents = 1, 2827c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2828c2526597SStephen Boyd .ops = &clk_branch2_ops, 2829c2526597SStephen Boyd }, 2830c2526597SStephen Boyd }, 2831c2526597SStephen Boyd }; 2832c2526597SStephen Boyd 2833c2526597SStephen Boyd static struct clk_branch camss_csi1_clk = { 2834c2526597SStephen Boyd .halt_reg = 0x3124, 2835c2526597SStephen Boyd .clkr = { 2836c2526597SStephen Boyd .enable_reg = 0x3124, 2837c2526597SStephen Boyd .enable_mask = BIT(0), 2838c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2839c2526597SStephen Boyd .name = "camss_csi1_clk", 2840*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2841*e7c65912SDmitry Baryshkov &csi1_clk_src.clkr.hw 2842*e7c65912SDmitry Baryshkov }, 2843c2526597SStephen Boyd .num_parents = 1, 2844c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2845c2526597SStephen Boyd .ops = &clk_branch2_ops, 2846c2526597SStephen Boyd }, 2847c2526597SStephen Boyd }, 2848c2526597SStephen Boyd }; 2849c2526597SStephen Boyd 2850c2526597SStephen Boyd static struct clk_branch camss_csi1_ahb_clk = { 2851c2526597SStephen Boyd .halt_reg = 0x3128, 2852c2526597SStephen Boyd .clkr = { 2853c2526597SStephen Boyd .enable_reg = 0x3128, 2854c2526597SStephen Boyd .enable_mask = BIT(0), 2855c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2856c2526597SStephen Boyd .name = "camss_csi1_ahb_clk", 2857*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2858*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2859*e7c65912SDmitry Baryshkov }, 2860c2526597SStephen Boyd .num_parents = 1, 2861c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2862c2526597SStephen Boyd .ops = &clk_branch2_ops, 2863c2526597SStephen Boyd }, 2864c2526597SStephen Boyd }, 2865c2526597SStephen Boyd }; 2866c2526597SStephen Boyd 2867c2526597SStephen Boyd static struct clk_branch camss_csi1phy_clk = { 2868c2526597SStephen Boyd .halt_reg = 0x3134, 2869c2526597SStephen Boyd .clkr = { 2870c2526597SStephen Boyd .enable_reg = 0x3134, 2871c2526597SStephen Boyd .enable_mask = BIT(0), 2872c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2873c2526597SStephen Boyd .name = "camss_csi1phy_clk", 2874*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2875*e7c65912SDmitry Baryshkov &csi1_clk_src.clkr.hw 2876*e7c65912SDmitry Baryshkov }, 2877c2526597SStephen Boyd .num_parents = 1, 2878c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2879c2526597SStephen Boyd .ops = &clk_branch2_ops, 2880c2526597SStephen Boyd }, 2881c2526597SStephen Boyd }, 2882c2526597SStephen Boyd }; 2883c2526597SStephen Boyd 2884c2526597SStephen Boyd static struct clk_branch camss_csi1rdi_clk = { 2885c2526597SStephen Boyd .halt_reg = 0x3144, 2886c2526597SStephen Boyd .clkr = { 2887c2526597SStephen Boyd .enable_reg = 0x3144, 2888c2526597SStephen Boyd .enable_mask = BIT(0), 2889c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2890c2526597SStephen Boyd .name = "camss_csi1rdi_clk", 2891*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2892*e7c65912SDmitry Baryshkov &csi1_clk_src.clkr.hw 2893*e7c65912SDmitry Baryshkov }, 2894c2526597SStephen Boyd .num_parents = 1, 2895c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2896c2526597SStephen Boyd .ops = &clk_branch2_ops, 2897c2526597SStephen Boyd }, 2898c2526597SStephen Boyd }, 2899c2526597SStephen Boyd }; 2900c2526597SStephen Boyd 2901c2526597SStephen Boyd static struct clk_branch camss_csi1pix_clk = { 2902c2526597SStephen Boyd .halt_reg = 0x3154, 2903c2526597SStephen Boyd .clkr = { 2904c2526597SStephen Boyd .enable_reg = 0x3154, 2905c2526597SStephen Boyd .enable_mask = BIT(0), 2906c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2907c2526597SStephen Boyd .name = "camss_csi1pix_clk", 2908*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2909*e7c65912SDmitry Baryshkov &csi1_clk_src.clkr.hw 2910*e7c65912SDmitry Baryshkov }, 2911c2526597SStephen Boyd .num_parents = 1, 2912c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2913c2526597SStephen Boyd .ops = &clk_branch2_ops, 2914c2526597SStephen Boyd }, 2915c2526597SStephen Boyd }, 2916c2526597SStephen Boyd }; 2917c2526597SStephen Boyd 2918c2526597SStephen Boyd static struct clk_branch camss_csi2_clk = { 2919c2526597SStephen Boyd .halt_reg = 0x3184, 2920c2526597SStephen Boyd .clkr = { 2921c2526597SStephen Boyd .enable_reg = 0x3184, 2922c2526597SStephen Boyd .enable_mask = BIT(0), 2923c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2924c2526597SStephen Boyd .name = "camss_csi2_clk", 2925*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2926*e7c65912SDmitry Baryshkov &csi2_clk_src.clkr.hw 2927*e7c65912SDmitry Baryshkov }, 2928c2526597SStephen Boyd .num_parents = 1, 2929c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2930c2526597SStephen Boyd .ops = &clk_branch2_ops, 2931c2526597SStephen Boyd }, 2932c2526597SStephen Boyd }, 2933c2526597SStephen Boyd }; 2934c2526597SStephen Boyd 2935c2526597SStephen Boyd static struct clk_branch camss_csi2_ahb_clk = { 2936c2526597SStephen Boyd .halt_reg = 0x3188, 2937c2526597SStephen Boyd .clkr = { 2938c2526597SStephen Boyd .enable_reg = 0x3188, 2939c2526597SStephen Boyd .enable_mask = BIT(0), 2940c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2941c2526597SStephen Boyd .name = "camss_csi2_ahb_clk", 2942*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2943*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 2944*e7c65912SDmitry Baryshkov }, 2945c2526597SStephen Boyd .num_parents = 1, 2946c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2947c2526597SStephen Boyd .ops = &clk_branch2_ops, 2948c2526597SStephen Boyd }, 2949c2526597SStephen Boyd }, 2950c2526597SStephen Boyd }; 2951c2526597SStephen Boyd 2952c2526597SStephen Boyd static struct clk_branch camss_csi2phy_clk = { 2953c2526597SStephen Boyd .halt_reg = 0x3194, 2954c2526597SStephen Boyd .clkr = { 2955c2526597SStephen Boyd .enable_reg = 0x3194, 2956c2526597SStephen Boyd .enable_mask = BIT(0), 2957c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2958c2526597SStephen Boyd .name = "camss_csi2phy_clk", 2959*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2960*e7c65912SDmitry Baryshkov &csi2_clk_src.clkr.hw 2961*e7c65912SDmitry Baryshkov }, 2962c2526597SStephen Boyd .num_parents = 1, 2963c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2964c2526597SStephen Boyd .ops = &clk_branch2_ops, 2965c2526597SStephen Boyd }, 2966c2526597SStephen Boyd }, 2967c2526597SStephen Boyd }; 2968c2526597SStephen Boyd 2969c2526597SStephen Boyd static struct clk_branch camss_csi2rdi_clk = { 2970c2526597SStephen Boyd .halt_reg = 0x31a4, 2971c2526597SStephen Boyd .clkr = { 2972c2526597SStephen Boyd .enable_reg = 0x31a4, 2973c2526597SStephen Boyd .enable_mask = BIT(0), 2974c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2975c2526597SStephen Boyd .name = "camss_csi2rdi_clk", 2976*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2977*e7c65912SDmitry Baryshkov &csi2_clk_src.clkr.hw 2978*e7c65912SDmitry Baryshkov }, 2979c2526597SStephen Boyd .num_parents = 1, 2980c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2981c2526597SStephen Boyd .ops = &clk_branch2_ops, 2982c2526597SStephen Boyd }, 2983c2526597SStephen Boyd }, 2984c2526597SStephen Boyd }; 2985c2526597SStephen Boyd 2986c2526597SStephen Boyd static struct clk_branch camss_csi2pix_clk = { 2987c2526597SStephen Boyd .halt_reg = 0x31b4, 2988c2526597SStephen Boyd .clkr = { 2989c2526597SStephen Boyd .enable_reg = 0x31b4, 2990c2526597SStephen Boyd .enable_mask = BIT(0), 2991c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2992c2526597SStephen Boyd .name = "camss_csi2pix_clk", 2993*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 2994*e7c65912SDmitry Baryshkov &csi2_clk_src.clkr.hw 2995*e7c65912SDmitry Baryshkov }, 2996c2526597SStephen Boyd .num_parents = 1, 2997c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2998c2526597SStephen Boyd .ops = &clk_branch2_ops, 2999c2526597SStephen Boyd }, 3000c2526597SStephen Boyd }, 3001c2526597SStephen Boyd }; 3002c2526597SStephen Boyd 3003c2526597SStephen Boyd static struct clk_branch camss_csi3_clk = { 3004c2526597SStephen Boyd .halt_reg = 0x31e4, 3005c2526597SStephen Boyd .clkr = { 3006c2526597SStephen Boyd .enable_reg = 0x31e4, 3007c2526597SStephen Boyd .enable_mask = BIT(0), 3008c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 3009c2526597SStephen Boyd .name = "camss_csi3_clk", 3010*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 3011*e7c65912SDmitry Baryshkov &csi3_clk_src.clkr.hw 3012*e7c65912SDmitry Baryshkov }, 3013c2526597SStephen Boyd .num_parents = 1, 3014c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 3015c2526597SStephen Boyd .ops = &clk_branch2_ops, 3016c2526597SStephen Boyd }, 3017c2526597SStephen Boyd }, 3018c2526597SStephen Boyd }; 3019c2526597SStephen Boyd 3020c2526597SStephen Boyd static struct clk_branch camss_csi3_ahb_clk = { 3021c2526597SStephen Boyd .halt_reg = 0x31e8, 3022c2526597SStephen Boyd .clkr = { 3023c2526597SStephen Boyd .enable_reg = 0x31e8, 3024c2526597SStephen Boyd .enable_mask = BIT(0), 3025c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 3026c2526597SStephen Boyd .name = "camss_csi3_ahb_clk", 3027*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 3028*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 3029*e7c65912SDmitry Baryshkov }, 3030c2526597SStephen Boyd .num_parents = 1, 3031c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 3032c2526597SStephen Boyd .ops = &clk_branch2_ops, 3033c2526597SStephen Boyd }, 3034c2526597SStephen Boyd }, 3035c2526597SStephen Boyd }; 3036c2526597SStephen Boyd 3037c2526597SStephen Boyd static struct clk_branch camss_csi3phy_clk = { 3038c2526597SStephen Boyd .halt_reg = 0x31f4, 3039c2526597SStephen Boyd .clkr = { 3040c2526597SStephen Boyd .enable_reg = 0x31f4, 3041c2526597SStephen Boyd .enable_mask = BIT(0), 3042c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 3043c2526597SStephen Boyd .name = "camss_csi3phy_clk", 3044*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 3045*e7c65912SDmitry Baryshkov &csi3_clk_src.clkr.hw 3046*e7c65912SDmitry Baryshkov }, 3047c2526597SStephen Boyd .num_parents = 1, 3048c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 3049c2526597SStephen Boyd .ops = &clk_branch2_ops, 3050c2526597SStephen Boyd }, 3051c2526597SStephen Boyd }, 3052c2526597SStephen Boyd }; 3053c2526597SStephen Boyd 3054c2526597SStephen Boyd static struct clk_branch camss_csi3rdi_clk = { 3055c2526597SStephen Boyd .halt_reg = 0x3204, 3056c2526597SStephen Boyd .clkr = { 3057c2526597SStephen Boyd .enable_reg = 0x3204, 3058c2526597SStephen Boyd .enable_mask = BIT(0), 3059c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 3060c2526597SStephen Boyd .name = "camss_csi3rdi_clk", 3061*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 3062*e7c65912SDmitry Baryshkov &csi3_clk_src.clkr.hw 3063*e7c65912SDmitry Baryshkov }, 3064c2526597SStephen Boyd .num_parents = 1, 3065c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 3066c2526597SStephen Boyd .ops = &clk_branch2_ops, 3067c2526597SStephen Boyd }, 3068c2526597SStephen Boyd }, 3069c2526597SStephen Boyd }; 3070c2526597SStephen Boyd 3071c2526597SStephen Boyd static struct clk_branch camss_csi3pix_clk = { 3072c2526597SStephen Boyd .halt_reg = 0x3214, 3073c2526597SStephen Boyd .clkr = { 3074c2526597SStephen Boyd .enable_reg = 0x3214, 3075c2526597SStephen Boyd .enable_mask = BIT(0), 3076c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 3077c2526597SStephen Boyd .name = "camss_csi3pix_clk", 3078*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 3079*e7c65912SDmitry Baryshkov &csi3_clk_src.clkr.hw 3080*e7c65912SDmitry Baryshkov }, 3081c2526597SStephen Boyd .num_parents = 1, 3082c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 3083c2526597SStephen Boyd .ops = &clk_branch2_ops, 3084c2526597SStephen Boyd }, 3085c2526597SStephen Boyd }, 3086c2526597SStephen Boyd }; 3087c2526597SStephen Boyd 3088c2526597SStephen Boyd static struct clk_branch camss_ispif_ahb_clk = { 3089c2526597SStephen Boyd .halt_reg = 0x3224, 3090c2526597SStephen Boyd .clkr = { 3091c2526597SStephen Boyd .enable_reg = 0x3224, 3092c2526597SStephen Boyd .enable_mask = BIT(0), 3093c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 3094c2526597SStephen Boyd .name = "camss_ispif_ahb_clk", 3095*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 3096*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 3097*e7c65912SDmitry Baryshkov }, 3098c2526597SStephen Boyd .num_parents = 1, 3099c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 3100c2526597SStephen Boyd .ops = &clk_branch2_ops, 3101c2526597SStephen Boyd }, 3102c2526597SStephen Boyd }, 3103c2526597SStephen Boyd }; 3104c2526597SStephen Boyd 3105c2526597SStephen Boyd static struct clk_branch fd_core_clk = { 3106c2526597SStephen Boyd .halt_reg = 0x3b68, 3107c2526597SStephen Boyd .clkr = { 3108c2526597SStephen Boyd .enable_reg = 0x3b68, 3109c2526597SStephen Boyd .enable_mask = BIT(0), 3110c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 3111c2526597SStephen Boyd .name = "fd_core_clk", 3112*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 3113*e7c65912SDmitry Baryshkov &fd_core_clk_src.clkr.hw 3114*e7c65912SDmitry Baryshkov }, 3115c2526597SStephen Boyd .num_parents = 1, 3116c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 3117c2526597SStephen Boyd .ops = &clk_branch2_ops, 3118c2526597SStephen Boyd }, 3119c2526597SStephen Boyd }, 3120c2526597SStephen Boyd }; 3121c2526597SStephen Boyd 3122c2526597SStephen Boyd static struct clk_branch fd_core_uar_clk = { 3123c2526597SStephen Boyd .halt_reg = 0x3b6c, 3124c2526597SStephen Boyd .clkr = { 3125c2526597SStephen Boyd .enable_reg = 0x3b6c, 3126c2526597SStephen Boyd .enable_mask = BIT(0), 3127c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 3128c2526597SStephen Boyd .name = "fd_core_uar_clk", 3129*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 3130*e7c65912SDmitry Baryshkov &fd_core_clk_src.clkr.hw 3131*e7c65912SDmitry Baryshkov }, 3132c2526597SStephen Boyd .num_parents = 1, 3133c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 3134c2526597SStephen Boyd .ops = &clk_branch2_ops, 3135c2526597SStephen Boyd }, 3136c2526597SStephen Boyd }, 3137c2526597SStephen Boyd }; 3138c2526597SStephen Boyd 3139c2526597SStephen Boyd static struct clk_branch fd_ahb_clk = { 3140c2526597SStephen Boyd .halt_reg = 0x3ba74, 3141c2526597SStephen Boyd .clkr = { 3142c2526597SStephen Boyd .enable_reg = 0x3ba74, 3143c2526597SStephen Boyd .enable_mask = BIT(0), 3144c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 3145c2526597SStephen Boyd .name = "fd_ahb_clk", 3146*e7c65912SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 3147*e7c65912SDmitry Baryshkov &ahb_clk_src.clkr.hw 3148*e7c65912SDmitry Baryshkov }, 3149c2526597SStephen Boyd .num_parents = 1, 3150c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 3151c2526597SStephen Boyd .ops = &clk_branch2_ops, 3152c2526597SStephen Boyd }, 3153c2526597SStephen Boyd }, 3154c2526597SStephen Boyd }; 3155c2526597SStephen Boyd 3156c2526597SStephen Boyd static struct clk_hw *mmcc_msm8996_hws[] = { 3157c2526597SStephen Boyd &gpll0_div.hw, 3158c2526597SStephen Boyd }; 3159c2526597SStephen Boyd 316063bb4fd6SRajendra Nayak static struct gdsc mmagic_bimc_gdsc = { 316163bb4fd6SRajendra Nayak .gdscr = 0x529c, 316263bb4fd6SRajendra Nayak .pd = { 316363bb4fd6SRajendra Nayak .name = "mmagic_bimc", 316463bb4fd6SRajendra Nayak }, 316563bb4fd6SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 316653f3abe9SVivek Gautam .flags = ALWAYS_ON, 316763bb4fd6SRajendra Nayak }; 316863bb4fd6SRajendra Nayak 31697e824d50SRajendra Nayak static struct gdsc mmagic_video_gdsc = { 31707e824d50SRajendra Nayak .gdscr = 0x119c, 31717e824d50SRajendra Nayak .gds_hw_ctrl = 0x120c, 31727e824d50SRajendra Nayak .pd = { 31737e824d50SRajendra Nayak .name = "mmagic_video", 31747e824d50SRajendra Nayak }, 31757e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 31767705bb71SRajendra Nayak .flags = VOTABLE | ALWAYS_ON, 31777e824d50SRajendra Nayak }; 31787e824d50SRajendra Nayak 31797e824d50SRajendra Nayak static struct gdsc mmagic_mdss_gdsc = { 31807e824d50SRajendra Nayak .gdscr = 0x247c, 31817e824d50SRajendra Nayak .gds_hw_ctrl = 0x2480, 31827e824d50SRajendra Nayak .pd = { 31837e824d50SRajendra Nayak .name = "mmagic_mdss", 31847e824d50SRajendra Nayak }, 31857e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 31867705bb71SRajendra Nayak .flags = VOTABLE | ALWAYS_ON, 31877e824d50SRajendra Nayak }; 31887e824d50SRajendra Nayak 31897e824d50SRajendra Nayak static struct gdsc mmagic_camss_gdsc = { 31907e824d50SRajendra Nayak .gdscr = 0x3c4c, 31917e824d50SRajendra Nayak .gds_hw_ctrl = 0x3c50, 31927e824d50SRajendra Nayak .pd = { 31937e824d50SRajendra Nayak .name = "mmagic_camss", 31947e824d50SRajendra Nayak }, 31957e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 31967705bb71SRajendra Nayak .flags = VOTABLE | ALWAYS_ON, 31977e824d50SRajendra Nayak }; 31987e824d50SRajendra Nayak 31997e824d50SRajendra Nayak static struct gdsc venus_gdsc = { 32007e824d50SRajendra Nayak .gdscr = 0x1024, 32017e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 }, 32027e824d50SRajendra Nayak .cxc_count = 3, 32037e824d50SRajendra Nayak .pd = { 32047e824d50SRajendra Nayak .name = "venus", 32057e824d50SRajendra Nayak }, 32067e824d50SRajendra Nayak .parent = &mmagic_video_gdsc.pd, 32077e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 32087e824d50SRajendra Nayak }; 32097e824d50SRajendra Nayak 32107e824d50SRajendra Nayak static struct gdsc venus_core0_gdsc = { 32117e824d50SRajendra Nayak .gdscr = 0x1040, 32127e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x1048 }, 32137e824d50SRajendra Nayak .cxc_count = 1, 32147e824d50SRajendra Nayak .pd = { 32157e824d50SRajendra Nayak .name = "venus_core0", 32167e824d50SRajendra Nayak }, 32174a43e35dSStanimir Varbanov .parent = &venus_gdsc.pd, 32187e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 321996893e10SSricharan R .flags = HW_CTRL, 32207e824d50SRajendra Nayak }; 32217e824d50SRajendra Nayak 32227e824d50SRajendra Nayak static struct gdsc venus_core1_gdsc = { 32237e824d50SRajendra Nayak .gdscr = 0x1044, 32247e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x104c }, 32257e824d50SRajendra Nayak .cxc_count = 1, 32267e824d50SRajendra Nayak .pd = { 32277e824d50SRajendra Nayak .name = "venus_core1", 32287e824d50SRajendra Nayak }, 32294a43e35dSStanimir Varbanov .parent = &venus_gdsc.pd, 32307e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 323196893e10SSricharan R .flags = HW_CTRL, 32327e824d50SRajendra Nayak }; 32337e824d50SRajendra Nayak 32347e824d50SRajendra Nayak static struct gdsc camss_gdsc = { 32357e824d50SRajendra Nayak .gdscr = 0x34a0, 32367e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36bc, 0x36c4 }, 32377e824d50SRajendra Nayak .cxc_count = 2, 32387e824d50SRajendra Nayak .pd = { 32397e824d50SRajendra Nayak .name = "camss", 32407e824d50SRajendra Nayak }, 32417e824d50SRajendra Nayak .parent = &mmagic_camss_gdsc.pd, 32427e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 32437e824d50SRajendra Nayak }; 32447e824d50SRajendra Nayak 32457e824d50SRajendra Nayak static struct gdsc vfe0_gdsc = { 32467e824d50SRajendra Nayak .gdscr = 0x3664, 32477e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36a8 }, 32487e824d50SRajendra Nayak .cxc_count = 1, 32497e824d50SRajendra Nayak .pd = { 32507e824d50SRajendra Nayak .name = "vfe0", 32517e824d50SRajendra Nayak }, 32527e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 32537e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 32547e824d50SRajendra Nayak }; 32557e824d50SRajendra Nayak 32567e824d50SRajendra Nayak static struct gdsc vfe1_gdsc = { 32577e824d50SRajendra Nayak .gdscr = 0x3674, 32587e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36ac }, 32597e824d50SRajendra Nayak .cxc_count = 1, 32607e824d50SRajendra Nayak .pd = { 3261a62ca337SRajendra Nayak .name = "vfe1", 32627e824d50SRajendra Nayak }, 32637e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 32647e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 32657e824d50SRajendra Nayak }; 32667e824d50SRajendra Nayak 32677e824d50SRajendra Nayak static struct gdsc jpeg_gdsc = { 32687e824d50SRajendra Nayak .gdscr = 0x35a4, 32697e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 }, 32707e824d50SRajendra Nayak .cxc_count = 4, 32717e824d50SRajendra Nayak .pd = { 32727e824d50SRajendra Nayak .name = "jpeg", 32737e824d50SRajendra Nayak }, 32747e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 32757e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 32767e824d50SRajendra Nayak }; 32777e824d50SRajendra Nayak 32787e824d50SRajendra Nayak static struct gdsc cpp_gdsc = { 32797e824d50SRajendra Nayak .gdscr = 0x36d4, 32807e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36b0 }, 32817e824d50SRajendra Nayak .cxc_count = 1, 32827e824d50SRajendra Nayak .pd = { 32837e824d50SRajendra Nayak .name = "cpp", 32847e824d50SRajendra Nayak }, 32857e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 32867e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 32877e824d50SRajendra Nayak }; 32887e824d50SRajendra Nayak 32897e824d50SRajendra Nayak static struct gdsc fd_gdsc = { 32907e824d50SRajendra Nayak .gdscr = 0x3b64, 32917e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x3b68, 0x3b6c }, 32927e824d50SRajendra Nayak .cxc_count = 2, 32937e824d50SRajendra Nayak .pd = { 32947e824d50SRajendra Nayak .name = "fd", 32957e824d50SRajendra Nayak }, 32967e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 32977e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 32987e824d50SRajendra Nayak }; 32997e824d50SRajendra Nayak 33007e824d50SRajendra Nayak static struct gdsc mdss_gdsc = { 33017e824d50SRajendra Nayak .gdscr = 0x2304, 33027e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x2310, 0x231c }, 33037e824d50SRajendra Nayak .cxc_count = 2, 33047e824d50SRajendra Nayak .pd = { 33057e824d50SRajendra Nayak .name = "mdss", 33067e824d50SRajendra Nayak }, 33077e824d50SRajendra Nayak .parent = &mmagic_mdss_gdsc.pd, 33087e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 33097e824d50SRajendra Nayak }; 33107e824d50SRajendra Nayak 33114154f619SRajendra Nayak static struct gdsc gpu_gdsc = { 33124154f619SRajendra Nayak .gdscr = 0x4034, 33134154f619SRajendra Nayak .gds_hw_ctrl = 0x4038, 33144154f619SRajendra Nayak .pd = { 33154154f619SRajendra Nayak .name = "gpu", 33164154f619SRajendra Nayak }, 33174154f619SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 33184154f619SRajendra Nayak .flags = VOTABLE, 33194154f619SRajendra Nayak }; 33204154f619SRajendra Nayak 33214154f619SRajendra Nayak static struct gdsc gpu_gx_gdsc = { 33224154f619SRajendra Nayak .gdscr = 0x4024, 33234154f619SRajendra Nayak .clamp_io_ctrl = 0x4300, 33244154f619SRajendra Nayak .cxcs = (unsigned int []){ 0x4028 }, 33254154f619SRajendra Nayak .cxc_count = 1, 33264154f619SRajendra Nayak .pd = { 33274154f619SRajendra Nayak .name = "gpu_gx", 33284154f619SRajendra Nayak }, 33294154f619SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 333090a3691eSBjorn Andersson .parent = &gpu_gdsc.pd, 33314154f619SRajendra Nayak .flags = CLAMP_IO, 333290a3691eSBjorn Andersson .supply = "vdd-gfx", 33334154f619SRajendra Nayak }; 33344154f619SRajendra Nayak 3335c2526597SStephen Boyd static struct clk_regmap *mmcc_msm8996_clocks[] = { 3336c2526597SStephen Boyd [MMPLL0_EARLY] = &mmpll0_early.clkr, 3337c2526597SStephen Boyd [MMPLL0_PLL] = &mmpll0.clkr, 3338c2526597SStephen Boyd [MMPLL1_EARLY] = &mmpll1_early.clkr, 3339c2526597SStephen Boyd [MMPLL1_PLL] = &mmpll1.clkr, 3340c2526597SStephen Boyd [MMPLL2_EARLY] = &mmpll2_early.clkr, 3341c2526597SStephen Boyd [MMPLL2_PLL] = &mmpll2.clkr, 3342c2526597SStephen Boyd [MMPLL3_EARLY] = &mmpll3_early.clkr, 3343c2526597SStephen Boyd [MMPLL3_PLL] = &mmpll3.clkr, 3344c2526597SStephen Boyd [MMPLL4_EARLY] = &mmpll4_early.clkr, 3345c2526597SStephen Boyd [MMPLL4_PLL] = &mmpll4.clkr, 3346c2526597SStephen Boyd [MMPLL5_EARLY] = &mmpll5_early.clkr, 3347c2526597SStephen Boyd [MMPLL5_PLL] = &mmpll5.clkr, 3348c2526597SStephen Boyd [MMPLL8_EARLY] = &mmpll8_early.clkr, 3349c2526597SStephen Boyd [MMPLL8_PLL] = &mmpll8.clkr, 3350c2526597SStephen Boyd [MMPLL9_EARLY] = &mmpll9_early.clkr, 3351c2526597SStephen Boyd [MMPLL9_PLL] = &mmpll9.clkr, 3352c2526597SStephen Boyd [AHB_CLK_SRC] = &ahb_clk_src.clkr, 3353c2526597SStephen Boyd [AXI_CLK_SRC] = &axi_clk_src.clkr, 3354c2526597SStephen Boyd [MAXI_CLK_SRC] = &maxi_clk_src.clkr, 3355eaf87e56SAngeloGioacchino Del Regno [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr, 3356c2526597SStephen Boyd [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 3357c2526597SStephen Boyd [ISENSE_CLK_SRC] = &isense_clk_src.clkr, 3358c2526597SStephen Boyd [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 3359c2526597SStephen Boyd [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, 3360c2526597SStephen Boyd [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr, 3361c2526597SStephen Boyd [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr, 3362c2526597SStephen Boyd [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3363c2526597SStephen Boyd [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 3364c2526597SStephen Boyd [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3365c2526597SStephen Boyd [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 3366c2526597SStephen Boyd [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3367c2526597SStephen Boyd [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 3368c2526597SStephen Boyd [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3369c2526597SStephen Boyd [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 3370c2526597SStephen Boyd [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3371c2526597SStephen Boyd [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 3372c2526597SStephen Boyd [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3373c2526597SStephen Boyd [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3374c2526597SStephen Boyd [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3375c2526597SStephen Boyd [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3376c2526597SStephen Boyd [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 3377c2526597SStephen Boyd [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 3378c2526597SStephen Boyd [CCI_CLK_SRC] = &cci_clk_src.clkr, 3379c2526597SStephen Boyd [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3380c2526597SStephen Boyd [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3381c2526597SStephen Boyd [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 3382c2526597SStephen Boyd [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr, 3383c2526597SStephen Boyd [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr, 3384c2526597SStephen Boyd [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr, 3385c2526597SStephen Boyd [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3386c2526597SStephen Boyd [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, 3387c2526597SStephen Boyd [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr, 3388c2526597SStephen Boyd [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3389c2526597SStephen Boyd [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 3390c2526597SStephen Boyd [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3391c2526597SStephen Boyd [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3392c2526597SStephen Boyd [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3393c2526597SStephen Boyd [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 3394c2526597SStephen Boyd [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 3395c2526597SStephen Boyd [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr, 3396c2526597SStephen Boyd [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr, 3397c2526597SStephen Boyd [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr, 3398c2526597SStephen Boyd [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, 3399c2526597SStephen Boyd [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, 3400c2526597SStephen Boyd [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr, 3401c2526597SStephen Boyd [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr, 3402c2526597SStephen Boyd [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr, 3403c2526597SStephen Boyd [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr, 3404c2526597SStephen Boyd [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr, 3405c2526597SStephen Boyd [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr, 3406c2526597SStephen Boyd [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr, 3407c2526597SStephen Boyd [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr, 3408c2526597SStephen Boyd [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr, 3409c2526597SStephen Boyd [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr, 3410c2526597SStephen Boyd [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr, 3411c2526597SStephen Boyd [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr, 3412c2526597SStephen Boyd [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr, 3413c2526597SStephen Boyd [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr, 3414c2526597SStephen Boyd [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr, 3415c2526597SStephen Boyd [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr, 3416c2526597SStephen Boyd [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr, 3417c2526597SStephen Boyd [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr, 3418c2526597SStephen Boyd [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr, 3419c2526597SStephen Boyd [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr, 3420c2526597SStephen Boyd [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr, 3421c2526597SStephen Boyd [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr, 3422c2526597SStephen Boyd [GPU_AHB_CLK] = &gpu_ahb_clk.clkr, 3423c2526597SStephen Boyd [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr, 3424c2526597SStephen Boyd [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr, 3425c2526597SStephen Boyd [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr, 3426c2526597SStephen Boyd [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr, 3427c2526597SStephen Boyd [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr, 3428c2526597SStephen Boyd [VIDEO_CORE_CLK] = &video_core_clk.clkr, 3429c2526597SStephen Boyd [VIDEO_AXI_CLK] = &video_axi_clk.clkr, 3430c2526597SStephen Boyd [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr, 3431c2526597SStephen Boyd [VIDEO_AHB_CLK] = &video_ahb_clk.clkr, 3432c2526597SStephen Boyd [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr, 3433c2526597SStephen Boyd [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr, 3434c2526597SStephen Boyd [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 3435c2526597SStephen Boyd [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, 3436c2526597SStephen Boyd [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 3437c2526597SStephen Boyd [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 3438c2526597SStephen Boyd [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 3439c2526597SStephen Boyd [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 3440c2526597SStephen Boyd [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 3441c2526597SStephen Boyd [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 3442c2526597SStephen Boyd [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 3443c2526597SStephen Boyd [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 3444c2526597SStephen Boyd [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 3445c2526597SStephen Boyd [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 3446c2526597SStephen Boyd [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 3447c2526597SStephen Boyd [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 3448c2526597SStephen Boyd [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, 3449c2526597SStephen Boyd [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 3450c2526597SStephen Boyd [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 3451c2526597SStephen Boyd [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 3452c2526597SStephen Boyd [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 3453c2526597SStephen Boyd [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 3454c2526597SStephen Boyd [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 3455c2526597SStephen Boyd [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 3456c2526597SStephen Boyd [CAMSS_CCI_CLK] = &camss_cci_clk.clkr, 3457c2526597SStephen Boyd [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr, 3458c2526597SStephen Boyd [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr, 3459c2526597SStephen Boyd [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr, 3460c2526597SStephen Boyd [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr, 3461c2526597SStephen Boyd [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr, 3462c2526597SStephen Boyd [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr, 3463c2526597SStephen Boyd [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr, 3464c2526597SStephen Boyd [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr, 3465c2526597SStephen Boyd [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr, 3466c2526597SStephen Boyd [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr, 3467c2526597SStephen Boyd [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr, 3468c2526597SStephen Boyd [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr, 3469c2526597SStephen Boyd [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr, 3470c2526597SStephen Boyd [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr, 3471c2526597SStephen Boyd [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr, 3472c2526597SStephen Boyd [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr, 3473c2526597SStephen Boyd [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr, 3474c2526597SStephen Boyd [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr, 3475c2526597SStephen Boyd [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr, 3476c2526597SStephen Boyd [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr, 3477c2526597SStephen Boyd [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 3478c2526597SStephen Boyd [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 3479c2526597SStephen Boyd [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr, 3480c2526597SStephen Boyd [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr, 3481c2526597SStephen Boyd [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr, 3482c2526597SStephen Boyd [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr, 3483c2526597SStephen Boyd [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 3484c2526597SStephen Boyd [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 3485c2526597SStephen Boyd [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, 3486c2526597SStephen Boyd [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 3487c2526597SStephen Boyd [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 3488c2526597SStephen Boyd [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 3489c2526597SStephen Boyd [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 3490c2526597SStephen Boyd [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, 3491c2526597SStephen Boyd [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 3492c2526597SStephen Boyd [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 3493c2526597SStephen Boyd [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 3494c2526597SStephen Boyd [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 3495c2526597SStephen Boyd [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, 3496c2526597SStephen Boyd [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 3497c2526597SStephen Boyd [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 3498c2526597SStephen Boyd [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 3499c2526597SStephen Boyd [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 3500c2526597SStephen Boyd [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, 3501c2526597SStephen Boyd [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 3502c2526597SStephen Boyd [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 3503c2526597SStephen Boyd [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 3504c2526597SStephen Boyd [FD_CORE_CLK] = &fd_core_clk.clkr, 3505c2526597SStephen Boyd [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr, 3506c2526597SStephen Boyd [FD_AHB_CLK] = &fd_ahb_clk.clkr, 3507c2526597SStephen Boyd }; 3508c2526597SStephen Boyd 35097e824d50SRajendra Nayak static struct gdsc *mmcc_msm8996_gdscs[] = { 351063bb4fd6SRajendra Nayak [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc, 35117e824d50SRajendra Nayak [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc, 35127e824d50SRajendra Nayak [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc, 35137e824d50SRajendra Nayak [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc, 35147e824d50SRajendra Nayak [VENUS_GDSC] = &venus_gdsc, 35157e824d50SRajendra Nayak [VENUS_CORE0_GDSC] = &venus_core0_gdsc, 35167e824d50SRajendra Nayak [VENUS_CORE1_GDSC] = &venus_core1_gdsc, 35177e824d50SRajendra Nayak [CAMSS_GDSC] = &camss_gdsc, 35187e824d50SRajendra Nayak [VFE0_GDSC] = &vfe0_gdsc, 35197e824d50SRajendra Nayak [VFE1_GDSC] = &vfe1_gdsc, 35207e824d50SRajendra Nayak [JPEG_GDSC] = &jpeg_gdsc, 35217e824d50SRajendra Nayak [CPP_GDSC] = &cpp_gdsc, 35227e824d50SRajendra Nayak [FD_GDSC] = &fd_gdsc, 35237e824d50SRajendra Nayak [MDSS_GDSC] = &mdss_gdsc, 35244154f619SRajendra Nayak [GPU_GDSC] = &gpu_gdsc, 35254154f619SRajendra Nayak [GPU_GX_GDSC] = &gpu_gx_gdsc, 35267e824d50SRajendra Nayak }; 35277e824d50SRajendra Nayak 3528c2526597SStephen Boyd static const struct qcom_reset_map mmcc_msm8996_resets[] = { 3529c2526597SStephen Boyd [MMAGICAHB_BCR] = { 0x5020 }, 3530c2526597SStephen Boyd [MMAGIC_CFG_BCR] = { 0x5050 }, 3531c2526597SStephen Boyd [MISC_BCR] = { 0x5010 }, 3532c2526597SStephen Boyd [BTO_BCR] = { 0x5030 }, 3533c2526597SStephen Boyd [MMAGICAXI_BCR] = { 0x5060 }, 3534c2526597SStephen Boyd [MMAGICMAXI_BCR] = { 0x5070 }, 3535c2526597SStephen Boyd [DSA_BCR] = { 0x50a0 }, 3536c2526597SStephen Boyd [MMAGIC_CAMSS_BCR] = { 0x3c40 }, 3537c2526597SStephen Boyd [THROTTLE_CAMSS_BCR] = { 0x3c30 }, 3538c2526597SStephen Boyd [SMMU_VFE_BCR] = { 0x3c00 }, 3539c2526597SStephen Boyd [SMMU_CPP_BCR] = { 0x3c10 }, 3540c2526597SStephen Boyd [SMMU_JPEG_BCR] = { 0x3c20 }, 3541c2526597SStephen Boyd [MMAGIC_MDSS_BCR] = { 0x2470 }, 3542c2526597SStephen Boyd [THROTTLE_MDSS_BCR] = { 0x2460 }, 3543c2526597SStephen Boyd [SMMU_ROT_BCR] = { 0x2440 }, 3544c2526597SStephen Boyd [SMMU_MDP_BCR] = { 0x2450 }, 3545c2526597SStephen Boyd [MMAGIC_VIDEO_BCR] = { 0x1190 }, 3546c2526597SStephen Boyd [THROTTLE_VIDEO_BCR] = { 0x1180 }, 3547c2526597SStephen Boyd [SMMU_VIDEO_BCR] = { 0x1170 }, 3548c2526597SStephen Boyd [MMAGIC_BIMC_BCR] = { 0x5290 }, 3549c2526597SStephen Boyd [GPU_GX_BCR] = { 0x4020 }, 3550c2526597SStephen Boyd [GPU_BCR] = { 0x4030 }, 3551c2526597SStephen Boyd [GPU_AON_BCR] = { 0x4040 }, 3552c2526597SStephen Boyd [VMEM_BCR] = { 0x1200 }, 3553c2526597SStephen Boyd [MMSS_RBCPR_BCR] = { 0x4080 }, 3554c2526597SStephen Boyd [VIDEO_BCR] = { 0x1020 }, 3555c2526597SStephen Boyd [MDSS_BCR] = { 0x2300 }, 3556c2526597SStephen Boyd [CAMSS_TOP_BCR] = { 0x3480 }, 3557c2526597SStephen Boyd [CAMSS_AHB_BCR] = { 0x3488 }, 3558c2526597SStephen Boyd [CAMSS_MICRO_BCR] = { 0x3490 }, 3559c2526597SStephen Boyd [CAMSS_CCI_BCR] = { 0x3340 }, 3560c2526597SStephen Boyd [CAMSS_PHY0_BCR] = { 0x3020 }, 3561c2526597SStephen Boyd [CAMSS_PHY1_BCR] = { 0x3050 }, 3562c2526597SStephen Boyd [CAMSS_PHY2_BCR] = { 0x3080 }, 3563c2526597SStephen Boyd [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 }, 3564c2526597SStephen Boyd [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 }, 3565c2526597SStephen Boyd [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 }, 3566c2526597SStephen Boyd [CAMSS_JPEG_BCR] = { 0x35a0 }, 3567c2526597SStephen Boyd [CAMSS_VFE_BCR] = { 0x36a0 }, 3568c2526597SStephen Boyd [CAMSS_VFE0_BCR] = { 0x3660 }, 3569c2526597SStephen Boyd [CAMSS_VFE1_BCR] = { 0x3670 }, 3570c2526597SStephen Boyd [CAMSS_CSI_VFE0_BCR] = { 0x3700 }, 3571c2526597SStephen Boyd [CAMSS_CSI_VFE1_BCR] = { 0x3710 }, 3572c2526597SStephen Boyd [CAMSS_CPP_TOP_BCR] = { 0x36c0 }, 3573c2526597SStephen Boyd [CAMSS_CPP_BCR] = { 0x36d0 }, 3574c2526597SStephen Boyd [CAMSS_CSI0_BCR] = { 0x30b0 }, 3575c2526597SStephen Boyd [CAMSS_CSI0RDI_BCR] = { 0x30d0 }, 3576c2526597SStephen Boyd [CAMSS_CSI0PIX_BCR] = { 0x30e0 }, 3577c2526597SStephen Boyd [CAMSS_CSI1_BCR] = { 0x3120 }, 3578c2526597SStephen Boyd [CAMSS_CSI1RDI_BCR] = { 0x3140 }, 3579c2526597SStephen Boyd [CAMSS_CSI1PIX_BCR] = { 0x3150 }, 3580c2526597SStephen Boyd [CAMSS_CSI2_BCR] = { 0x3180 }, 3581c2526597SStephen Boyd [CAMSS_CSI2RDI_BCR] = { 0x31a0 }, 3582c2526597SStephen Boyd [CAMSS_CSI2PIX_BCR] = { 0x31b0 }, 3583c2526597SStephen Boyd [CAMSS_CSI3_BCR] = { 0x31e0 }, 3584c2526597SStephen Boyd [CAMSS_CSI3RDI_BCR] = { 0x3200 }, 3585c2526597SStephen Boyd [CAMSS_CSI3PIX_BCR] = { 0x3210 }, 3586c2526597SStephen Boyd [CAMSS_ISPIF_BCR] = { 0x3220 }, 3587c2526597SStephen Boyd [FD_BCR] = { 0x3b60 }, 3588c2526597SStephen Boyd [MMSS_SPDM_RM_BCR] = { 0x300 }, 3589c2526597SStephen Boyd }; 3590c2526597SStephen Boyd 3591c2526597SStephen Boyd static const struct regmap_config mmcc_msm8996_regmap_config = { 3592c2526597SStephen Boyd .reg_bits = 32, 3593c2526597SStephen Boyd .reg_stride = 4, 3594c2526597SStephen Boyd .val_bits = 32, 3595c2526597SStephen Boyd .max_register = 0xb008, 3596c2526597SStephen Boyd .fast_io = true, 3597c2526597SStephen Boyd }; 3598c2526597SStephen Boyd 3599c2526597SStephen Boyd static const struct qcom_cc_desc mmcc_msm8996_desc = { 3600c2526597SStephen Boyd .config = &mmcc_msm8996_regmap_config, 3601c2526597SStephen Boyd .clks = mmcc_msm8996_clocks, 3602c2526597SStephen Boyd .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks), 3603c2526597SStephen Boyd .resets = mmcc_msm8996_resets, 3604c2526597SStephen Boyd .num_resets = ARRAY_SIZE(mmcc_msm8996_resets), 36057e824d50SRajendra Nayak .gdscs = mmcc_msm8996_gdscs, 36067e824d50SRajendra Nayak .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs), 3607760be658SJeffrey Hugo .clk_hws = mmcc_msm8996_hws, 3608760be658SJeffrey Hugo .num_clk_hws = ARRAY_SIZE(mmcc_msm8996_hws), 3609c2526597SStephen Boyd }; 3610c2526597SStephen Boyd 3611c2526597SStephen Boyd static const struct of_device_id mmcc_msm8996_match_table[] = { 3612c2526597SStephen Boyd { .compatible = "qcom,mmcc-msm8996" }, 3613c2526597SStephen Boyd { } 3614c2526597SStephen Boyd }; 3615c2526597SStephen Boyd MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table); 3616c2526597SStephen Boyd 3617c2526597SStephen Boyd static int mmcc_msm8996_probe(struct platform_device *pdev) 3618c2526597SStephen Boyd { 3619c2526597SStephen Boyd struct regmap *regmap; 3620c2526597SStephen Boyd 3621c2526597SStephen Boyd regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc); 3622c2526597SStephen Boyd if (IS_ERR(regmap)) 3623c2526597SStephen Boyd return PTR_ERR(regmap); 3624c2526597SStephen Boyd 3625c2526597SStephen Boyd /* Disable the AHB DCD */ 3626c2526597SStephen Boyd regmap_update_bits(regmap, 0x50d8, BIT(31), 0); 3627c2526597SStephen Boyd /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */ 3628c2526597SStephen Boyd regmap_update_bits(regmap, 0x5054, BIT(15), 0); 3629c2526597SStephen Boyd 3630c2526597SStephen Boyd return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap); 3631c2526597SStephen Boyd } 3632c2526597SStephen Boyd 3633c2526597SStephen Boyd static struct platform_driver mmcc_msm8996_driver = { 3634c2526597SStephen Boyd .probe = mmcc_msm8996_probe, 3635c2526597SStephen Boyd .driver = { 3636c2526597SStephen Boyd .name = "mmcc-msm8996", 3637c2526597SStephen Boyd .of_match_table = mmcc_msm8996_match_table, 3638c2526597SStephen Boyd }, 3639c2526597SStephen Boyd }; 3640c2526597SStephen Boyd module_platform_driver(mmcc_msm8996_driver); 3641c2526597SStephen Boyd 3642c2526597SStephen Boyd MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver"); 3643c2526597SStephen Boyd MODULE_LICENSE("GPL v2"); 3644c2526597SStephen Boyd MODULE_ALIAS("platform:mmcc-msm8996"); 3645