1c2526597SStephen Boyd /*x 2c2526597SStephen Boyd * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3c2526597SStephen Boyd * 4c2526597SStephen Boyd * This software is licensed under the terms of the GNU General Public 5c2526597SStephen Boyd * License version 2, as published by the Free Software Foundation, and 6c2526597SStephen Boyd * may be copied, distributed, and modified under those terms. 7c2526597SStephen Boyd * 8c2526597SStephen Boyd * This program is distributed in the hope that it will be useful, 9c2526597SStephen Boyd * but WITHOUT ANY WARRANTY; without even the implied warranty of 10c2526597SStephen Boyd * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11c2526597SStephen Boyd * GNU General Public License for more details. 12c2526597SStephen Boyd */ 13c2526597SStephen Boyd 14c2526597SStephen Boyd #include <linux/kernel.h> 15c2526597SStephen Boyd #include <linux/bitops.h> 16c2526597SStephen Boyd #include <linux/err.h> 17c2526597SStephen Boyd #include <linux/platform_device.h> 18c2526597SStephen Boyd #include <linux/module.h> 19c2526597SStephen Boyd #include <linux/of.h> 20c2526597SStephen Boyd #include <linux/of_device.h> 21c2526597SStephen Boyd #include <linux/clk-provider.h> 22c2526597SStephen Boyd #include <linux/regmap.h> 23c2526597SStephen Boyd #include <linux/reset-controller.h> 24c2526597SStephen Boyd #include <linux/clk.h> 25c2526597SStephen Boyd 26c2526597SStephen Boyd #include <dt-bindings/clock/qcom,mmcc-msm8996.h> 27c2526597SStephen Boyd 28c2526597SStephen Boyd #include "common.h" 29c2526597SStephen Boyd #include "clk-regmap.h" 30c2526597SStephen Boyd #include "clk-regmap-divider.h" 31c2526597SStephen Boyd #include "clk-alpha-pll.h" 32c2526597SStephen Boyd #include "clk-rcg.h" 33c2526597SStephen Boyd #include "clk-branch.h" 34c2526597SStephen Boyd #include "reset.h" 357e824d50SRajendra Nayak #include "gdsc.h" 36c2526597SStephen Boyd 37c2526597SStephen Boyd #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 38c2526597SStephen Boyd 39c2526597SStephen Boyd enum { 40c2526597SStephen Boyd P_XO, 41c2526597SStephen Boyd P_MMPLL0, 42c2526597SStephen Boyd P_GPLL0, 43c2526597SStephen Boyd P_GPLL0_DIV, 44c2526597SStephen Boyd P_MMPLL1, 45c2526597SStephen Boyd P_MMPLL9, 46c2526597SStephen Boyd P_MMPLL2, 47c2526597SStephen Boyd P_MMPLL8, 48c2526597SStephen Boyd P_MMPLL3, 49c2526597SStephen Boyd P_DSI0PLL, 50c2526597SStephen Boyd P_DSI1PLL, 51c2526597SStephen Boyd P_MMPLL5, 52c2526597SStephen Boyd P_HDMIPLL, 53c2526597SStephen Boyd P_DSI0PLL_BYTE, 54c2526597SStephen Boyd P_DSI1PLL_BYTE, 55c2526597SStephen Boyd P_MMPLL4, 56c2526597SStephen Boyd }; 57c2526597SStephen Boyd 58c2526597SStephen Boyd static const struct parent_map mmss_xo_hdmi_map[] = { 59c2526597SStephen Boyd { P_XO, 0 }, 60c2526597SStephen Boyd { P_HDMIPLL, 1 } 61c2526597SStephen Boyd }; 62c2526597SStephen Boyd 63c2526597SStephen Boyd static const char * const mmss_xo_hdmi[] = { 64c2526597SStephen Boyd "xo", 65c2526597SStephen Boyd "hdmipll" 66c2526597SStephen Boyd }; 67c2526597SStephen Boyd 68c2526597SStephen Boyd static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { 69c2526597SStephen Boyd { P_XO, 0 }, 70c2526597SStephen Boyd { P_DSI0PLL, 1 }, 71c2526597SStephen Boyd { P_DSI1PLL, 2 } 72c2526597SStephen Boyd }; 73c2526597SStephen Boyd 74c2526597SStephen Boyd static const char * const mmss_xo_dsi0pll_dsi1pll[] = { 75c2526597SStephen Boyd "xo", 76c2526597SStephen Boyd "dsi0pll", 77c2526597SStephen Boyd "dsi1pll" 78c2526597SStephen Boyd }; 79c2526597SStephen Boyd 80c2526597SStephen Boyd static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { 81c2526597SStephen Boyd { P_XO, 0 }, 82c2526597SStephen Boyd { P_GPLL0, 5 }, 83c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 84c2526597SStephen Boyd }; 85c2526597SStephen Boyd 86c2526597SStephen Boyd static const char * const mmss_xo_gpll0_gpll0_div[] = { 87c2526597SStephen Boyd "xo", 88c2526597SStephen Boyd "gpll0", 89c2526597SStephen Boyd "gpll0_div" 90c2526597SStephen Boyd }; 91c2526597SStephen Boyd 92c2526597SStephen Boyd static const struct parent_map mmss_xo_dsibyte_map[] = { 93c2526597SStephen Boyd { P_XO, 0 }, 94c2526597SStephen Boyd { P_DSI0PLL_BYTE, 1 }, 95c2526597SStephen Boyd { P_DSI1PLL_BYTE, 2 } 96c2526597SStephen Boyd }; 97c2526597SStephen Boyd 98c2526597SStephen Boyd static const char * const mmss_xo_dsibyte[] = { 99c2526597SStephen Boyd "xo", 100c2526597SStephen Boyd "dsi0pllbyte", 101c2526597SStephen Boyd "dsi1pllbyte" 102c2526597SStephen Boyd }; 103c2526597SStephen Boyd 104c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { 105c2526597SStephen Boyd { P_XO, 0 }, 106c2526597SStephen Boyd { P_MMPLL0, 1 }, 107c2526597SStephen Boyd { P_GPLL0, 5 }, 108c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 109c2526597SStephen Boyd }; 110c2526597SStephen Boyd 111c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = { 112c2526597SStephen Boyd "xo", 113c2526597SStephen Boyd "mmpll0", 114c2526597SStephen Boyd "gpll0", 115c2526597SStephen Boyd "gpll0_div" 116c2526597SStephen Boyd }; 117c2526597SStephen Boyd 118c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { 119c2526597SStephen Boyd { P_XO, 0 }, 120c2526597SStephen Boyd { P_MMPLL0, 1 }, 121c2526597SStephen Boyd { P_MMPLL1, 2 }, 122c2526597SStephen Boyd { P_GPLL0, 5 }, 123c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 124c2526597SStephen Boyd }; 125c2526597SStephen Boyd 126c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { 127c2526597SStephen Boyd "xo", 128c2526597SStephen Boyd "mmpll0", 129c2526597SStephen Boyd "mmpll1", 130c2526597SStephen Boyd "gpll0", 131c2526597SStephen Boyd "gpll0_div" 132c2526597SStephen Boyd }; 133c2526597SStephen Boyd 134c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { 135c2526597SStephen Boyd { P_XO, 0 }, 136c2526597SStephen Boyd { P_MMPLL0, 1 }, 137c2526597SStephen Boyd { P_MMPLL3, 3 }, 138c2526597SStephen Boyd { P_GPLL0, 5 }, 139c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 140c2526597SStephen Boyd }; 141c2526597SStephen Boyd 142c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { 143c2526597SStephen Boyd "xo", 144c2526597SStephen Boyd "mmpll0", 145c2526597SStephen Boyd "mmpll3", 146c2526597SStephen Boyd "gpll0", 147c2526597SStephen Boyd "gpll0_div" 148c2526597SStephen Boyd }; 149c2526597SStephen Boyd 150c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { 151c2526597SStephen Boyd { P_XO, 0 }, 152c2526597SStephen Boyd { P_MMPLL0, 1 }, 153c2526597SStephen Boyd { P_MMPLL5, 2 }, 154c2526597SStephen Boyd { P_GPLL0, 5 }, 155c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 156c2526597SStephen Boyd }; 157c2526597SStephen Boyd 158c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { 159c2526597SStephen Boyd "xo", 160c2526597SStephen Boyd "mmpll0", 161c2526597SStephen Boyd "mmpll5", 162c2526597SStephen Boyd "gpll0", 163c2526597SStephen Boyd "gpll0_div" 164c2526597SStephen Boyd }; 165c2526597SStephen Boyd 166c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { 167c2526597SStephen Boyd { P_XO, 0 }, 168c2526597SStephen Boyd { P_MMPLL0, 1 }, 169c2526597SStephen Boyd { P_MMPLL4, 3 }, 170c2526597SStephen Boyd { P_GPLL0, 5 }, 171c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 172c2526597SStephen Boyd }; 173c2526597SStephen Boyd 174c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { 175c2526597SStephen Boyd "xo", 176c2526597SStephen Boyd "mmpll0", 177c2526597SStephen Boyd "mmpll4", 178c2526597SStephen Boyd "gpll0", 179c2526597SStephen Boyd "gpll0_div" 180c2526597SStephen Boyd }; 181c2526597SStephen Boyd 182c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { 183c2526597SStephen Boyd { P_XO, 0 }, 184c2526597SStephen Boyd { P_MMPLL0, 1 }, 185c2526597SStephen Boyd { P_MMPLL9, 2 }, 186c2526597SStephen Boyd { P_MMPLL2, 3 }, 187c2526597SStephen Boyd { P_MMPLL8, 4 }, 188c2526597SStephen Boyd { P_GPLL0, 5 } 189c2526597SStephen Boyd }; 190c2526597SStephen Boyd 191c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { 192c2526597SStephen Boyd "xo", 193c2526597SStephen Boyd "mmpll0", 194c2526597SStephen Boyd "mmpll9", 195c2526597SStephen Boyd "mmpll2", 196c2526597SStephen Boyd "mmpll8", 197c2526597SStephen Boyd "gpll0" 198c2526597SStephen Boyd }; 199c2526597SStephen Boyd 200c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { 201c2526597SStephen Boyd { P_XO, 0 }, 202c2526597SStephen Boyd { P_MMPLL0, 1 }, 203c2526597SStephen Boyd { P_MMPLL9, 2 }, 204c2526597SStephen Boyd { P_MMPLL2, 3 }, 205c2526597SStephen Boyd { P_MMPLL8, 4 }, 206c2526597SStephen Boyd { P_GPLL0, 5 }, 207c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 208c2526597SStephen Boyd }; 209c2526597SStephen Boyd 210c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { 211c2526597SStephen Boyd "xo", 212c2526597SStephen Boyd "mmpll0", 213c2526597SStephen Boyd "mmpll9", 214c2526597SStephen Boyd "mmpll2", 215c2526597SStephen Boyd "mmpll8", 216c2526597SStephen Boyd "gpll0", 217c2526597SStephen Boyd "gpll0_div" 218c2526597SStephen Boyd }; 219c2526597SStephen Boyd 220c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { 221c2526597SStephen Boyd { P_XO, 0 }, 222c2526597SStephen Boyd { P_MMPLL0, 1 }, 223c2526597SStephen Boyd { P_MMPLL1, 2 }, 224c2526597SStephen Boyd { P_MMPLL4, 3 }, 225c2526597SStephen Boyd { P_MMPLL3, 4 }, 226c2526597SStephen Boyd { P_GPLL0, 5 }, 227c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 228c2526597SStephen Boyd }; 229c2526597SStephen Boyd 230c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { 231c2526597SStephen Boyd "xo", 232c2526597SStephen Boyd "mmpll0", 233c2526597SStephen Boyd "mmpll1", 234c2526597SStephen Boyd "mmpll4", 235c2526597SStephen Boyd "mmpll3", 236c2526597SStephen Boyd "gpll0", 237c2526597SStephen Boyd "gpll0_div" 238c2526597SStephen Boyd }; 239c2526597SStephen Boyd 240c2526597SStephen Boyd static struct clk_fixed_factor gpll0_div = { 241c2526597SStephen Boyd .mult = 1, 242c2526597SStephen Boyd .div = 2, 243c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 244c2526597SStephen Boyd .name = "gpll0_div", 245c2526597SStephen Boyd .parent_names = (const char *[]){ "gpll0" }, 246c2526597SStephen Boyd .num_parents = 1, 247c2526597SStephen Boyd .ops = &clk_fixed_factor_ops, 248c2526597SStephen Boyd }, 249c2526597SStephen Boyd }; 250c2526597SStephen Boyd 251c2526597SStephen Boyd static struct pll_vco mmpll_p_vco[] = { 252c2526597SStephen Boyd { 250000000, 500000000, 3 }, 253c2526597SStephen Boyd { 500000000, 1000000000, 2 }, 254c2526597SStephen Boyd { 1000000000, 1500000000, 1 }, 255c2526597SStephen Boyd { 1500000000, 2000000000, 0 }, 256c2526597SStephen Boyd }; 257c2526597SStephen Boyd 258c2526597SStephen Boyd static struct pll_vco mmpll_gfx_vco[] = { 259c2526597SStephen Boyd { 400000000, 1000000000, 2 }, 260c2526597SStephen Boyd { 1000000000, 1500000000, 1 }, 261c2526597SStephen Boyd { 1500000000, 2000000000, 0 }, 262c2526597SStephen Boyd }; 263c2526597SStephen Boyd 264c2526597SStephen Boyd static struct pll_vco mmpll_t_vco[] = { 265c2526597SStephen Boyd { 500000000, 1500000000, 0 }, 266c2526597SStephen Boyd }; 267c2526597SStephen Boyd 268c2526597SStephen Boyd static struct clk_alpha_pll mmpll0_early = { 269c2526597SStephen Boyd .offset = 0x0, 270c2526597SStephen Boyd .vco_table = mmpll_p_vco, 271c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 272c2526597SStephen Boyd .clkr = { 273c2526597SStephen Boyd .enable_reg = 0x100, 274c2526597SStephen Boyd .enable_mask = BIT(0), 275c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 276c2526597SStephen Boyd .name = "mmpll0_early", 277c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 278c2526597SStephen Boyd .num_parents = 1, 279c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 280c2526597SStephen Boyd }, 281c2526597SStephen Boyd }, 282c2526597SStephen Boyd }; 283c2526597SStephen Boyd 284c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll0 = { 285c2526597SStephen Boyd .offset = 0x0, 286c2526597SStephen Boyd .width = 4, 287c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 288c2526597SStephen Boyd .name = "mmpll0", 289c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll0_early" }, 290c2526597SStephen Boyd .num_parents = 1, 291c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 292c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 293c2526597SStephen Boyd }, 294c2526597SStephen Boyd }; 295c2526597SStephen Boyd 296c2526597SStephen Boyd static struct clk_alpha_pll mmpll1_early = { 297c2526597SStephen Boyd .offset = 0x30, 298c2526597SStephen Boyd .vco_table = mmpll_p_vco, 299c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 300c2526597SStephen Boyd .clkr = { 301c2526597SStephen Boyd .enable_reg = 0x100, 302c2526597SStephen Boyd .enable_mask = BIT(1), 303c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 304c2526597SStephen Boyd .name = "mmpll1_early", 305c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 306c2526597SStephen Boyd .num_parents = 1, 307c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 308c2526597SStephen Boyd } 309c2526597SStephen Boyd }, 310c2526597SStephen Boyd }; 311c2526597SStephen Boyd 312c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll1 = { 313c2526597SStephen Boyd .offset = 0x30, 314c2526597SStephen Boyd .width = 4, 315c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 316c2526597SStephen Boyd .name = "mmpll1", 317c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll1_early" }, 318c2526597SStephen Boyd .num_parents = 1, 319c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 320c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 321c2526597SStephen Boyd }, 322c2526597SStephen Boyd }; 323c2526597SStephen Boyd 324c2526597SStephen Boyd static struct clk_alpha_pll mmpll2_early = { 325c2526597SStephen Boyd .offset = 0x4100, 326c2526597SStephen Boyd .vco_table = mmpll_gfx_vco, 327c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 328c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 329c2526597SStephen Boyd .name = "mmpll2_early", 330c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 331c2526597SStephen Boyd .num_parents = 1, 332c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 333c2526597SStephen Boyd }, 334c2526597SStephen Boyd }; 335c2526597SStephen Boyd 336c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll2 = { 337c2526597SStephen Boyd .offset = 0x4100, 338c2526597SStephen Boyd .width = 4, 339c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 340c2526597SStephen Boyd .name = "mmpll2", 341c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll2_early" }, 342c2526597SStephen Boyd .num_parents = 1, 343c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 344c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 345c2526597SStephen Boyd }, 346c2526597SStephen Boyd }; 347c2526597SStephen Boyd 348c2526597SStephen Boyd static struct clk_alpha_pll mmpll3_early = { 349c2526597SStephen Boyd .offset = 0x60, 350c2526597SStephen Boyd .vco_table = mmpll_p_vco, 351c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 352c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 353c2526597SStephen Boyd .name = "mmpll3_early", 354c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 355c2526597SStephen Boyd .num_parents = 1, 356c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 357c2526597SStephen Boyd }, 358c2526597SStephen Boyd }; 359c2526597SStephen Boyd 360c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll3 = { 361c2526597SStephen Boyd .offset = 0x60, 362c2526597SStephen Boyd .width = 4, 363c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 364c2526597SStephen Boyd .name = "mmpll3", 365c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll3_early" }, 366c2526597SStephen Boyd .num_parents = 1, 367c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 368c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 369c2526597SStephen Boyd }, 370c2526597SStephen Boyd }; 371c2526597SStephen Boyd 372c2526597SStephen Boyd static struct clk_alpha_pll mmpll4_early = { 373c2526597SStephen Boyd .offset = 0x90, 374c2526597SStephen Boyd .vco_table = mmpll_t_vco, 375c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_t_vco), 376c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 377c2526597SStephen Boyd .name = "mmpll4_early", 378c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 379c2526597SStephen Boyd .num_parents = 1, 380c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 381c2526597SStephen Boyd }, 382c2526597SStephen Boyd }; 383c2526597SStephen Boyd 384c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll4 = { 385c2526597SStephen Boyd .offset = 0x90, 386c2526597SStephen Boyd .width = 2, 387c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 388c2526597SStephen Boyd .name = "mmpll4", 389c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll4_early" }, 390c2526597SStephen Boyd .num_parents = 1, 391c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 392c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 393c2526597SStephen Boyd }, 394c2526597SStephen Boyd }; 395c2526597SStephen Boyd 396c2526597SStephen Boyd static struct clk_alpha_pll mmpll5_early = { 397c2526597SStephen Boyd .offset = 0xc0, 398c2526597SStephen Boyd .vco_table = mmpll_p_vco, 399c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 400c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 401c2526597SStephen Boyd .name = "mmpll5_early", 402c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 403c2526597SStephen Boyd .num_parents = 1, 404c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 405c2526597SStephen Boyd }, 406c2526597SStephen Boyd }; 407c2526597SStephen Boyd 408c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll5 = { 409c2526597SStephen Boyd .offset = 0xc0, 410c2526597SStephen Boyd .width = 4, 411c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 412c2526597SStephen Boyd .name = "mmpll5", 413c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll5_early" }, 414c2526597SStephen Boyd .num_parents = 1, 415c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 416c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 417c2526597SStephen Boyd }, 418c2526597SStephen Boyd }; 419c2526597SStephen Boyd 420c2526597SStephen Boyd static struct clk_alpha_pll mmpll8_early = { 421c2526597SStephen Boyd .offset = 0x4130, 422c2526597SStephen Boyd .vco_table = mmpll_gfx_vco, 423c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 424c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 425c2526597SStephen Boyd .name = "mmpll8_early", 426c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 427c2526597SStephen Boyd .num_parents = 1, 428c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 429c2526597SStephen Boyd }, 430c2526597SStephen Boyd }; 431c2526597SStephen Boyd 432c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll8 = { 433c2526597SStephen Boyd .offset = 0x4130, 434c2526597SStephen Boyd .width = 4, 435c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 436c2526597SStephen Boyd .name = "mmpll8", 437c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll8_early" }, 438c2526597SStephen Boyd .num_parents = 1, 439c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 440c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 441c2526597SStephen Boyd }, 442c2526597SStephen Boyd }; 443c2526597SStephen Boyd 444c2526597SStephen Boyd static struct clk_alpha_pll mmpll9_early = { 445c2526597SStephen Boyd .offset = 0x4200, 446c2526597SStephen Boyd .vco_table = mmpll_t_vco, 447c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_t_vco), 448c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 449c2526597SStephen Boyd .name = "mmpll9_early", 450c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 451c2526597SStephen Boyd .num_parents = 1, 452c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 453c2526597SStephen Boyd }, 454c2526597SStephen Boyd }; 455c2526597SStephen Boyd 456c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll9 = { 457c2526597SStephen Boyd .offset = 0x4200, 458c2526597SStephen Boyd .width = 2, 459c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 460c2526597SStephen Boyd .name = "mmpll9", 461c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll9_early" }, 462c2526597SStephen Boyd .num_parents = 1, 463c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 464c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 465c2526597SStephen Boyd }, 466c2526597SStephen Boyd }; 467c2526597SStephen Boyd 468c2526597SStephen Boyd static const struct freq_tbl ftbl_ahb_clk_src[] = { 469c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 470c2526597SStephen Boyd F(40000000, P_GPLL0_DIV, 7.5, 0, 0), 471c2526597SStephen Boyd F(80000000, P_MMPLL0, 10, 0, 0), 472c2526597SStephen Boyd { } 473c2526597SStephen Boyd }; 474c2526597SStephen Boyd 475c2526597SStephen Boyd static struct clk_rcg2 ahb_clk_src = { 476c2526597SStephen Boyd .cmd_rcgr = 0x5000, 477c2526597SStephen Boyd .hid_width = 5, 478c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 479c2526597SStephen Boyd .freq_tbl = ftbl_ahb_clk_src, 480c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 481c2526597SStephen Boyd .name = "ahb_clk_src", 482c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 483c2526597SStephen Boyd .num_parents = 4, 484c2526597SStephen Boyd .ops = &clk_rcg2_ops, 485c2526597SStephen Boyd }, 486c2526597SStephen Boyd }; 487c2526597SStephen Boyd 488c2526597SStephen Boyd static const struct freq_tbl ftbl_axi_clk_src[] = { 489c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 490c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 491c2526597SStephen Boyd F(100000000, P_GPLL0, 6, 0, 0), 492c2526597SStephen Boyd F(171430000, P_GPLL0, 3.5, 0, 0), 493c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 494c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 495c2526597SStephen Boyd F(400000000, P_MMPLL0, 2, 0, 0), 496c2526597SStephen Boyd { } 497c2526597SStephen Boyd }; 498c2526597SStephen Boyd 499c2526597SStephen Boyd static struct clk_rcg2 axi_clk_src = { 500c2526597SStephen Boyd .cmd_rcgr = 0x5040, 501c2526597SStephen Boyd .hid_width = 5, 502c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 503c2526597SStephen Boyd .freq_tbl = ftbl_axi_clk_src, 504c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 505c2526597SStephen Boyd .name = "axi_clk_src", 506c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 507c2526597SStephen Boyd .num_parents = 5, 508c2526597SStephen Boyd .ops = &clk_rcg2_ops, 509c2526597SStephen Boyd }, 510c2526597SStephen Boyd }; 511c2526597SStephen Boyd 512c2526597SStephen Boyd static struct clk_rcg2 maxi_clk_src = { 513c2526597SStephen Boyd .cmd_rcgr = 0x5090, 514c2526597SStephen Boyd .hid_width = 5, 515c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 516c2526597SStephen Boyd .freq_tbl = ftbl_axi_clk_src, 517c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 518c2526597SStephen Boyd .name = "maxi_clk_src", 519c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 520c2526597SStephen Boyd .num_parents = 5, 521c2526597SStephen Boyd .ops = &clk_rcg2_ops, 522c2526597SStephen Boyd }, 523c2526597SStephen Boyd }; 524c2526597SStephen Boyd 525c2526597SStephen Boyd static struct clk_rcg2 gfx3d_clk_src = { 526c2526597SStephen Boyd .cmd_rcgr = 0x4000, 527c2526597SStephen Boyd .hid_width = 5, 528c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map, 529c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 530c2526597SStephen Boyd .name = "gfx3d_clk_src", 531c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, 532c2526597SStephen Boyd .num_parents = 6, 533c2526597SStephen Boyd .ops = &clk_gfx3d_ops, 534c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 535c2526597SStephen Boyd }, 536c2526597SStephen Boyd }; 537c2526597SStephen Boyd 538c2526597SStephen Boyd static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { 539c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 540c2526597SStephen Boyd { } 541c2526597SStephen Boyd }; 542c2526597SStephen Boyd 543c2526597SStephen Boyd static struct clk_rcg2 rbbmtimer_clk_src = { 544c2526597SStephen Boyd .cmd_rcgr = 0x4090, 545c2526597SStephen Boyd .hid_width = 5, 546c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 547c2526597SStephen Boyd .freq_tbl = ftbl_rbbmtimer_clk_src, 548c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 549c2526597SStephen Boyd .name = "rbbmtimer_clk_src", 550c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 551c2526597SStephen Boyd .num_parents = 4, 552c2526597SStephen Boyd .ops = &clk_rcg2_ops, 553c2526597SStephen Boyd }, 554c2526597SStephen Boyd }; 555c2526597SStephen Boyd 556c2526597SStephen Boyd static struct clk_rcg2 isense_clk_src = { 557c2526597SStephen Boyd .cmd_rcgr = 0x4010, 558c2526597SStephen Boyd .hid_width = 5, 559c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map, 560c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 561c2526597SStephen Boyd .name = "isense_clk_src", 562c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div, 563c2526597SStephen Boyd .num_parents = 7, 564c2526597SStephen Boyd .ops = &clk_rcg2_ops, 565c2526597SStephen Boyd }, 566c2526597SStephen Boyd }; 567c2526597SStephen Boyd 568c2526597SStephen Boyd static const struct freq_tbl ftbl_rbcpr_clk_src[] = { 569c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 570c2526597SStephen Boyd F(50000000, P_GPLL0, 12, 0, 0), 571c2526597SStephen Boyd { } 572c2526597SStephen Boyd }; 573c2526597SStephen Boyd 574c2526597SStephen Boyd static struct clk_rcg2 rbcpr_clk_src = { 575c2526597SStephen Boyd .cmd_rcgr = 0x4060, 576c2526597SStephen Boyd .hid_width = 5, 577c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 578c2526597SStephen Boyd .freq_tbl = ftbl_rbcpr_clk_src, 579c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 580c2526597SStephen Boyd .name = "rbcpr_clk_src", 581c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 582c2526597SStephen Boyd .num_parents = 4, 583c2526597SStephen Boyd .ops = &clk_rcg2_ops, 584c2526597SStephen Boyd }, 585c2526597SStephen Boyd }; 586c2526597SStephen Boyd 587c2526597SStephen Boyd static const struct freq_tbl ftbl_video_core_clk_src[] = { 588c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 589c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 590c2526597SStephen Boyd F(346666667, P_MMPLL3, 3, 0, 0), 591c2526597SStephen Boyd F(520000000, P_MMPLL3, 2, 0, 0), 592c2526597SStephen Boyd { } 593c2526597SStephen Boyd }; 594c2526597SStephen Boyd 595c2526597SStephen Boyd static struct clk_rcg2 video_core_clk_src = { 596c2526597SStephen Boyd .cmd_rcgr = 0x1000, 597c2526597SStephen Boyd .mnd_width = 8, 598c2526597SStephen Boyd .hid_width = 5, 599c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 600c2526597SStephen Boyd .freq_tbl = ftbl_video_core_clk_src, 601c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 602c2526597SStephen Boyd .name = "video_core_clk_src", 603c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 604c2526597SStephen Boyd .num_parents = 5, 605c2526597SStephen Boyd .ops = &clk_rcg2_ops, 606c2526597SStephen Boyd }, 607c2526597SStephen Boyd }; 608c2526597SStephen Boyd 609c2526597SStephen Boyd static struct clk_rcg2 video_subcore0_clk_src = { 610c2526597SStephen Boyd .cmd_rcgr = 0x1060, 611c2526597SStephen Boyd .mnd_width = 8, 612c2526597SStephen Boyd .hid_width = 5, 613c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 614c2526597SStephen Boyd .freq_tbl = ftbl_video_core_clk_src, 615c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 616c2526597SStephen Boyd .name = "video_subcore0_clk_src", 617c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 618c2526597SStephen Boyd .num_parents = 5, 619c2526597SStephen Boyd .ops = &clk_rcg2_ops, 620c2526597SStephen Boyd }, 621c2526597SStephen Boyd }; 622c2526597SStephen Boyd 623c2526597SStephen Boyd static struct clk_rcg2 video_subcore1_clk_src = { 624c2526597SStephen Boyd .cmd_rcgr = 0x1080, 625c2526597SStephen Boyd .mnd_width = 8, 626c2526597SStephen Boyd .hid_width = 5, 627c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 628c2526597SStephen Boyd .freq_tbl = ftbl_video_core_clk_src, 629c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 630c2526597SStephen Boyd .name = "video_subcore1_clk_src", 631c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 632c2526597SStephen Boyd .num_parents = 5, 633c2526597SStephen Boyd .ops = &clk_rcg2_ops, 634c2526597SStephen Boyd }, 635c2526597SStephen Boyd }; 636c2526597SStephen Boyd 637c2526597SStephen Boyd static struct clk_rcg2 pclk0_clk_src = { 638c2526597SStephen Boyd .cmd_rcgr = 0x2000, 639c2526597SStephen Boyd .mnd_width = 8, 640c2526597SStephen Boyd .hid_width = 5, 641c2526597SStephen Boyd .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 642c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 643c2526597SStephen Boyd .name = "pclk0_clk_src", 644c2526597SStephen Boyd .parent_names = mmss_xo_dsi0pll_dsi1pll, 645c2526597SStephen Boyd .num_parents = 3, 646c2526597SStephen Boyd .ops = &clk_pixel_ops, 647c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 648c2526597SStephen Boyd }, 649c2526597SStephen Boyd }; 650c2526597SStephen Boyd 651c2526597SStephen Boyd static struct clk_rcg2 pclk1_clk_src = { 652c2526597SStephen Boyd .cmd_rcgr = 0x2020, 653c2526597SStephen Boyd .mnd_width = 8, 654c2526597SStephen Boyd .hid_width = 5, 655c2526597SStephen Boyd .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 656c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 657c2526597SStephen Boyd .name = "pclk1_clk_src", 658c2526597SStephen Boyd .parent_names = mmss_xo_dsi0pll_dsi1pll, 659c2526597SStephen Boyd .num_parents = 3, 660c2526597SStephen Boyd .ops = &clk_pixel_ops, 661c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 662c2526597SStephen Boyd }, 663c2526597SStephen Boyd }; 664c2526597SStephen Boyd 665c2526597SStephen Boyd static const struct freq_tbl ftbl_mdp_clk_src[] = { 666c2526597SStephen Boyd F(85714286, P_GPLL0, 7, 0, 0), 667c2526597SStephen Boyd F(100000000, P_GPLL0, 6, 0, 0), 668c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 669c2526597SStephen Boyd F(171428571, P_GPLL0, 3.5, 0, 0), 670c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 671c2526597SStephen Boyd F(275000000, P_MMPLL5, 3, 0, 0), 672c2526597SStephen Boyd F(300000000, P_GPLL0, 2, 0, 0), 673c2526597SStephen Boyd F(330000000, P_MMPLL5, 2.5, 0, 0), 674c2526597SStephen Boyd F(412500000, P_MMPLL5, 2, 0, 0), 675c2526597SStephen Boyd { } 676c2526597SStephen Boyd }; 677c2526597SStephen Boyd 678c2526597SStephen Boyd static struct clk_rcg2 mdp_clk_src = { 679c2526597SStephen Boyd .cmd_rcgr = 0x2040, 680c2526597SStephen Boyd .hid_width = 5, 681c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map, 682c2526597SStephen Boyd .freq_tbl = ftbl_mdp_clk_src, 683c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 684c2526597SStephen Boyd .name = "mdp_clk_src", 685c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, 686c2526597SStephen Boyd .num_parents = 5, 687c2526597SStephen Boyd .ops = &clk_rcg2_ops, 688c2526597SStephen Boyd }, 689c2526597SStephen Boyd }; 690c2526597SStephen Boyd 691c2526597SStephen Boyd static struct freq_tbl extpclk_freq_tbl[] = { 692c2526597SStephen Boyd { .src = P_HDMIPLL }, 693c2526597SStephen Boyd { } 694c2526597SStephen Boyd }; 695c2526597SStephen Boyd 696c2526597SStephen Boyd static struct clk_rcg2 extpclk_clk_src = { 697c2526597SStephen Boyd .cmd_rcgr = 0x2060, 698c2526597SStephen Boyd .hid_width = 5, 699c2526597SStephen Boyd .parent_map = mmss_xo_hdmi_map, 700c2526597SStephen Boyd .freq_tbl = extpclk_freq_tbl, 701c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 702c2526597SStephen Boyd .name = "extpclk_clk_src", 703c2526597SStephen Boyd .parent_names = mmss_xo_hdmi, 704c2526597SStephen Boyd .num_parents = 2, 705c2526597SStephen Boyd .ops = &clk_byte_ops, 706c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 707c2526597SStephen Boyd }, 708c2526597SStephen Boyd }; 709c2526597SStephen Boyd 710c2526597SStephen Boyd static struct freq_tbl ftbl_mdss_vsync_clk[] = { 711c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 712c2526597SStephen Boyd { } 713c2526597SStephen Boyd }; 714c2526597SStephen Boyd 715c2526597SStephen Boyd static struct clk_rcg2 vsync_clk_src = { 716c2526597SStephen Boyd .cmd_rcgr = 0x2080, 717c2526597SStephen Boyd .hid_width = 5, 718c2526597SStephen Boyd .parent_map = mmss_xo_gpll0_gpll0_div_map, 719c2526597SStephen Boyd .freq_tbl = ftbl_mdss_vsync_clk, 720c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 721c2526597SStephen Boyd .name = "vsync_clk_src", 722c2526597SStephen Boyd .parent_names = mmss_xo_gpll0_gpll0_div, 723c2526597SStephen Boyd .num_parents = 3, 724c2526597SStephen Boyd .ops = &clk_rcg2_ops, 725c2526597SStephen Boyd }, 726c2526597SStephen Boyd }; 727c2526597SStephen Boyd 728c2526597SStephen Boyd static struct freq_tbl ftbl_mdss_hdmi_clk[] = { 729c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 730c2526597SStephen Boyd { } 731c2526597SStephen Boyd }; 732c2526597SStephen Boyd 733c2526597SStephen Boyd static struct clk_rcg2 hdmi_clk_src = { 734c2526597SStephen Boyd .cmd_rcgr = 0x2100, 735c2526597SStephen Boyd .hid_width = 5, 736c2526597SStephen Boyd .parent_map = mmss_xo_gpll0_gpll0_div_map, 737c2526597SStephen Boyd .freq_tbl = ftbl_mdss_hdmi_clk, 738c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 739c2526597SStephen Boyd .name = "hdmi_clk_src", 740c2526597SStephen Boyd .parent_names = mmss_xo_gpll0_gpll0_div, 741c2526597SStephen Boyd .num_parents = 3, 742c2526597SStephen Boyd .ops = &clk_rcg2_ops, 743c2526597SStephen Boyd }, 744c2526597SStephen Boyd }; 745c2526597SStephen Boyd 746c2526597SStephen Boyd static struct clk_rcg2 byte0_clk_src = { 747c2526597SStephen Boyd .cmd_rcgr = 0x2120, 748c2526597SStephen Boyd .hid_width = 5, 749c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 750c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 751c2526597SStephen Boyd .name = "byte0_clk_src", 752c2526597SStephen Boyd .parent_names = mmss_xo_dsibyte, 753c2526597SStephen Boyd .num_parents = 3, 754c2526597SStephen Boyd .ops = &clk_byte2_ops, 755c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 756c2526597SStephen Boyd }, 757c2526597SStephen Boyd }; 758c2526597SStephen Boyd 759c2526597SStephen Boyd static struct clk_rcg2 byte1_clk_src = { 760c2526597SStephen Boyd .cmd_rcgr = 0x2140, 761c2526597SStephen Boyd .hid_width = 5, 762c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 763c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 764c2526597SStephen Boyd .name = "byte1_clk_src", 765c2526597SStephen Boyd .parent_names = mmss_xo_dsibyte, 766c2526597SStephen Boyd .num_parents = 3, 767c2526597SStephen Boyd .ops = &clk_byte2_ops, 768c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 769c2526597SStephen Boyd }, 770c2526597SStephen Boyd }; 771c2526597SStephen Boyd 772c2526597SStephen Boyd static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { 773c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 774c2526597SStephen Boyd { } 775c2526597SStephen Boyd }; 776c2526597SStephen Boyd 777c2526597SStephen Boyd static struct clk_rcg2 esc0_clk_src = { 778c2526597SStephen Boyd .cmd_rcgr = 0x2160, 779c2526597SStephen Boyd .hid_width = 5, 780c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 781c2526597SStephen Boyd .freq_tbl = ftbl_mdss_esc0_1_clk, 782c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 783c2526597SStephen Boyd .name = "esc0_clk_src", 784c2526597SStephen Boyd .parent_names = mmss_xo_dsibyte, 785c2526597SStephen Boyd .num_parents = 3, 786c2526597SStephen Boyd .ops = &clk_rcg2_ops, 787c2526597SStephen Boyd }, 788c2526597SStephen Boyd }; 789c2526597SStephen Boyd 790c2526597SStephen Boyd static struct clk_rcg2 esc1_clk_src = { 791c2526597SStephen Boyd .cmd_rcgr = 0x2180, 792c2526597SStephen Boyd .hid_width = 5, 793c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 794c2526597SStephen Boyd .freq_tbl = ftbl_mdss_esc0_1_clk, 795c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 796c2526597SStephen Boyd .name = "esc1_clk_src", 797c2526597SStephen Boyd .parent_names = mmss_xo_dsibyte, 798c2526597SStephen Boyd .num_parents = 3, 799c2526597SStephen Boyd .ops = &clk_rcg2_ops, 800c2526597SStephen Boyd }, 801c2526597SStephen Boyd }; 802c2526597SStephen Boyd 803c2526597SStephen Boyd static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { 804c2526597SStephen Boyd F(10000, P_XO, 16, 1, 120), 805c2526597SStephen Boyd F(24000, P_XO, 16, 1, 50), 806c2526597SStephen Boyd F(6000000, P_GPLL0_DIV, 10, 1, 5), 807c2526597SStephen Boyd F(12000000, P_GPLL0_DIV, 1, 1, 25), 808c2526597SStephen Boyd F(13000000, P_GPLL0_DIV, 2, 13, 150), 809c2526597SStephen Boyd F(24000000, P_GPLL0_DIV, 1, 2, 25), 810c2526597SStephen Boyd { } 811c2526597SStephen Boyd }; 812c2526597SStephen Boyd 813c2526597SStephen Boyd static struct clk_rcg2 camss_gp0_clk_src = { 814c2526597SStephen Boyd .cmd_rcgr = 0x3420, 815c2526597SStephen Boyd .mnd_width = 8, 816c2526597SStephen Boyd .hid_width = 5, 817c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 818c2526597SStephen Boyd .freq_tbl = ftbl_camss_gp0_clk_src, 819c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 820c2526597SStephen Boyd .name = "camss_gp0_clk_src", 821c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 822c2526597SStephen Boyd .num_parents = 5, 823c2526597SStephen Boyd .ops = &clk_rcg2_ops, 824c2526597SStephen Boyd }, 825c2526597SStephen Boyd }; 826c2526597SStephen Boyd 827c2526597SStephen Boyd static struct clk_rcg2 camss_gp1_clk_src = { 828c2526597SStephen Boyd .cmd_rcgr = 0x3450, 829c2526597SStephen Boyd .mnd_width = 8, 830c2526597SStephen Boyd .hid_width = 5, 831c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 832c2526597SStephen Boyd .freq_tbl = ftbl_camss_gp0_clk_src, 833c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 834c2526597SStephen Boyd .name = "camss_gp1_clk_src", 835c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 836c2526597SStephen Boyd .num_parents = 5, 837c2526597SStephen Boyd .ops = &clk_rcg2_ops, 838c2526597SStephen Boyd }, 839c2526597SStephen Boyd }; 840c2526597SStephen Boyd 841c2526597SStephen Boyd static const struct freq_tbl ftbl_mclk0_clk_src[] = { 842c2526597SStephen Boyd F(4800000, P_XO, 4, 0, 0), 843c2526597SStephen Boyd F(6000000, P_GPLL0_DIV, 10, 1, 5), 844c2526597SStephen Boyd F(8000000, P_GPLL0_DIV, 1, 2, 75), 845c2526597SStephen Boyd F(9600000, P_XO, 2, 0, 0), 846c2526597SStephen Boyd F(16666667, P_GPLL0_DIV, 2, 1, 9), 847c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 848c2526597SStephen Boyd F(24000000, P_GPLL0_DIV, 1, 2, 25), 849c2526597SStephen Boyd F(33333333, P_GPLL0_DIV, 1, 1, 9), 850c2526597SStephen Boyd F(48000000, P_GPLL0, 1, 2, 25), 851c2526597SStephen Boyd F(66666667, P_GPLL0, 1, 1, 9), 852c2526597SStephen Boyd { } 853c2526597SStephen Boyd }; 854c2526597SStephen Boyd 855c2526597SStephen Boyd static struct clk_rcg2 mclk0_clk_src = { 856c2526597SStephen Boyd .cmd_rcgr = 0x3360, 857c2526597SStephen Boyd .mnd_width = 8, 858c2526597SStephen Boyd .hid_width = 5, 859c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 860c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 861c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 862c2526597SStephen Boyd .name = "mclk0_clk_src", 863c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 864c2526597SStephen Boyd .num_parents = 5, 865c2526597SStephen Boyd .ops = &clk_rcg2_ops, 866c2526597SStephen Boyd }, 867c2526597SStephen Boyd }; 868c2526597SStephen Boyd 869c2526597SStephen Boyd static struct clk_rcg2 mclk1_clk_src = { 870c2526597SStephen Boyd .cmd_rcgr = 0x3390, 871c2526597SStephen Boyd .mnd_width = 8, 872c2526597SStephen Boyd .hid_width = 5, 873c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 874c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 875c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 876c2526597SStephen Boyd .name = "mclk1_clk_src", 877c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 878c2526597SStephen Boyd .num_parents = 5, 879c2526597SStephen Boyd .ops = &clk_rcg2_ops, 880c2526597SStephen Boyd }, 881c2526597SStephen Boyd }; 882c2526597SStephen Boyd 883c2526597SStephen Boyd static struct clk_rcg2 mclk2_clk_src = { 884c2526597SStephen Boyd .cmd_rcgr = 0x33c0, 885c2526597SStephen Boyd .mnd_width = 8, 886c2526597SStephen Boyd .hid_width = 5, 887c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 888c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 889c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 890c2526597SStephen Boyd .name = "mclk2_clk_src", 891c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 892c2526597SStephen Boyd .num_parents = 5, 893c2526597SStephen Boyd .ops = &clk_rcg2_ops, 894c2526597SStephen Boyd }, 895c2526597SStephen Boyd }; 896c2526597SStephen Boyd 897c2526597SStephen Boyd static struct clk_rcg2 mclk3_clk_src = { 898c2526597SStephen Boyd .cmd_rcgr = 0x33f0, 899c2526597SStephen Boyd .mnd_width = 8, 900c2526597SStephen Boyd .hid_width = 5, 901c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 902c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 903c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 904c2526597SStephen Boyd .name = "mclk3_clk_src", 905c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 906c2526597SStephen Boyd .num_parents = 5, 907c2526597SStephen Boyd .ops = &clk_rcg2_ops, 908c2526597SStephen Boyd }, 909c2526597SStephen Boyd }; 910c2526597SStephen Boyd 911c2526597SStephen Boyd static const struct freq_tbl ftbl_cci_clk_src[] = { 912c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 913c2526597SStephen Boyd F(37500000, P_GPLL0, 16, 0, 0), 914c2526597SStephen Boyd F(50000000, P_GPLL0, 12, 0, 0), 915c2526597SStephen Boyd F(100000000, P_GPLL0, 6, 0, 0), 916c2526597SStephen Boyd { } 917c2526597SStephen Boyd }; 918c2526597SStephen Boyd 919c2526597SStephen Boyd static struct clk_rcg2 cci_clk_src = { 920c2526597SStephen Boyd .cmd_rcgr = 0x3300, 921c2526597SStephen Boyd .mnd_width = 8, 922c2526597SStephen Boyd .hid_width = 5, 923c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 924c2526597SStephen Boyd .freq_tbl = ftbl_cci_clk_src, 925c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 926c2526597SStephen Boyd .name = "cci_clk_src", 927c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 928c2526597SStephen Boyd .num_parents = 5, 929c2526597SStephen Boyd .ops = &clk_rcg2_ops, 930c2526597SStephen Boyd }, 931c2526597SStephen Boyd }; 932c2526597SStephen Boyd 933c2526597SStephen Boyd static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { 934c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 935c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 936c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 937c2526597SStephen Boyd { } 938c2526597SStephen Boyd }; 939c2526597SStephen Boyd 940c2526597SStephen Boyd static struct clk_rcg2 csi0phytimer_clk_src = { 941c2526597SStephen Boyd .cmd_rcgr = 0x3000, 942c2526597SStephen Boyd .hid_width = 5, 943c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 944c2526597SStephen Boyd .freq_tbl = ftbl_csi0phytimer_clk_src, 945c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 946c2526597SStephen Boyd .name = "csi0phytimer_clk_src", 947c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 948c2526597SStephen Boyd .num_parents = 7, 949c2526597SStephen Boyd .ops = &clk_rcg2_ops, 950c2526597SStephen Boyd }, 951c2526597SStephen Boyd }; 952c2526597SStephen Boyd 953c2526597SStephen Boyd static struct clk_rcg2 csi1phytimer_clk_src = { 954c2526597SStephen Boyd .cmd_rcgr = 0x3030, 955c2526597SStephen Boyd .hid_width = 5, 956c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 957c2526597SStephen Boyd .freq_tbl = ftbl_csi0phytimer_clk_src, 958c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 959c2526597SStephen Boyd .name = "csi1phytimer_clk_src", 960c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 961c2526597SStephen Boyd .num_parents = 7, 962c2526597SStephen Boyd .ops = &clk_rcg2_ops, 963c2526597SStephen Boyd }, 964c2526597SStephen Boyd }; 965c2526597SStephen Boyd 966c2526597SStephen Boyd static struct clk_rcg2 csi2phytimer_clk_src = { 967c2526597SStephen Boyd .cmd_rcgr = 0x3060, 968c2526597SStephen Boyd .hid_width = 5, 969c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 970c2526597SStephen Boyd .freq_tbl = ftbl_csi0phytimer_clk_src, 971c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 972c2526597SStephen Boyd .name = "csi2phytimer_clk_src", 973c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 974c2526597SStephen Boyd .num_parents = 7, 975c2526597SStephen Boyd .ops = &clk_rcg2_ops, 976c2526597SStephen Boyd }, 977c2526597SStephen Boyd }; 978c2526597SStephen Boyd 979c2526597SStephen Boyd static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = { 980c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 981c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 982c2526597SStephen Boyd F(320000000, P_MMPLL4, 3, 0, 0), 983c2526597SStephen Boyd F(384000000, P_MMPLL4, 2.5, 0, 0), 984c2526597SStephen Boyd { } 985c2526597SStephen Boyd }; 986c2526597SStephen Boyd 987c2526597SStephen Boyd static struct clk_rcg2 csiphy0_3p_clk_src = { 988c2526597SStephen Boyd .cmd_rcgr = 0x3240, 989c2526597SStephen Boyd .hid_width = 5, 990c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 991c2526597SStephen Boyd .freq_tbl = ftbl_csiphy0_3p_clk_src, 992c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 993c2526597SStephen Boyd .name = "csiphy0_3p_clk_src", 994c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 995c2526597SStephen Boyd .num_parents = 7, 996c2526597SStephen Boyd .ops = &clk_rcg2_ops, 997c2526597SStephen Boyd }, 998c2526597SStephen Boyd }; 999c2526597SStephen Boyd 1000c2526597SStephen Boyd static struct clk_rcg2 csiphy1_3p_clk_src = { 1001c2526597SStephen Boyd .cmd_rcgr = 0x3260, 1002c2526597SStephen Boyd .hid_width = 5, 1003c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1004c2526597SStephen Boyd .freq_tbl = ftbl_csiphy0_3p_clk_src, 1005c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1006c2526597SStephen Boyd .name = "csiphy1_3p_clk_src", 1007c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1008c2526597SStephen Boyd .num_parents = 7, 1009c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1010c2526597SStephen Boyd }, 1011c2526597SStephen Boyd }; 1012c2526597SStephen Boyd 1013c2526597SStephen Boyd static struct clk_rcg2 csiphy2_3p_clk_src = { 1014c2526597SStephen Boyd .cmd_rcgr = 0x3280, 1015c2526597SStephen Boyd .hid_width = 5, 1016c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1017c2526597SStephen Boyd .freq_tbl = ftbl_csiphy0_3p_clk_src, 1018c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1019c2526597SStephen Boyd .name = "csiphy2_3p_clk_src", 1020c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1021c2526597SStephen Boyd .num_parents = 7, 1022c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1023c2526597SStephen Boyd }, 1024c2526597SStephen Boyd }; 1025c2526597SStephen Boyd 1026c2526597SStephen Boyd static const struct freq_tbl ftbl_jpeg0_clk_src[] = { 1027c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 1028c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 1029c2526597SStephen Boyd F(228571429, P_MMPLL0, 3.5, 0, 0), 1030c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 1031c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1032c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1033c2526597SStephen Boyd { } 1034c2526597SStephen Boyd }; 1035c2526597SStephen Boyd 1036c2526597SStephen Boyd static struct clk_rcg2 jpeg0_clk_src = { 1037c2526597SStephen Boyd .cmd_rcgr = 0x3500, 1038c2526597SStephen Boyd .hid_width = 5, 1039c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1040c2526597SStephen Boyd .freq_tbl = ftbl_jpeg0_clk_src, 1041c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1042c2526597SStephen Boyd .name = "jpeg0_clk_src", 1043c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1044c2526597SStephen Boyd .num_parents = 7, 1045c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1046c2526597SStephen Boyd }, 1047c2526597SStephen Boyd }; 1048c2526597SStephen Boyd 1049c2526597SStephen Boyd static const struct freq_tbl ftbl_jpeg2_clk_src[] = { 1050c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 1051c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 1052c2526597SStephen Boyd F(228571429, P_MMPLL0, 3.5, 0, 0), 1053c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 1054c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1055c2526597SStephen Boyd { } 1056c2526597SStephen Boyd }; 1057c2526597SStephen Boyd 1058c2526597SStephen Boyd static struct clk_rcg2 jpeg2_clk_src = { 1059c2526597SStephen Boyd .cmd_rcgr = 0x3540, 1060c2526597SStephen Boyd .hid_width = 5, 1061c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1062c2526597SStephen Boyd .freq_tbl = ftbl_jpeg2_clk_src, 1063c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1064c2526597SStephen Boyd .name = "jpeg2_clk_src", 1065c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1066c2526597SStephen Boyd .num_parents = 7, 1067c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1068c2526597SStephen Boyd }, 1069c2526597SStephen Boyd }; 1070c2526597SStephen Boyd 1071c2526597SStephen Boyd static struct clk_rcg2 jpeg_dma_clk_src = { 1072c2526597SStephen Boyd .cmd_rcgr = 0x3560, 1073c2526597SStephen Boyd .hid_width = 5, 1074c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1075c2526597SStephen Boyd .freq_tbl = ftbl_jpeg0_clk_src, 1076c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1077c2526597SStephen Boyd .name = "jpeg_dma_clk_src", 1078c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1079c2526597SStephen Boyd .num_parents = 7, 1080c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1081c2526597SStephen Boyd }, 1082c2526597SStephen Boyd }; 1083c2526597SStephen Boyd 1084c2526597SStephen Boyd static const struct freq_tbl ftbl_vfe0_clk_src[] = { 1085c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 1086c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1087c2526597SStephen Boyd F(300000000, P_GPLL0, 2, 0, 0), 1088c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1089c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1090c2526597SStephen Boyd F(600000000, P_GPLL0, 1, 0, 0), 1091c2526597SStephen Boyd { } 1092c2526597SStephen Boyd }; 1093c2526597SStephen Boyd 1094c2526597SStephen Boyd static struct clk_rcg2 vfe0_clk_src = { 1095c2526597SStephen Boyd .cmd_rcgr = 0x3600, 1096c2526597SStephen Boyd .hid_width = 5, 1097c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1098c2526597SStephen Boyd .freq_tbl = ftbl_vfe0_clk_src, 1099c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1100c2526597SStephen Boyd .name = "vfe0_clk_src", 1101c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1102c2526597SStephen Boyd .num_parents = 7, 1103c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1104c2526597SStephen Boyd }, 1105c2526597SStephen Boyd }; 1106c2526597SStephen Boyd 1107c2526597SStephen Boyd static struct clk_rcg2 vfe1_clk_src = { 1108c2526597SStephen Boyd .cmd_rcgr = 0x3620, 1109c2526597SStephen Boyd .hid_width = 5, 1110c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1111c2526597SStephen Boyd .freq_tbl = ftbl_vfe0_clk_src, 1112c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1113c2526597SStephen Boyd .name = "vfe1_clk_src", 1114c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1115c2526597SStephen Boyd .num_parents = 7, 1116c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1117c2526597SStephen Boyd }, 1118c2526597SStephen Boyd }; 1119c2526597SStephen Boyd 1120c2526597SStephen Boyd static const struct freq_tbl ftbl_cpp_clk_src[] = { 1121c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1122c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1123c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1124c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1125c2526597SStephen Boyd F(640000000, P_MMPLL4, 1.5, 0, 0), 1126c2526597SStephen Boyd { } 1127c2526597SStephen Boyd }; 1128c2526597SStephen Boyd 1129c2526597SStephen Boyd static struct clk_rcg2 cpp_clk_src = { 1130c2526597SStephen Boyd .cmd_rcgr = 0x3640, 1131c2526597SStephen Boyd .hid_width = 5, 1132c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1133c2526597SStephen Boyd .freq_tbl = ftbl_cpp_clk_src, 1134c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1135c2526597SStephen Boyd .name = "cpp_clk_src", 1136c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1137c2526597SStephen Boyd .num_parents = 7, 1138c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1139c2526597SStephen Boyd }, 1140c2526597SStephen Boyd }; 1141c2526597SStephen Boyd 1142c2526597SStephen Boyd static const struct freq_tbl ftbl_csi0_clk_src[] = { 1143c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1144c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1145c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 1146c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1147c2526597SStephen Boyd F(600000000, P_GPLL0, 1, 0, 0), 1148c2526597SStephen Boyd { } 1149c2526597SStephen Boyd }; 1150c2526597SStephen Boyd 1151c2526597SStephen Boyd static struct clk_rcg2 csi0_clk_src = { 1152c2526597SStephen Boyd .cmd_rcgr = 0x3090, 1153c2526597SStephen Boyd .hid_width = 5, 1154c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1155c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1156c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1157c2526597SStephen Boyd .name = "csi0_clk_src", 1158c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1159c2526597SStephen Boyd .num_parents = 7, 1160c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1161c2526597SStephen Boyd }, 1162c2526597SStephen Boyd }; 1163c2526597SStephen Boyd 1164c2526597SStephen Boyd static struct clk_rcg2 csi1_clk_src = { 1165c2526597SStephen Boyd .cmd_rcgr = 0x3100, 1166c2526597SStephen Boyd .hid_width = 5, 1167c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1168c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1169c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1170c2526597SStephen Boyd .name = "csi1_clk_src", 1171c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1172c2526597SStephen Boyd .num_parents = 7, 1173c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1174c2526597SStephen Boyd }, 1175c2526597SStephen Boyd }; 1176c2526597SStephen Boyd 1177c2526597SStephen Boyd static struct clk_rcg2 csi2_clk_src = { 1178c2526597SStephen Boyd .cmd_rcgr = 0x3160, 1179c2526597SStephen Boyd .hid_width = 5, 1180c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1181c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1182c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1183c2526597SStephen Boyd .name = "csi2_clk_src", 1184c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1185c2526597SStephen Boyd .num_parents = 7, 1186c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1187c2526597SStephen Boyd }, 1188c2526597SStephen Boyd }; 1189c2526597SStephen Boyd 1190c2526597SStephen Boyd static struct clk_rcg2 csi3_clk_src = { 1191c2526597SStephen Boyd .cmd_rcgr = 0x31c0, 1192c2526597SStephen Boyd .hid_width = 5, 1193c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1194c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1195c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1196c2526597SStephen Boyd .name = "csi3_clk_src", 1197c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1198c2526597SStephen Boyd .num_parents = 7, 1199c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1200c2526597SStephen Boyd }, 1201c2526597SStephen Boyd }; 1202c2526597SStephen Boyd 1203c2526597SStephen Boyd static const struct freq_tbl ftbl_fd_core_clk_src[] = { 1204c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1205c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1206c2526597SStephen Boyd F(400000000, P_MMPLL0, 2, 0, 0), 1207c2526597SStephen Boyd { } 1208c2526597SStephen Boyd }; 1209c2526597SStephen Boyd 1210c2526597SStephen Boyd static struct clk_rcg2 fd_core_clk_src = { 1211c2526597SStephen Boyd .cmd_rcgr = 0x3b00, 1212c2526597SStephen Boyd .hid_width = 5, 1213c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 1214c2526597SStephen Boyd .freq_tbl = ftbl_fd_core_clk_src, 1215c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1216c2526597SStephen Boyd .name = "fd_core_clk_src", 1217c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 1218c2526597SStephen Boyd .num_parents = 5, 1219c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1220c2526597SStephen Boyd }, 1221c2526597SStephen Boyd }; 1222c2526597SStephen Boyd 1223c2526597SStephen Boyd static struct clk_branch mmss_mmagic_ahb_clk = { 1224c2526597SStephen Boyd .halt_reg = 0x5024, 1225c2526597SStephen Boyd .clkr = { 1226c2526597SStephen Boyd .enable_reg = 0x5024, 1227c2526597SStephen Boyd .enable_mask = BIT(0), 1228c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1229c2526597SStephen Boyd .name = "mmss_mmagic_ahb_clk", 1230c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1231c2526597SStephen Boyd .num_parents = 1, 1232c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1233c2526597SStephen Boyd .ops = &clk_branch2_ops, 1234c2526597SStephen Boyd }, 1235c2526597SStephen Boyd }, 1236c2526597SStephen Boyd }; 1237c2526597SStephen Boyd 1238c2526597SStephen Boyd static struct clk_branch mmss_mmagic_cfg_ahb_clk = { 1239c2526597SStephen Boyd .halt_reg = 0x5054, 1240c2526597SStephen Boyd .clkr = { 1241c2526597SStephen Boyd .enable_reg = 0x5054, 1242c2526597SStephen Boyd .enable_mask = BIT(0), 1243c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1244c2526597SStephen Boyd .name = "mmss_mmagic_cfg_ahb_clk", 1245c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1246c2526597SStephen Boyd .num_parents = 1, 1247c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1248c2526597SStephen Boyd .ops = &clk_branch2_ops, 1249c2526597SStephen Boyd }, 1250c2526597SStephen Boyd }, 1251c2526597SStephen Boyd }; 1252c2526597SStephen Boyd 1253c2526597SStephen Boyd static struct clk_branch mmss_misc_ahb_clk = { 1254c2526597SStephen Boyd .halt_reg = 0x5018, 1255c2526597SStephen Boyd .clkr = { 1256c2526597SStephen Boyd .enable_reg = 0x5018, 1257c2526597SStephen Boyd .enable_mask = BIT(0), 1258c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1259c2526597SStephen Boyd .name = "mmss_misc_ahb_clk", 1260c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1261c2526597SStephen Boyd .num_parents = 1, 1262c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1263c2526597SStephen Boyd .ops = &clk_branch2_ops, 1264c2526597SStephen Boyd }, 1265c2526597SStephen Boyd }, 1266c2526597SStephen Boyd }; 1267c2526597SStephen Boyd 1268c2526597SStephen Boyd static struct clk_branch mmss_misc_cxo_clk = { 1269c2526597SStephen Boyd .halt_reg = 0x5014, 1270c2526597SStephen Boyd .clkr = { 1271c2526597SStephen Boyd .enable_reg = 0x5014, 1272c2526597SStephen Boyd .enable_mask = BIT(0), 1273c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1274c2526597SStephen Boyd .name = "mmss_misc_cxo_clk", 1275c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 1276c2526597SStephen Boyd .num_parents = 1, 1277c2526597SStephen Boyd .ops = &clk_branch2_ops, 1278c2526597SStephen Boyd }, 1279c2526597SStephen Boyd }, 1280c2526597SStephen Boyd }; 1281c2526597SStephen Boyd 1282c2526597SStephen Boyd static struct clk_branch mmss_mmagic_maxi_clk = { 1283c2526597SStephen Boyd .halt_reg = 0x5074, 1284c2526597SStephen Boyd .clkr = { 1285c2526597SStephen Boyd .enable_reg = 0x5074, 1286c2526597SStephen Boyd .enable_mask = BIT(0), 1287c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1288c2526597SStephen Boyd .name = "mmss_mmagic_maxi_clk", 1289c2526597SStephen Boyd .parent_names = (const char *[]){ "maxi_clk_src" }, 1290c2526597SStephen Boyd .num_parents = 1, 1291c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1292c2526597SStephen Boyd .ops = &clk_branch2_ops, 1293c2526597SStephen Boyd }, 1294c2526597SStephen Boyd }, 1295c2526597SStephen Boyd }; 1296c2526597SStephen Boyd 1297c2526597SStephen Boyd static struct clk_branch mmagic_camss_axi_clk = { 1298c2526597SStephen Boyd .halt_reg = 0x3c44, 1299c2526597SStephen Boyd .clkr = { 1300c2526597SStephen Boyd .enable_reg = 0x3c44, 1301c2526597SStephen Boyd .enable_mask = BIT(0), 1302c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1303c2526597SStephen Boyd .name = "mmagic_camss_axi_clk", 1304c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1305c2526597SStephen Boyd .num_parents = 1, 1306c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1307c2526597SStephen Boyd .ops = &clk_branch2_ops, 1308c2526597SStephen Boyd }, 1309c2526597SStephen Boyd }, 1310c2526597SStephen Boyd }; 1311c2526597SStephen Boyd 1312c2526597SStephen Boyd static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = { 1313c2526597SStephen Boyd .halt_reg = 0x3c48, 1314c2526597SStephen Boyd .clkr = { 1315c2526597SStephen Boyd .enable_reg = 0x3c48, 1316c2526597SStephen Boyd .enable_mask = BIT(0), 1317c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1318c2526597SStephen Boyd .name = "mmagic_camss_noc_cfg_ahb_clk", 1319c2526597SStephen Boyd .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1320c2526597SStephen Boyd .num_parents = 1, 1321c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1322c2526597SStephen Boyd .ops = &clk_branch2_ops, 1323c2526597SStephen Boyd }, 1324c2526597SStephen Boyd }, 1325c2526597SStephen Boyd }; 1326c2526597SStephen Boyd 1327c2526597SStephen Boyd static struct clk_branch smmu_vfe_ahb_clk = { 1328c2526597SStephen Boyd .halt_reg = 0x3c04, 1329c2526597SStephen Boyd .clkr = { 1330c2526597SStephen Boyd .enable_reg = 0x3c04, 1331c2526597SStephen Boyd .enable_mask = BIT(0), 1332c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1333c2526597SStephen Boyd .name = "smmu_vfe_ahb_clk", 1334c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1335c2526597SStephen Boyd .num_parents = 1, 1336c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1337c2526597SStephen Boyd .ops = &clk_branch2_ops, 1338c2526597SStephen Boyd }, 1339c2526597SStephen Boyd }, 1340c2526597SStephen Boyd }; 1341c2526597SStephen Boyd 1342c2526597SStephen Boyd static struct clk_branch smmu_vfe_axi_clk = { 1343c2526597SStephen Boyd .halt_reg = 0x3c08, 1344c2526597SStephen Boyd .clkr = { 1345c2526597SStephen Boyd .enable_reg = 0x3c08, 1346c2526597SStephen Boyd .enable_mask = BIT(0), 1347c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1348c2526597SStephen Boyd .name = "smmu_vfe_axi_clk", 1349c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1350c2526597SStephen Boyd .num_parents = 1, 1351c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1352c2526597SStephen Boyd .ops = &clk_branch2_ops, 1353c2526597SStephen Boyd }, 1354c2526597SStephen Boyd }, 1355c2526597SStephen Boyd }; 1356c2526597SStephen Boyd 1357c2526597SStephen Boyd static struct clk_branch smmu_cpp_ahb_clk = { 1358c2526597SStephen Boyd .halt_reg = 0x3c14, 1359c2526597SStephen Boyd .clkr = { 1360c2526597SStephen Boyd .enable_reg = 0x3c14, 1361c2526597SStephen Boyd .enable_mask = BIT(0), 1362c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1363c2526597SStephen Boyd .name = "smmu_cpp_ahb_clk", 1364c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1365c2526597SStephen Boyd .num_parents = 1, 1366c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1367c2526597SStephen Boyd .ops = &clk_branch2_ops, 1368c2526597SStephen Boyd }, 1369c2526597SStephen Boyd }, 1370c2526597SStephen Boyd }; 1371c2526597SStephen Boyd 1372c2526597SStephen Boyd static struct clk_branch smmu_cpp_axi_clk = { 1373c2526597SStephen Boyd .halt_reg = 0x3c18, 1374c2526597SStephen Boyd .clkr = { 1375c2526597SStephen Boyd .enable_reg = 0x3c18, 1376c2526597SStephen Boyd .enable_mask = BIT(0), 1377c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1378c2526597SStephen Boyd .name = "smmu_cpp_axi_clk", 1379c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1380c2526597SStephen Boyd .num_parents = 1, 1381c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1382c2526597SStephen Boyd .ops = &clk_branch2_ops, 1383c2526597SStephen Boyd }, 1384c2526597SStephen Boyd }, 1385c2526597SStephen Boyd }; 1386c2526597SStephen Boyd 1387c2526597SStephen Boyd static struct clk_branch smmu_jpeg_ahb_clk = { 1388c2526597SStephen Boyd .halt_reg = 0x3c24, 1389c2526597SStephen Boyd .clkr = { 1390c2526597SStephen Boyd .enable_reg = 0x3c24, 1391c2526597SStephen Boyd .enable_mask = BIT(0), 1392c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1393c2526597SStephen Boyd .name = "smmu_jpeg_ahb_clk", 1394c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1395c2526597SStephen Boyd .num_parents = 1, 1396c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1397c2526597SStephen Boyd .ops = &clk_branch2_ops, 1398c2526597SStephen Boyd }, 1399c2526597SStephen Boyd }, 1400c2526597SStephen Boyd }; 1401c2526597SStephen Boyd 1402c2526597SStephen Boyd static struct clk_branch smmu_jpeg_axi_clk = { 1403c2526597SStephen Boyd .halt_reg = 0x3c28, 1404c2526597SStephen Boyd .clkr = { 1405c2526597SStephen Boyd .enable_reg = 0x3c28, 1406c2526597SStephen Boyd .enable_mask = BIT(0), 1407c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1408c2526597SStephen Boyd .name = "smmu_jpeg_axi_clk", 1409c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1410c2526597SStephen Boyd .num_parents = 1, 1411c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1412c2526597SStephen Boyd .ops = &clk_branch2_ops, 1413c2526597SStephen Boyd }, 1414c2526597SStephen Boyd }, 1415c2526597SStephen Boyd }; 1416c2526597SStephen Boyd 1417c2526597SStephen Boyd static struct clk_branch mmagic_mdss_axi_clk = { 1418c2526597SStephen Boyd .halt_reg = 0x2474, 1419c2526597SStephen Boyd .clkr = { 1420c2526597SStephen Boyd .enable_reg = 0x2474, 1421c2526597SStephen Boyd .enable_mask = BIT(0), 1422c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1423c2526597SStephen Boyd .name = "mmagic_mdss_axi_clk", 1424c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1425c2526597SStephen Boyd .num_parents = 1, 1426c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1427c2526597SStephen Boyd .ops = &clk_branch2_ops, 1428c2526597SStephen Boyd }, 1429c2526597SStephen Boyd }, 1430c2526597SStephen Boyd }; 1431c2526597SStephen Boyd 1432c2526597SStephen Boyd static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = { 1433c2526597SStephen Boyd .halt_reg = 0x2478, 1434c2526597SStephen Boyd .clkr = { 1435c2526597SStephen Boyd .enable_reg = 0x2478, 1436c2526597SStephen Boyd .enable_mask = BIT(0), 1437c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1438c2526597SStephen Boyd .name = "mmagic_mdss_noc_cfg_ahb_clk", 1439c2526597SStephen Boyd .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1440c2526597SStephen Boyd .num_parents = 1, 1441c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1442c2526597SStephen Boyd .ops = &clk_branch2_ops, 1443c2526597SStephen Boyd }, 1444c2526597SStephen Boyd }, 1445c2526597SStephen Boyd }; 1446c2526597SStephen Boyd 1447c2526597SStephen Boyd static struct clk_branch smmu_rot_ahb_clk = { 1448c2526597SStephen Boyd .halt_reg = 0x2444, 1449c2526597SStephen Boyd .clkr = { 1450c2526597SStephen Boyd .enable_reg = 0x2444, 1451c2526597SStephen Boyd .enable_mask = BIT(0), 1452c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1453c2526597SStephen Boyd .name = "smmu_rot_ahb_clk", 1454c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1455c2526597SStephen Boyd .num_parents = 1, 1456c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1457c2526597SStephen Boyd .ops = &clk_branch2_ops, 1458c2526597SStephen Boyd }, 1459c2526597SStephen Boyd }, 1460c2526597SStephen Boyd }; 1461c2526597SStephen Boyd 1462c2526597SStephen Boyd static struct clk_branch smmu_rot_axi_clk = { 1463c2526597SStephen Boyd .halt_reg = 0x2448, 1464c2526597SStephen Boyd .clkr = { 1465c2526597SStephen Boyd .enable_reg = 0x2448, 1466c2526597SStephen Boyd .enable_mask = BIT(0), 1467c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1468c2526597SStephen Boyd .name = "smmu_rot_axi_clk", 1469c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1470c2526597SStephen Boyd .num_parents = 1, 1471c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1472c2526597SStephen Boyd .ops = &clk_branch2_ops, 1473c2526597SStephen Boyd }, 1474c2526597SStephen Boyd }, 1475c2526597SStephen Boyd }; 1476c2526597SStephen Boyd 1477c2526597SStephen Boyd static struct clk_branch smmu_mdp_ahb_clk = { 1478c2526597SStephen Boyd .halt_reg = 0x2454, 1479c2526597SStephen Boyd .clkr = { 1480c2526597SStephen Boyd .enable_reg = 0x2454, 1481c2526597SStephen Boyd .enable_mask = BIT(0), 1482c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1483c2526597SStephen Boyd .name = "smmu_mdp_ahb_clk", 1484c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1485c2526597SStephen Boyd .num_parents = 1, 1486c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1487c2526597SStephen Boyd .ops = &clk_branch2_ops, 1488c2526597SStephen Boyd }, 1489c2526597SStephen Boyd }, 1490c2526597SStephen Boyd }; 1491c2526597SStephen Boyd 1492c2526597SStephen Boyd static struct clk_branch smmu_mdp_axi_clk = { 1493c2526597SStephen Boyd .halt_reg = 0x2458, 1494c2526597SStephen Boyd .clkr = { 1495c2526597SStephen Boyd .enable_reg = 0x2458, 1496c2526597SStephen Boyd .enable_mask = BIT(0), 1497c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1498c2526597SStephen Boyd .name = "smmu_mdp_axi_clk", 1499c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1500c2526597SStephen Boyd .num_parents = 1, 1501c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1502c2526597SStephen Boyd .ops = &clk_branch2_ops, 1503c2526597SStephen Boyd }, 1504c2526597SStephen Boyd }, 1505c2526597SStephen Boyd }; 1506c2526597SStephen Boyd 1507c2526597SStephen Boyd static struct clk_branch mmagic_video_axi_clk = { 1508c2526597SStephen Boyd .halt_reg = 0x1194, 1509c2526597SStephen Boyd .clkr = { 1510c2526597SStephen Boyd .enable_reg = 0x1194, 1511c2526597SStephen Boyd .enable_mask = BIT(0), 1512c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1513c2526597SStephen Boyd .name = "mmagic_video_axi_clk", 1514c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1515c2526597SStephen Boyd .num_parents = 1, 1516c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1517c2526597SStephen Boyd .ops = &clk_branch2_ops, 1518c2526597SStephen Boyd }, 1519c2526597SStephen Boyd }, 1520c2526597SStephen Boyd }; 1521c2526597SStephen Boyd 1522c2526597SStephen Boyd static struct clk_branch mmagic_video_noc_cfg_ahb_clk = { 1523c2526597SStephen Boyd .halt_reg = 0x1198, 1524c2526597SStephen Boyd .clkr = { 1525c2526597SStephen Boyd .enable_reg = 0x1198, 1526c2526597SStephen Boyd .enable_mask = BIT(0), 1527c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1528c2526597SStephen Boyd .name = "mmagic_video_noc_cfg_ahb_clk", 1529c2526597SStephen Boyd .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1530c2526597SStephen Boyd .num_parents = 1, 1531c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1532c2526597SStephen Boyd .ops = &clk_branch2_ops, 1533c2526597SStephen Boyd }, 1534c2526597SStephen Boyd }, 1535c2526597SStephen Boyd }; 1536c2526597SStephen Boyd 1537c2526597SStephen Boyd static struct clk_branch smmu_video_ahb_clk = { 1538c2526597SStephen Boyd .halt_reg = 0x1174, 1539c2526597SStephen Boyd .clkr = { 1540c2526597SStephen Boyd .enable_reg = 0x1174, 1541c2526597SStephen Boyd .enable_mask = BIT(0), 1542c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1543c2526597SStephen Boyd .name = "smmu_video_ahb_clk", 1544c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1545c2526597SStephen Boyd .num_parents = 1, 1546c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1547c2526597SStephen Boyd .ops = &clk_branch2_ops, 1548c2526597SStephen Boyd }, 1549c2526597SStephen Boyd }, 1550c2526597SStephen Boyd }; 1551c2526597SStephen Boyd 1552c2526597SStephen Boyd static struct clk_branch smmu_video_axi_clk = { 1553c2526597SStephen Boyd .halt_reg = 0x1178, 1554c2526597SStephen Boyd .clkr = { 1555c2526597SStephen Boyd .enable_reg = 0x1178, 1556c2526597SStephen Boyd .enable_mask = BIT(0), 1557c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1558c2526597SStephen Boyd .name = "smmu_video_axi_clk", 1559c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1560c2526597SStephen Boyd .num_parents = 1, 1561c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1562c2526597SStephen Boyd .ops = &clk_branch2_ops, 1563c2526597SStephen Boyd }, 1564c2526597SStephen Boyd }, 1565c2526597SStephen Boyd }; 1566c2526597SStephen Boyd 1567c2526597SStephen Boyd static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { 1568c2526597SStephen Boyd .halt_reg = 0x5298, 1569c2526597SStephen Boyd .clkr = { 1570c2526597SStephen Boyd .enable_reg = 0x5298, 1571c2526597SStephen Boyd .enable_mask = BIT(0), 1572c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1573c2526597SStephen Boyd .name = "mmagic_bimc_noc_cfg_ahb_clk", 1574c2526597SStephen Boyd .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1575c2526597SStephen Boyd .num_parents = 1, 1576c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1577c2526597SStephen Boyd .ops = &clk_branch2_ops, 1578c2526597SStephen Boyd }, 1579c2526597SStephen Boyd }, 1580c2526597SStephen Boyd }; 1581c2526597SStephen Boyd 1582c2526597SStephen Boyd static struct clk_branch gpu_gx_gfx3d_clk = { 1583c2526597SStephen Boyd .halt_reg = 0x4028, 1584c2526597SStephen Boyd .clkr = { 1585c2526597SStephen Boyd .enable_reg = 0x4028, 1586c2526597SStephen Boyd .enable_mask = BIT(0), 1587c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1588c2526597SStephen Boyd .name = "gpu_gx_gfx3d_clk", 1589c2526597SStephen Boyd .parent_names = (const char *[]){ "gfx3d_clk_src" }, 1590c2526597SStephen Boyd .num_parents = 1, 1591c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1592c2526597SStephen Boyd .ops = &clk_branch2_ops, 1593c2526597SStephen Boyd }, 1594c2526597SStephen Boyd }, 1595c2526597SStephen Boyd }; 1596c2526597SStephen Boyd 1597c2526597SStephen Boyd static struct clk_branch gpu_gx_rbbmtimer_clk = { 1598c2526597SStephen Boyd .halt_reg = 0x40b0, 1599c2526597SStephen Boyd .clkr = { 1600c2526597SStephen Boyd .enable_reg = 0x40b0, 1601c2526597SStephen Boyd .enable_mask = BIT(0), 1602c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1603c2526597SStephen Boyd .name = "gpu_gx_rbbmtimer_clk", 1604c2526597SStephen Boyd .parent_names = (const char *[]){ "rbbmtimer_clk_src" }, 1605c2526597SStephen Boyd .num_parents = 1, 1606c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1607c2526597SStephen Boyd .ops = &clk_branch2_ops, 1608c2526597SStephen Boyd }, 1609c2526597SStephen Boyd }, 1610c2526597SStephen Boyd }; 1611c2526597SStephen Boyd 1612c2526597SStephen Boyd static struct clk_branch gpu_ahb_clk = { 1613c2526597SStephen Boyd .halt_reg = 0x403c, 1614c2526597SStephen Boyd .clkr = { 1615c2526597SStephen Boyd .enable_reg = 0x403c, 1616c2526597SStephen Boyd .enable_mask = BIT(0), 1617c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1618c2526597SStephen Boyd .name = "gpu_ahb_clk", 1619c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1620c2526597SStephen Boyd .num_parents = 1, 1621c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1622c2526597SStephen Boyd .ops = &clk_branch2_ops, 1623c2526597SStephen Boyd }, 1624c2526597SStephen Boyd }, 1625c2526597SStephen Boyd }; 1626c2526597SStephen Boyd 1627c2526597SStephen Boyd static struct clk_branch gpu_aon_isense_clk = { 1628c2526597SStephen Boyd .halt_reg = 0x4044, 1629c2526597SStephen Boyd .clkr = { 1630c2526597SStephen Boyd .enable_reg = 0x4044, 1631c2526597SStephen Boyd .enable_mask = BIT(0), 1632c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1633c2526597SStephen Boyd .name = "gpu_aon_isense_clk", 1634c2526597SStephen Boyd .parent_names = (const char *[]){ "isense_clk_src" }, 1635c2526597SStephen Boyd .num_parents = 1, 1636c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1637c2526597SStephen Boyd .ops = &clk_branch2_ops, 1638c2526597SStephen Boyd }, 1639c2526597SStephen Boyd }, 1640c2526597SStephen Boyd }; 1641c2526597SStephen Boyd 1642c2526597SStephen Boyd static struct clk_branch vmem_maxi_clk = { 1643c2526597SStephen Boyd .halt_reg = 0x1204, 1644c2526597SStephen Boyd .clkr = { 1645c2526597SStephen Boyd .enable_reg = 0x1204, 1646c2526597SStephen Boyd .enable_mask = BIT(0), 1647c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1648c2526597SStephen Boyd .name = "vmem_maxi_clk", 1649c2526597SStephen Boyd .parent_names = (const char *[]){ "maxi_clk_src" }, 1650c2526597SStephen Boyd .num_parents = 1, 1651c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1652c2526597SStephen Boyd .ops = &clk_branch2_ops, 1653c2526597SStephen Boyd }, 1654c2526597SStephen Boyd }, 1655c2526597SStephen Boyd }; 1656c2526597SStephen Boyd 1657c2526597SStephen Boyd static struct clk_branch vmem_ahb_clk = { 1658c2526597SStephen Boyd .halt_reg = 0x1208, 1659c2526597SStephen Boyd .clkr = { 1660c2526597SStephen Boyd .enable_reg = 0x1208, 1661c2526597SStephen Boyd .enable_mask = BIT(0), 1662c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1663c2526597SStephen Boyd .name = "vmem_ahb_clk", 1664c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1665c2526597SStephen Boyd .num_parents = 1, 1666c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1667c2526597SStephen Boyd .ops = &clk_branch2_ops, 1668c2526597SStephen Boyd }, 1669c2526597SStephen Boyd }, 1670c2526597SStephen Boyd }; 1671c2526597SStephen Boyd 1672c2526597SStephen Boyd static struct clk_branch mmss_rbcpr_clk = { 1673c2526597SStephen Boyd .halt_reg = 0x4084, 1674c2526597SStephen Boyd .clkr = { 1675c2526597SStephen Boyd .enable_reg = 0x4084, 1676c2526597SStephen Boyd .enable_mask = BIT(0), 1677c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1678c2526597SStephen Boyd .name = "mmss_rbcpr_clk", 1679c2526597SStephen Boyd .parent_names = (const char *[]){ "rbcpr_clk_src" }, 1680c2526597SStephen Boyd .num_parents = 1, 1681c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1682c2526597SStephen Boyd .ops = &clk_branch2_ops, 1683c2526597SStephen Boyd }, 1684c2526597SStephen Boyd }, 1685c2526597SStephen Boyd }; 1686c2526597SStephen Boyd 1687c2526597SStephen Boyd static struct clk_branch mmss_rbcpr_ahb_clk = { 1688c2526597SStephen Boyd .halt_reg = 0x4088, 1689c2526597SStephen Boyd .clkr = { 1690c2526597SStephen Boyd .enable_reg = 0x4088, 1691c2526597SStephen Boyd .enable_mask = BIT(0), 1692c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1693c2526597SStephen Boyd .name = "mmss_rbcpr_ahb_clk", 1694c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1695c2526597SStephen Boyd .num_parents = 1, 1696c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1697c2526597SStephen Boyd .ops = &clk_branch2_ops, 1698c2526597SStephen Boyd }, 1699c2526597SStephen Boyd }, 1700c2526597SStephen Boyd }; 1701c2526597SStephen Boyd 1702c2526597SStephen Boyd static struct clk_branch video_core_clk = { 1703c2526597SStephen Boyd .halt_reg = 0x1028, 1704c2526597SStephen Boyd .clkr = { 1705c2526597SStephen Boyd .enable_reg = 0x1028, 1706c2526597SStephen Boyd .enable_mask = BIT(0), 1707c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1708c2526597SStephen Boyd .name = "video_core_clk", 1709c2526597SStephen Boyd .parent_names = (const char *[]){ "video_core_clk_src" }, 1710c2526597SStephen Boyd .num_parents = 1, 1711c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1712c2526597SStephen Boyd .ops = &clk_branch2_ops, 1713c2526597SStephen Boyd }, 1714c2526597SStephen Boyd }, 1715c2526597SStephen Boyd }; 1716c2526597SStephen Boyd 1717c2526597SStephen Boyd static struct clk_branch video_axi_clk = { 1718c2526597SStephen Boyd .halt_reg = 0x1034, 1719c2526597SStephen Boyd .clkr = { 1720c2526597SStephen Boyd .enable_reg = 0x1034, 1721c2526597SStephen Boyd .enable_mask = BIT(0), 1722c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1723c2526597SStephen Boyd .name = "video_axi_clk", 1724c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1725c2526597SStephen Boyd .num_parents = 1, 1726c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1727c2526597SStephen Boyd .ops = &clk_branch2_ops, 1728c2526597SStephen Boyd }, 1729c2526597SStephen Boyd }, 1730c2526597SStephen Boyd }; 1731c2526597SStephen Boyd 1732c2526597SStephen Boyd static struct clk_branch video_maxi_clk = { 1733c2526597SStephen Boyd .halt_reg = 0x1038, 1734c2526597SStephen Boyd .clkr = { 1735c2526597SStephen Boyd .enable_reg = 0x1038, 1736c2526597SStephen Boyd .enable_mask = BIT(0), 1737c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1738c2526597SStephen Boyd .name = "video_maxi_clk", 1739c2526597SStephen Boyd .parent_names = (const char *[]){ "maxi_clk_src" }, 1740c2526597SStephen Boyd .num_parents = 1, 1741c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1742c2526597SStephen Boyd .ops = &clk_branch2_ops, 1743c2526597SStephen Boyd }, 1744c2526597SStephen Boyd }, 1745c2526597SStephen Boyd }; 1746c2526597SStephen Boyd 1747c2526597SStephen Boyd static struct clk_branch video_ahb_clk = { 1748c2526597SStephen Boyd .halt_reg = 0x1030, 1749c2526597SStephen Boyd .clkr = { 1750c2526597SStephen Boyd .enable_reg = 0x1030, 1751c2526597SStephen Boyd .enable_mask = BIT(0), 1752c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1753c2526597SStephen Boyd .name = "video_ahb_clk", 1754c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1755c2526597SStephen Boyd .num_parents = 1, 1756c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1757c2526597SStephen Boyd .ops = &clk_branch2_ops, 1758c2526597SStephen Boyd }, 1759c2526597SStephen Boyd }, 1760c2526597SStephen Boyd }; 1761c2526597SStephen Boyd 1762c2526597SStephen Boyd static struct clk_branch video_subcore0_clk = { 1763c2526597SStephen Boyd .halt_reg = 0x1048, 1764c2526597SStephen Boyd .clkr = { 1765c2526597SStephen Boyd .enable_reg = 0x1048, 1766c2526597SStephen Boyd .enable_mask = BIT(0), 1767c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1768c2526597SStephen Boyd .name = "video_subcore0_clk", 1769c2526597SStephen Boyd .parent_names = (const char *[]){ "video_subcore0_clk_src" }, 1770c2526597SStephen Boyd .num_parents = 1, 1771c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1772c2526597SStephen Boyd .ops = &clk_branch2_ops, 1773c2526597SStephen Boyd }, 1774c2526597SStephen Boyd }, 1775c2526597SStephen Boyd }; 1776c2526597SStephen Boyd 1777c2526597SStephen Boyd static struct clk_branch video_subcore1_clk = { 1778c2526597SStephen Boyd .halt_reg = 0x104c, 1779c2526597SStephen Boyd .clkr = { 1780c2526597SStephen Boyd .enable_reg = 0x104c, 1781c2526597SStephen Boyd .enable_mask = BIT(0), 1782c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1783c2526597SStephen Boyd .name = "video_subcore1_clk", 1784c2526597SStephen Boyd .parent_names = (const char *[]){ "video_subcore1_clk_src" }, 1785c2526597SStephen Boyd .num_parents = 1, 1786c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1787c2526597SStephen Boyd .ops = &clk_branch2_ops, 1788c2526597SStephen Boyd }, 1789c2526597SStephen Boyd }, 1790c2526597SStephen Boyd }; 1791c2526597SStephen Boyd 1792c2526597SStephen Boyd static struct clk_branch mdss_ahb_clk = { 1793c2526597SStephen Boyd .halt_reg = 0x2308, 1794c2526597SStephen Boyd .clkr = { 1795c2526597SStephen Boyd .enable_reg = 0x2308, 1796c2526597SStephen Boyd .enable_mask = BIT(0), 1797c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1798c2526597SStephen Boyd .name = "mdss_ahb_clk", 1799c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1800c2526597SStephen Boyd .num_parents = 1, 1801c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1802c2526597SStephen Boyd .ops = &clk_branch2_ops, 1803c2526597SStephen Boyd }, 1804c2526597SStephen Boyd }, 1805c2526597SStephen Boyd }; 1806c2526597SStephen Boyd 1807c2526597SStephen Boyd static struct clk_branch mdss_hdmi_ahb_clk = { 1808c2526597SStephen Boyd .halt_reg = 0x230c, 1809c2526597SStephen Boyd .clkr = { 1810c2526597SStephen Boyd .enable_reg = 0x230c, 1811c2526597SStephen Boyd .enable_mask = BIT(0), 1812c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1813c2526597SStephen Boyd .name = "mdss_hdmi_ahb_clk", 1814c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1815c2526597SStephen Boyd .num_parents = 1, 1816c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1817c2526597SStephen Boyd .ops = &clk_branch2_ops, 1818c2526597SStephen Boyd }, 1819c2526597SStephen Boyd }, 1820c2526597SStephen Boyd }; 1821c2526597SStephen Boyd 1822c2526597SStephen Boyd static struct clk_branch mdss_axi_clk = { 1823c2526597SStephen Boyd .halt_reg = 0x2310, 1824c2526597SStephen Boyd .clkr = { 1825c2526597SStephen Boyd .enable_reg = 0x2310, 1826c2526597SStephen Boyd .enable_mask = BIT(0), 1827c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1828c2526597SStephen Boyd .name = "mdss_axi_clk", 1829c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1830c2526597SStephen Boyd .num_parents = 1, 1831c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1832c2526597SStephen Boyd .ops = &clk_branch2_ops, 1833c2526597SStephen Boyd }, 1834c2526597SStephen Boyd }, 1835c2526597SStephen Boyd }; 1836c2526597SStephen Boyd 1837c2526597SStephen Boyd static struct clk_branch mdss_pclk0_clk = { 1838c2526597SStephen Boyd .halt_reg = 0x2314, 1839c2526597SStephen Boyd .clkr = { 1840c2526597SStephen Boyd .enable_reg = 0x2314, 1841c2526597SStephen Boyd .enable_mask = BIT(0), 1842c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1843c2526597SStephen Boyd .name = "mdss_pclk0_clk", 1844c2526597SStephen Boyd .parent_names = (const char *[]){ "pclk0_clk_src" }, 1845c2526597SStephen Boyd .num_parents = 1, 1846c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1847c2526597SStephen Boyd .ops = &clk_branch2_ops, 1848c2526597SStephen Boyd }, 1849c2526597SStephen Boyd }, 1850c2526597SStephen Boyd }; 1851c2526597SStephen Boyd 1852c2526597SStephen Boyd static struct clk_branch mdss_pclk1_clk = { 1853c2526597SStephen Boyd .halt_reg = 0x2318, 1854c2526597SStephen Boyd .clkr = { 1855c2526597SStephen Boyd .enable_reg = 0x2318, 1856c2526597SStephen Boyd .enable_mask = BIT(0), 1857c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1858c2526597SStephen Boyd .name = "mdss_pclk1_clk", 1859c2526597SStephen Boyd .parent_names = (const char *[]){ "pclk1_clk_src" }, 1860c2526597SStephen Boyd .num_parents = 1, 1861c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1862c2526597SStephen Boyd .ops = &clk_branch2_ops, 1863c2526597SStephen Boyd }, 1864c2526597SStephen Boyd }, 1865c2526597SStephen Boyd }; 1866c2526597SStephen Boyd 1867c2526597SStephen Boyd static struct clk_branch mdss_mdp_clk = { 1868c2526597SStephen Boyd .halt_reg = 0x231c, 1869c2526597SStephen Boyd .clkr = { 1870c2526597SStephen Boyd .enable_reg = 0x231c, 1871c2526597SStephen Boyd .enable_mask = BIT(0), 1872c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1873c2526597SStephen Boyd .name = "mdss_mdp_clk", 1874c2526597SStephen Boyd .parent_names = (const char *[]){ "mdp_clk_src" }, 1875c2526597SStephen Boyd .num_parents = 1, 1876c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1877c2526597SStephen Boyd .ops = &clk_branch2_ops, 1878c2526597SStephen Boyd }, 1879c2526597SStephen Boyd }, 1880c2526597SStephen Boyd }; 1881c2526597SStephen Boyd 1882c2526597SStephen Boyd static struct clk_branch mdss_extpclk_clk = { 1883c2526597SStephen Boyd .halt_reg = 0x2324, 1884c2526597SStephen Boyd .clkr = { 1885c2526597SStephen Boyd .enable_reg = 0x2324, 1886c2526597SStephen Boyd .enable_mask = BIT(0), 1887c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1888c2526597SStephen Boyd .name = "mdss_extpclk_clk", 1889c2526597SStephen Boyd .parent_names = (const char *[]){ "extpclk_clk_src" }, 1890c2526597SStephen Boyd .num_parents = 1, 1891c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1892c2526597SStephen Boyd .ops = &clk_branch2_ops, 1893c2526597SStephen Boyd }, 1894c2526597SStephen Boyd }, 1895c2526597SStephen Boyd }; 1896c2526597SStephen Boyd 1897c2526597SStephen Boyd static struct clk_branch mdss_vsync_clk = { 1898c2526597SStephen Boyd .halt_reg = 0x2328, 1899c2526597SStephen Boyd .clkr = { 1900c2526597SStephen Boyd .enable_reg = 0x2328, 1901c2526597SStephen Boyd .enable_mask = BIT(0), 1902c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1903c2526597SStephen Boyd .name = "mdss_vsync_clk", 1904c2526597SStephen Boyd .parent_names = (const char *[]){ "vsync_clk_src" }, 1905c2526597SStephen Boyd .num_parents = 1, 1906c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1907c2526597SStephen Boyd .ops = &clk_branch2_ops, 1908c2526597SStephen Boyd }, 1909c2526597SStephen Boyd }, 1910c2526597SStephen Boyd }; 1911c2526597SStephen Boyd 1912c2526597SStephen Boyd static struct clk_branch mdss_hdmi_clk = { 1913c2526597SStephen Boyd .halt_reg = 0x2338, 1914c2526597SStephen Boyd .clkr = { 1915c2526597SStephen Boyd .enable_reg = 0x2338, 1916c2526597SStephen Boyd .enable_mask = BIT(0), 1917c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1918c2526597SStephen Boyd .name = "mdss_hdmi_clk", 1919c2526597SStephen Boyd .parent_names = (const char *[]){ "hdmi_clk_src" }, 1920c2526597SStephen Boyd .num_parents = 1, 1921c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1922c2526597SStephen Boyd .ops = &clk_branch2_ops, 1923c2526597SStephen Boyd }, 1924c2526597SStephen Boyd }, 1925c2526597SStephen Boyd }; 1926c2526597SStephen Boyd 1927c2526597SStephen Boyd static struct clk_branch mdss_byte0_clk = { 1928c2526597SStephen Boyd .halt_reg = 0x233c, 1929c2526597SStephen Boyd .clkr = { 1930c2526597SStephen Boyd .enable_reg = 0x233c, 1931c2526597SStephen Boyd .enable_mask = BIT(0), 1932c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1933c2526597SStephen Boyd .name = "mdss_byte0_clk", 1934c2526597SStephen Boyd .parent_names = (const char *[]){ "byte0_clk_src" }, 1935c2526597SStephen Boyd .num_parents = 1, 1936c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1937c2526597SStephen Boyd .ops = &clk_branch2_ops, 1938c2526597SStephen Boyd }, 1939c2526597SStephen Boyd }, 1940c2526597SStephen Boyd }; 1941c2526597SStephen Boyd 1942c2526597SStephen Boyd static struct clk_branch mdss_byte1_clk = { 1943c2526597SStephen Boyd .halt_reg = 0x2340, 1944c2526597SStephen Boyd .clkr = { 1945c2526597SStephen Boyd .enable_reg = 0x2340, 1946c2526597SStephen Boyd .enable_mask = BIT(0), 1947c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1948c2526597SStephen Boyd .name = "mdss_byte1_clk", 1949c2526597SStephen Boyd .parent_names = (const char *[]){ "byte1_clk_src" }, 1950c2526597SStephen Boyd .num_parents = 1, 1951c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1952c2526597SStephen Boyd .ops = &clk_branch2_ops, 1953c2526597SStephen Boyd }, 1954c2526597SStephen Boyd }, 1955c2526597SStephen Boyd }; 1956c2526597SStephen Boyd 1957c2526597SStephen Boyd static struct clk_branch mdss_esc0_clk = { 1958c2526597SStephen Boyd .halt_reg = 0x2344, 1959c2526597SStephen Boyd .clkr = { 1960c2526597SStephen Boyd .enable_reg = 0x2344, 1961c2526597SStephen Boyd .enable_mask = BIT(0), 1962c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1963c2526597SStephen Boyd .name = "mdss_esc0_clk", 1964c2526597SStephen Boyd .parent_names = (const char *[]){ "esc0_clk_src" }, 1965c2526597SStephen Boyd .num_parents = 1, 1966c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1967c2526597SStephen Boyd .ops = &clk_branch2_ops, 1968c2526597SStephen Boyd }, 1969c2526597SStephen Boyd }, 1970c2526597SStephen Boyd }; 1971c2526597SStephen Boyd 1972c2526597SStephen Boyd static struct clk_branch mdss_esc1_clk = { 1973c2526597SStephen Boyd .halt_reg = 0x2348, 1974c2526597SStephen Boyd .clkr = { 1975c2526597SStephen Boyd .enable_reg = 0x2348, 1976c2526597SStephen Boyd .enable_mask = BIT(0), 1977c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1978c2526597SStephen Boyd .name = "mdss_esc1_clk", 1979c2526597SStephen Boyd .parent_names = (const char *[]){ "esc1_clk_src" }, 1980c2526597SStephen Boyd .num_parents = 1, 1981c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1982c2526597SStephen Boyd .ops = &clk_branch2_ops, 1983c2526597SStephen Boyd }, 1984c2526597SStephen Boyd }, 1985c2526597SStephen Boyd }; 1986c2526597SStephen Boyd 1987c2526597SStephen Boyd static struct clk_branch camss_top_ahb_clk = { 1988c2526597SStephen Boyd .halt_reg = 0x3484, 1989c2526597SStephen Boyd .clkr = { 1990c2526597SStephen Boyd .enable_reg = 0x3484, 1991c2526597SStephen Boyd .enable_mask = BIT(0), 1992c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1993c2526597SStephen Boyd .name = "camss_top_ahb_clk", 1994c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1995c2526597SStephen Boyd .num_parents = 1, 1996c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1997c2526597SStephen Boyd .ops = &clk_branch2_ops, 1998c2526597SStephen Boyd }, 1999c2526597SStephen Boyd }, 2000c2526597SStephen Boyd }; 2001c2526597SStephen Boyd 2002c2526597SStephen Boyd static struct clk_branch camss_ahb_clk = { 2003c2526597SStephen Boyd .halt_reg = 0x348c, 2004c2526597SStephen Boyd .clkr = { 2005c2526597SStephen Boyd .enable_reg = 0x348c, 2006c2526597SStephen Boyd .enable_mask = BIT(0), 2007c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2008c2526597SStephen Boyd .name = "camss_ahb_clk", 2009c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2010c2526597SStephen Boyd .num_parents = 1, 2011c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2012c2526597SStephen Boyd .ops = &clk_branch2_ops, 2013c2526597SStephen Boyd }, 2014c2526597SStephen Boyd }, 2015c2526597SStephen Boyd }; 2016c2526597SStephen Boyd 2017c2526597SStephen Boyd static struct clk_branch camss_micro_ahb_clk = { 2018c2526597SStephen Boyd .halt_reg = 0x3494, 2019c2526597SStephen Boyd .clkr = { 2020c2526597SStephen Boyd .enable_reg = 0x3494, 2021c2526597SStephen Boyd .enable_mask = BIT(0), 2022c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2023c2526597SStephen Boyd .name = "camss_micro_ahb_clk", 2024c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2025c2526597SStephen Boyd .num_parents = 1, 2026c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2027c2526597SStephen Boyd .ops = &clk_branch2_ops, 2028c2526597SStephen Boyd }, 2029c2526597SStephen Boyd }, 2030c2526597SStephen Boyd }; 2031c2526597SStephen Boyd 2032c2526597SStephen Boyd static struct clk_branch camss_gp0_clk = { 2033c2526597SStephen Boyd .halt_reg = 0x3444, 2034c2526597SStephen Boyd .clkr = { 2035c2526597SStephen Boyd .enable_reg = 0x3444, 2036c2526597SStephen Boyd .enable_mask = BIT(0), 2037c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2038c2526597SStephen Boyd .name = "camss_gp0_clk", 2039c2526597SStephen Boyd .parent_names = (const char *[]){ "camss_gp0_clk_src" }, 2040c2526597SStephen Boyd .num_parents = 1, 2041c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2042c2526597SStephen Boyd .ops = &clk_branch2_ops, 2043c2526597SStephen Boyd }, 2044c2526597SStephen Boyd }, 2045c2526597SStephen Boyd }; 2046c2526597SStephen Boyd 2047c2526597SStephen Boyd static struct clk_branch camss_gp1_clk = { 2048c2526597SStephen Boyd .halt_reg = 0x3474, 2049c2526597SStephen Boyd .clkr = { 2050c2526597SStephen Boyd .enable_reg = 0x3474, 2051c2526597SStephen Boyd .enable_mask = BIT(0), 2052c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2053c2526597SStephen Boyd .name = "camss_gp1_clk", 2054c2526597SStephen Boyd .parent_names = (const char *[]){ "camss_gp1_clk_src" }, 2055c2526597SStephen Boyd .num_parents = 1, 2056c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2057c2526597SStephen Boyd .ops = &clk_branch2_ops, 2058c2526597SStephen Boyd }, 2059c2526597SStephen Boyd }, 2060c2526597SStephen Boyd }; 2061c2526597SStephen Boyd 2062c2526597SStephen Boyd static struct clk_branch camss_mclk0_clk = { 2063c2526597SStephen Boyd .halt_reg = 0x3384, 2064c2526597SStephen Boyd .clkr = { 2065c2526597SStephen Boyd .enable_reg = 0x3384, 2066c2526597SStephen Boyd .enable_mask = BIT(0), 2067c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2068c2526597SStephen Boyd .name = "camss_mclk0_clk", 2069c2526597SStephen Boyd .parent_names = (const char *[]){ "mclk0_clk_src" }, 2070c2526597SStephen Boyd .num_parents = 1, 2071c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2072c2526597SStephen Boyd .ops = &clk_branch2_ops, 2073c2526597SStephen Boyd }, 2074c2526597SStephen Boyd }, 2075c2526597SStephen Boyd }; 2076c2526597SStephen Boyd 2077c2526597SStephen Boyd static struct clk_branch camss_mclk1_clk = { 2078c2526597SStephen Boyd .halt_reg = 0x33b4, 2079c2526597SStephen Boyd .clkr = { 2080c2526597SStephen Boyd .enable_reg = 0x33b4, 2081c2526597SStephen Boyd .enable_mask = BIT(0), 2082c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2083c2526597SStephen Boyd .name = "camss_mclk1_clk", 2084c2526597SStephen Boyd .parent_names = (const char *[]){ "mclk1_clk_src" }, 2085c2526597SStephen Boyd .num_parents = 1, 2086c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2087c2526597SStephen Boyd .ops = &clk_branch2_ops, 2088c2526597SStephen Boyd }, 2089c2526597SStephen Boyd }, 2090c2526597SStephen Boyd }; 2091c2526597SStephen Boyd 2092c2526597SStephen Boyd static struct clk_branch camss_mclk2_clk = { 2093c2526597SStephen Boyd .halt_reg = 0x33e4, 2094c2526597SStephen Boyd .clkr = { 2095c2526597SStephen Boyd .enable_reg = 0x33e4, 2096c2526597SStephen Boyd .enable_mask = BIT(0), 2097c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2098c2526597SStephen Boyd .name = "camss_mclk2_clk", 2099c2526597SStephen Boyd .parent_names = (const char *[]){ "mclk2_clk_src" }, 2100c2526597SStephen Boyd .num_parents = 1, 2101c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2102c2526597SStephen Boyd .ops = &clk_branch2_ops, 2103c2526597SStephen Boyd }, 2104c2526597SStephen Boyd }, 2105c2526597SStephen Boyd }; 2106c2526597SStephen Boyd 2107c2526597SStephen Boyd static struct clk_branch camss_mclk3_clk = { 2108c2526597SStephen Boyd .halt_reg = 0x3414, 2109c2526597SStephen Boyd .clkr = { 2110c2526597SStephen Boyd .enable_reg = 0x3414, 2111c2526597SStephen Boyd .enable_mask = BIT(0), 2112c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2113c2526597SStephen Boyd .name = "camss_mclk3_clk", 2114c2526597SStephen Boyd .parent_names = (const char *[]){ "mclk3_clk_src" }, 2115c2526597SStephen Boyd .num_parents = 1, 2116c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2117c2526597SStephen Boyd .ops = &clk_branch2_ops, 2118c2526597SStephen Boyd }, 2119c2526597SStephen Boyd }, 2120c2526597SStephen Boyd }; 2121c2526597SStephen Boyd 2122c2526597SStephen Boyd static struct clk_branch camss_cci_clk = { 2123c2526597SStephen Boyd .halt_reg = 0x3344, 2124c2526597SStephen Boyd .clkr = { 2125c2526597SStephen Boyd .enable_reg = 0x3344, 2126c2526597SStephen Boyd .enable_mask = BIT(0), 2127c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2128c2526597SStephen Boyd .name = "camss_cci_clk", 2129c2526597SStephen Boyd .parent_names = (const char *[]){ "cci_clk_src" }, 2130c2526597SStephen Boyd .num_parents = 1, 2131c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2132c2526597SStephen Boyd .ops = &clk_branch2_ops, 2133c2526597SStephen Boyd }, 2134c2526597SStephen Boyd }, 2135c2526597SStephen Boyd }; 2136c2526597SStephen Boyd 2137c2526597SStephen Boyd static struct clk_branch camss_cci_ahb_clk = { 2138c2526597SStephen Boyd .halt_reg = 0x3348, 2139c2526597SStephen Boyd .clkr = { 2140c2526597SStephen Boyd .enable_reg = 0x3348, 2141c2526597SStephen Boyd .enable_mask = BIT(0), 2142c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2143c2526597SStephen Boyd .name = "camss_cci_ahb_clk", 2144c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2145c2526597SStephen Boyd .num_parents = 1, 2146c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2147c2526597SStephen Boyd .ops = &clk_branch2_ops, 2148c2526597SStephen Boyd }, 2149c2526597SStephen Boyd }, 2150c2526597SStephen Boyd }; 2151c2526597SStephen Boyd 2152c2526597SStephen Boyd static struct clk_branch camss_csi0phytimer_clk = { 2153c2526597SStephen Boyd .halt_reg = 0x3024, 2154c2526597SStephen Boyd .clkr = { 2155c2526597SStephen Boyd .enable_reg = 0x3024, 2156c2526597SStephen Boyd .enable_mask = BIT(0), 2157c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2158c2526597SStephen Boyd .name = "camss_csi0phytimer_clk", 2159c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0phytimer_clk_src" }, 2160c2526597SStephen Boyd .num_parents = 1, 2161c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2162c2526597SStephen Boyd .ops = &clk_branch2_ops, 2163c2526597SStephen Boyd }, 2164c2526597SStephen Boyd }, 2165c2526597SStephen Boyd }; 2166c2526597SStephen Boyd 2167c2526597SStephen Boyd static struct clk_branch camss_csi1phytimer_clk = { 2168c2526597SStephen Boyd .halt_reg = 0x3054, 2169c2526597SStephen Boyd .clkr = { 2170c2526597SStephen Boyd .enable_reg = 0x3054, 2171c2526597SStephen Boyd .enable_mask = BIT(0), 2172c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2173c2526597SStephen Boyd .name = "camss_csi1phytimer_clk", 2174c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1phytimer_clk_src" }, 2175c2526597SStephen Boyd .num_parents = 1, 2176c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2177c2526597SStephen Boyd .ops = &clk_branch2_ops, 2178c2526597SStephen Boyd }, 2179c2526597SStephen Boyd }, 2180c2526597SStephen Boyd }; 2181c2526597SStephen Boyd 2182c2526597SStephen Boyd static struct clk_branch camss_csi2phytimer_clk = { 2183c2526597SStephen Boyd .halt_reg = 0x3084, 2184c2526597SStephen Boyd .clkr = { 2185c2526597SStephen Boyd .enable_reg = 0x3084, 2186c2526597SStephen Boyd .enable_mask = BIT(0), 2187c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2188c2526597SStephen Boyd .name = "camss_csi2phytimer_clk", 2189c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2phytimer_clk_src" }, 2190c2526597SStephen Boyd .num_parents = 1, 2191c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2192c2526597SStephen Boyd .ops = &clk_branch2_ops, 2193c2526597SStephen Boyd }, 2194c2526597SStephen Boyd }, 2195c2526597SStephen Boyd }; 2196c2526597SStephen Boyd 2197c2526597SStephen Boyd static struct clk_branch camss_csiphy0_3p_clk = { 2198c2526597SStephen Boyd .halt_reg = 0x3234, 2199c2526597SStephen Boyd .clkr = { 2200c2526597SStephen Boyd .enable_reg = 0x3234, 2201c2526597SStephen Boyd .enable_mask = BIT(0), 2202c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2203c2526597SStephen Boyd .name = "camss_csiphy0_3p_clk", 2204c2526597SStephen Boyd .parent_names = (const char *[]){ "csiphy0_3p_clk_src" }, 2205c2526597SStephen Boyd .num_parents = 1, 2206c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2207c2526597SStephen Boyd .ops = &clk_branch2_ops, 2208c2526597SStephen Boyd }, 2209c2526597SStephen Boyd }, 2210c2526597SStephen Boyd }; 2211c2526597SStephen Boyd 2212c2526597SStephen Boyd static struct clk_branch camss_csiphy1_3p_clk = { 2213c2526597SStephen Boyd .halt_reg = 0x3254, 2214c2526597SStephen Boyd .clkr = { 2215c2526597SStephen Boyd .enable_reg = 0x3254, 2216c2526597SStephen Boyd .enable_mask = BIT(0), 2217c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2218c2526597SStephen Boyd .name = "camss_csiphy1_3p_clk", 2219c2526597SStephen Boyd .parent_names = (const char *[]){ "csiphy1_3p_clk_src" }, 2220c2526597SStephen Boyd .num_parents = 1, 2221c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2222c2526597SStephen Boyd .ops = &clk_branch2_ops, 2223c2526597SStephen Boyd }, 2224c2526597SStephen Boyd }, 2225c2526597SStephen Boyd }; 2226c2526597SStephen Boyd 2227c2526597SStephen Boyd static struct clk_branch camss_csiphy2_3p_clk = { 2228c2526597SStephen Boyd .halt_reg = 0x3274, 2229c2526597SStephen Boyd .clkr = { 2230c2526597SStephen Boyd .enable_reg = 0x3274, 2231c2526597SStephen Boyd .enable_mask = BIT(0), 2232c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2233c2526597SStephen Boyd .name = "camss_csiphy2_3p_clk", 2234c2526597SStephen Boyd .parent_names = (const char *[]){ "csiphy2_3p_clk_src" }, 2235c2526597SStephen Boyd .num_parents = 1, 2236c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2237c2526597SStephen Boyd .ops = &clk_branch2_ops, 2238c2526597SStephen Boyd }, 2239c2526597SStephen Boyd }, 2240c2526597SStephen Boyd }; 2241c2526597SStephen Boyd 2242c2526597SStephen Boyd static struct clk_branch camss_jpeg0_clk = { 2243c2526597SStephen Boyd .halt_reg = 0x35a8, 2244c2526597SStephen Boyd .clkr = { 2245c2526597SStephen Boyd .enable_reg = 0x35a8, 2246c2526597SStephen Boyd .enable_mask = BIT(0), 2247c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2248c2526597SStephen Boyd .name = "camss_jpeg0_clk", 2249c2526597SStephen Boyd .parent_names = (const char *[]){ "jpeg0_clk_src" }, 2250c2526597SStephen Boyd .num_parents = 1, 2251c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2252c2526597SStephen Boyd .ops = &clk_branch2_ops, 2253c2526597SStephen Boyd }, 2254c2526597SStephen Boyd }, 2255c2526597SStephen Boyd }; 2256c2526597SStephen Boyd 2257c2526597SStephen Boyd static struct clk_branch camss_jpeg2_clk = { 2258c2526597SStephen Boyd .halt_reg = 0x35b0, 2259c2526597SStephen Boyd .clkr = { 2260c2526597SStephen Boyd .enable_reg = 0x35b0, 2261c2526597SStephen Boyd .enable_mask = BIT(0), 2262c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2263c2526597SStephen Boyd .name = "camss_jpeg2_clk", 2264c2526597SStephen Boyd .parent_names = (const char *[]){ "jpeg2_clk_src" }, 2265c2526597SStephen Boyd .num_parents = 1, 2266c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2267c2526597SStephen Boyd .ops = &clk_branch2_ops, 2268c2526597SStephen Boyd }, 2269c2526597SStephen Boyd }, 2270c2526597SStephen Boyd }; 2271c2526597SStephen Boyd 2272c2526597SStephen Boyd static struct clk_branch camss_jpeg_dma_clk = { 2273c2526597SStephen Boyd .halt_reg = 0x35c0, 2274c2526597SStephen Boyd .clkr = { 2275c2526597SStephen Boyd .enable_reg = 0x35c0, 2276c2526597SStephen Boyd .enable_mask = BIT(0), 2277c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2278c2526597SStephen Boyd .name = "camss_jpeg_dma_clk", 2279c2526597SStephen Boyd .parent_names = (const char *[]){ "jpeg_dma_clk_src" }, 2280c2526597SStephen Boyd .num_parents = 1, 2281c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2282c2526597SStephen Boyd .ops = &clk_branch2_ops, 2283c2526597SStephen Boyd }, 2284c2526597SStephen Boyd }, 2285c2526597SStephen Boyd }; 2286c2526597SStephen Boyd 2287c2526597SStephen Boyd static struct clk_branch camss_jpeg_ahb_clk = { 2288c2526597SStephen Boyd .halt_reg = 0x35b4, 2289c2526597SStephen Boyd .clkr = { 2290c2526597SStephen Boyd .enable_reg = 0x35b4, 2291c2526597SStephen Boyd .enable_mask = BIT(0), 2292c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2293c2526597SStephen Boyd .name = "camss_jpeg_ahb_clk", 2294c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2295c2526597SStephen Boyd .num_parents = 1, 2296c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2297c2526597SStephen Boyd .ops = &clk_branch2_ops, 2298c2526597SStephen Boyd }, 2299c2526597SStephen Boyd }, 2300c2526597SStephen Boyd }; 2301c2526597SStephen Boyd 2302c2526597SStephen Boyd static struct clk_branch camss_jpeg_axi_clk = { 2303c2526597SStephen Boyd .halt_reg = 0x35b8, 2304c2526597SStephen Boyd .clkr = { 2305c2526597SStephen Boyd .enable_reg = 0x35b8, 2306c2526597SStephen Boyd .enable_mask = BIT(0), 2307c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2308c2526597SStephen Boyd .name = "camss_jpeg_axi_clk", 2309c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 2310c2526597SStephen Boyd .num_parents = 1, 2311c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2312c2526597SStephen Boyd .ops = &clk_branch2_ops, 2313c2526597SStephen Boyd }, 2314c2526597SStephen Boyd }, 2315c2526597SStephen Boyd }; 2316c2526597SStephen Boyd 2317c2526597SStephen Boyd static struct clk_branch camss_vfe_ahb_clk = { 2318c2526597SStephen Boyd .halt_reg = 0x36b8, 2319c2526597SStephen Boyd .clkr = { 2320c2526597SStephen Boyd .enable_reg = 0x36b8, 2321c2526597SStephen Boyd .enable_mask = BIT(0), 2322c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2323c2526597SStephen Boyd .name = "camss_vfe_ahb_clk", 2324c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2325c2526597SStephen Boyd .num_parents = 1, 2326c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2327c2526597SStephen Boyd .ops = &clk_branch2_ops, 2328c2526597SStephen Boyd }, 2329c2526597SStephen Boyd }, 2330c2526597SStephen Boyd }; 2331c2526597SStephen Boyd 2332c2526597SStephen Boyd static struct clk_branch camss_vfe_axi_clk = { 2333c2526597SStephen Boyd .halt_reg = 0x36bc, 2334c2526597SStephen Boyd .clkr = { 2335c2526597SStephen Boyd .enable_reg = 0x36bc, 2336c2526597SStephen Boyd .enable_mask = BIT(0), 2337c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2338c2526597SStephen Boyd .name = "camss_vfe_axi_clk", 2339c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 2340c2526597SStephen Boyd .num_parents = 1, 2341c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2342c2526597SStephen Boyd .ops = &clk_branch2_ops, 2343c2526597SStephen Boyd }, 2344c2526597SStephen Boyd }, 2345c2526597SStephen Boyd }; 2346c2526597SStephen Boyd 2347c2526597SStephen Boyd static struct clk_branch camss_vfe0_clk = { 2348c2526597SStephen Boyd .halt_reg = 0x36a8, 2349c2526597SStephen Boyd .clkr = { 2350c2526597SStephen Boyd .enable_reg = 0x36a8, 2351c2526597SStephen Boyd .enable_mask = BIT(0), 2352c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2353c2526597SStephen Boyd .name = "camss_vfe0_clk", 2354c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe0_clk_src" }, 2355c2526597SStephen Boyd .num_parents = 1, 2356c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2357c2526597SStephen Boyd .ops = &clk_branch2_ops, 2358c2526597SStephen Boyd }, 2359c2526597SStephen Boyd }, 2360c2526597SStephen Boyd }; 2361c2526597SStephen Boyd 2362c2526597SStephen Boyd static struct clk_branch camss_vfe0_stream_clk = { 2363c2526597SStephen Boyd .halt_reg = 0x3720, 2364c2526597SStephen Boyd .clkr = { 2365c2526597SStephen Boyd .enable_reg = 0x3720, 2366c2526597SStephen Boyd .enable_mask = BIT(0), 2367c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2368c2526597SStephen Boyd .name = "camss_vfe0_stream_clk", 2369c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe0_clk_src" }, 2370c2526597SStephen Boyd .num_parents = 1, 2371c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2372c2526597SStephen Boyd .ops = &clk_branch2_ops, 2373c2526597SStephen Boyd }, 2374c2526597SStephen Boyd }, 2375c2526597SStephen Boyd }; 2376c2526597SStephen Boyd 2377c2526597SStephen Boyd static struct clk_branch camss_vfe0_ahb_clk = { 2378c2526597SStephen Boyd .halt_reg = 0x3668, 2379c2526597SStephen Boyd .clkr = { 2380c2526597SStephen Boyd .enable_reg = 0x3668, 2381c2526597SStephen Boyd .enable_mask = BIT(0), 2382c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2383c2526597SStephen Boyd .name = "camss_vfe0_ahb_clk", 2384c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2385c2526597SStephen Boyd .num_parents = 1, 2386c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2387c2526597SStephen Boyd .ops = &clk_branch2_ops, 2388c2526597SStephen Boyd }, 2389c2526597SStephen Boyd }, 2390c2526597SStephen Boyd }; 2391c2526597SStephen Boyd 2392c2526597SStephen Boyd static struct clk_branch camss_vfe1_clk = { 2393c2526597SStephen Boyd .halt_reg = 0x36ac, 2394c2526597SStephen Boyd .clkr = { 2395c2526597SStephen Boyd .enable_reg = 0x36ac, 2396c2526597SStephen Boyd .enable_mask = BIT(0), 2397c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2398c2526597SStephen Boyd .name = "camss_vfe1_clk", 2399c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe1_clk_src" }, 2400c2526597SStephen Boyd .num_parents = 1, 2401c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2402c2526597SStephen Boyd .ops = &clk_branch2_ops, 2403c2526597SStephen Boyd }, 2404c2526597SStephen Boyd }, 2405c2526597SStephen Boyd }; 2406c2526597SStephen Boyd 2407c2526597SStephen Boyd static struct clk_branch camss_vfe1_stream_clk = { 2408c2526597SStephen Boyd .halt_reg = 0x3724, 2409c2526597SStephen Boyd .clkr = { 2410c2526597SStephen Boyd .enable_reg = 0x3724, 2411c2526597SStephen Boyd .enable_mask = BIT(0), 2412c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2413c2526597SStephen Boyd .name = "camss_vfe1_stream_clk", 2414c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe1_clk_src" }, 2415c2526597SStephen Boyd .num_parents = 1, 2416c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2417c2526597SStephen Boyd .ops = &clk_branch2_ops, 2418c2526597SStephen Boyd }, 2419c2526597SStephen Boyd }, 2420c2526597SStephen Boyd }; 2421c2526597SStephen Boyd 2422c2526597SStephen Boyd static struct clk_branch camss_vfe1_ahb_clk = { 2423c2526597SStephen Boyd .halt_reg = 0x3678, 2424c2526597SStephen Boyd .clkr = { 2425c2526597SStephen Boyd .enable_reg = 0x3678, 2426c2526597SStephen Boyd .enable_mask = BIT(0), 2427c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2428c2526597SStephen Boyd .name = "camss_vfe1_ahb_clk", 2429c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2430c2526597SStephen Boyd .num_parents = 1, 2431c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2432c2526597SStephen Boyd .ops = &clk_branch2_ops, 2433c2526597SStephen Boyd }, 2434c2526597SStephen Boyd }, 2435c2526597SStephen Boyd }; 2436c2526597SStephen Boyd 2437c2526597SStephen Boyd static struct clk_branch camss_csi_vfe0_clk = { 2438c2526597SStephen Boyd .halt_reg = 0x3704, 2439c2526597SStephen Boyd .clkr = { 2440c2526597SStephen Boyd .enable_reg = 0x3704, 2441c2526597SStephen Boyd .enable_mask = BIT(0), 2442c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2443c2526597SStephen Boyd .name = "camss_csi_vfe0_clk", 2444c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe0_clk_src" }, 2445c2526597SStephen Boyd .num_parents = 1, 2446c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2447c2526597SStephen Boyd .ops = &clk_branch2_ops, 2448c2526597SStephen Boyd }, 2449c2526597SStephen Boyd }, 2450c2526597SStephen Boyd }; 2451c2526597SStephen Boyd 2452c2526597SStephen Boyd static struct clk_branch camss_csi_vfe1_clk = { 2453c2526597SStephen Boyd .halt_reg = 0x3714, 2454c2526597SStephen Boyd .clkr = { 2455c2526597SStephen Boyd .enable_reg = 0x3714, 2456c2526597SStephen Boyd .enable_mask = BIT(0), 2457c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2458c2526597SStephen Boyd .name = "camss_csi_vfe1_clk", 2459c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe1_clk_src" }, 2460c2526597SStephen Boyd .num_parents = 1, 2461c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2462c2526597SStephen Boyd .ops = &clk_branch2_ops, 2463c2526597SStephen Boyd }, 2464c2526597SStephen Boyd }, 2465c2526597SStephen Boyd }; 2466c2526597SStephen Boyd 2467c2526597SStephen Boyd static struct clk_branch camss_cpp_vbif_ahb_clk = { 2468c2526597SStephen Boyd .halt_reg = 0x36c8, 2469c2526597SStephen Boyd .clkr = { 2470c2526597SStephen Boyd .enable_reg = 0x36c8, 2471c2526597SStephen Boyd .enable_mask = BIT(0), 2472c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2473c2526597SStephen Boyd .name = "camss_cpp_vbif_ahb_clk", 2474c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2475c2526597SStephen Boyd .num_parents = 1, 2476c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2477c2526597SStephen Boyd .ops = &clk_branch2_ops, 2478c2526597SStephen Boyd }, 2479c2526597SStephen Boyd }, 2480c2526597SStephen Boyd }; 2481c2526597SStephen Boyd 2482c2526597SStephen Boyd static struct clk_branch camss_cpp_axi_clk = { 2483c2526597SStephen Boyd .halt_reg = 0x36c4, 2484c2526597SStephen Boyd .clkr = { 2485c2526597SStephen Boyd .enable_reg = 0x36c4, 2486c2526597SStephen Boyd .enable_mask = BIT(0), 2487c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2488c2526597SStephen Boyd .name = "camss_cpp_axi_clk", 2489c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 2490c2526597SStephen Boyd .num_parents = 1, 2491c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2492c2526597SStephen Boyd .ops = &clk_branch2_ops, 2493c2526597SStephen Boyd }, 2494c2526597SStephen Boyd }, 2495c2526597SStephen Boyd }; 2496c2526597SStephen Boyd 2497c2526597SStephen Boyd static struct clk_branch camss_cpp_clk = { 2498c2526597SStephen Boyd .halt_reg = 0x36b0, 2499c2526597SStephen Boyd .clkr = { 2500c2526597SStephen Boyd .enable_reg = 0x36b0, 2501c2526597SStephen Boyd .enable_mask = BIT(0), 2502c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2503c2526597SStephen Boyd .name = "camss_cpp_clk", 2504c2526597SStephen Boyd .parent_names = (const char *[]){ "cpp_clk_src" }, 2505c2526597SStephen Boyd .num_parents = 1, 2506c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2507c2526597SStephen Boyd .ops = &clk_branch2_ops, 2508c2526597SStephen Boyd }, 2509c2526597SStephen Boyd }, 2510c2526597SStephen Boyd }; 2511c2526597SStephen Boyd 2512c2526597SStephen Boyd static struct clk_branch camss_cpp_ahb_clk = { 2513c2526597SStephen Boyd .halt_reg = 0x36b4, 2514c2526597SStephen Boyd .clkr = { 2515c2526597SStephen Boyd .enable_reg = 0x36b4, 2516c2526597SStephen Boyd .enable_mask = BIT(0), 2517c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2518c2526597SStephen Boyd .name = "camss_cpp_ahb_clk", 2519c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2520c2526597SStephen Boyd .num_parents = 1, 2521c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2522c2526597SStephen Boyd .ops = &clk_branch2_ops, 2523c2526597SStephen Boyd }, 2524c2526597SStephen Boyd }, 2525c2526597SStephen Boyd }; 2526c2526597SStephen Boyd 2527c2526597SStephen Boyd static struct clk_branch camss_csi0_clk = { 2528c2526597SStephen Boyd .halt_reg = 0x30b4, 2529c2526597SStephen Boyd .clkr = { 2530c2526597SStephen Boyd .enable_reg = 0x30b4, 2531c2526597SStephen Boyd .enable_mask = BIT(0), 2532c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2533c2526597SStephen Boyd .name = "camss_csi0_clk", 2534c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0_clk_src" }, 2535c2526597SStephen Boyd .num_parents = 1, 2536c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2537c2526597SStephen Boyd .ops = &clk_branch2_ops, 2538c2526597SStephen Boyd }, 2539c2526597SStephen Boyd }, 2540c2526597SStephen Boyd }; 2541c2526597SStephen Boyd 2542c2526597SStephen Boyd static struct clk_branch camss_csi0_ahb_clk = { 2543c2526597SStephen Boyd .halt_reg = 0x30bc, 2544c2526597SStephen Boyd .clkr = { 2545c2526597SStephen Boyd .enable_reg = 0x30bc, 2546c2526597SStephen Boyd .enable_mask = BIT(0), 2547c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2548c2526597SStephen Boyd .name = "camss_csi0_ahb_clk", 2549c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2550c2526597SStephen Boyd .num_parents = 1, 2551c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2552c2526597SStephen Boyd .ops = &clk_branch2_ops, 2553c2526597SStephen Boyd }, 2554c2526597SStephen Boyd }, 2555c2526597SStephen Boyd }; 2556c2526597SStephen Boyd 2557c2526597SStephen Boyd static struct clk_branch camss_csi0phy_clk = { 2558c2526597SStephen Boyd .halt_reg = 0x30c4, 2559c2526597SStephen Boyd .clkr = { 2560c2526597SStephen Boyd .enable_reg = 0x30c4, 2561c2526597SStephen Boyd .enable_mask = BIT(0), 2562c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2563c2526597SStephen Boyd .name = "camss_csi0phy_clk", 2564c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0_clk_src" }, 2565c2526597SStephen Boyd .num_parents = 1, 2566c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2567c2526597SStephen Boyd .ops = &clk_branch2_ops, 2568c2526597SStephen Boyd }, 2569c2526597SStephen Boyd }, 2570c2526597SStephen Boyd }; 2571c2526597SStephen Boyd 2572c2526597SStephen Boyd static struct clk_branch camss_csi0rdi_clk = { 2573c2526597SStephen Boyd .halt_reg = 0x30d4, 2574c2526597SStephen Boyd .clkr = { 2575c2526597SStephen Boyd .enable_reg = 0x30d4, 2576c2526597SStephen Boyd .enable_mask = BIT(0), 2577c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2578c2526597SStephen Boyd .name = "camss_csi0rdi_clk", 2579c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0_clk_src" }, 2580c2526597SStephen Boyd .num_parents = 1, 2581c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2582c2526597SStephen Boyd .ops = &clk_branch2_ops, 2583c2526597SStephen Boyd }, 2584c2526597SStephen Boyd }, 2585c2526597SStephen Boyd }; 2586c2526597SStephen Boyd 2587c2526597SStephen Boyd static struct clk_branch camss_csi0pix_clk = { 2588c2526597SStephen Boyd .halt_reg = 0x30e4, 2589c2526597SStephen Boyd .clkr = { 2590c2526597SStephen Boyd .enable_reg = 0x30e4, 2591c2526597SStephen Boyd .enable_mask = BIT(0), 2592c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2593c2526597SStephen Boyd .name = "camss_csi0pix_clk", 2594c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0_clk_src" }, 2595c2526597SStephen Boyd .num_parents = 1, 2596c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2597c2526597SStephen Boyd .ops = &clk_branch2_ops, 2598c2526597SStephen Boyd }, 2599c2526597SStephen Boyd }, 2600c2526597SStephen Boyd }; 2601c2526597SStephen Boyd 2602c2526597SStephen Boyd static struct clk_branch camss_csi1_clk = { 2603c2526597SStephen Boyd .halt_reg = 0x3124, 2604c2526597SStephen Boyd .clkr = { 2605c2526597SStephen Boyd .enable_reg = 0x3124, 2606c2526597SStephen Boyd .enable_mask = BIT(0), 2607c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2608c2526597SStephen Boyd .name = "camss_csi1_clk", 2609c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1_clk_src" }, 2610c2526597SStephen Boyd .num_parents = 1, 2611c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2612c2526597SStephen Boyd .ops = &clk_branch2_ops, 2613c2526597SStephen Boyd }, 2614c2526597SStephen Boyd }, 2615c2526597SStephen Boyd }; 2616c2526597SStephen Boyd 2617c2526597SStephen Boyd static struct clk_branch camss_csi1_ahb_clk = { 2618c2526597SStephen Boyd .halt_reg = 0x3128, 2619c2526597SStephen Boyd .clkr = { 2620c2526597SStephen Boyd .enable_reg = 0x3128, 2621c2526597SStephen Boyd .enable_mask = BIT(0), 2622c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2623c2526597SStephen Boyd .name = "camss_csi1_ahb_clk", 2624c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2625c2526597SStephen Boyd .num_parents = 1, 2626c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2627c2526597SStephen Boyd .ops = &clk_branch2_ops, 2628c2526597SStephen Boyd }, 2629c2526597SStephen Boyd }, 2630c2526597SStephen Boyd }; 2631c2526597SStephen Boyd 2632c2526597SStephen Boyd static struct clk_branch camss_csi1phy_clk = { 2633c2526597SStephen Boyd .halt_reg = 0x3134, 2634c2526597SStephen Boyd .clkr = { 2635c2526597SStephen Boyd .enable_reg = 0x3134, 2636c2526597SStephen Boyd .enable_mask = BIT(0), 2637c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2638c2526597SStephen Boyd .name = "camss_csi1phy_clk", 2639c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1_clk_src" }, 2640c2526597SStephen Boyd .num_parents = 1, 2641c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2642c2526597SStephen Boyd .ops = &clk_branch2_ops, 2643c2526597SStephen Boyd }, 2644c2526597SStephen Boyd }, 2645c2526597SStephen Boyd }; 2646c2526597SStephen Boyd 2647c2526597SStephen Boyd static struct clk_branch camss_csi1rdi_clk = { 2648c2526597SStephen Boyd .halt_reg = 0x3144, 2649c2526597SStephen Boyd .clkr = { 2650c2526597SStephen Boyd .enable_reg = 0x3144, 2651c2526597SStephen Boyd .enable_mask = BIT(0), 2652c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2653c2526597SStephen Boyd .name = "camss_csi1rdi_clk", 2654c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1_clk_src" }, 2655c2526597SStephen Boyd .num_parents = 1, 2656c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2657c2526597SStephen Boyd .ops = &clk_branch2_ops, 2658c2526597SStephen Boyd }, 2659c2526597SStephen Boyd }, 2660c2526597SStephen Boyd }; 2661c2526597SStephen Boyd 2662c2526597SStephen Boyd static struct clk_branch camss_csi1pix_clk = { 2663c2526597SStephen Boyd .halt_reg = 0x3154, 2664c2526597SStephen Boyd .clkr = { 2665c2526597SStephen Boyd .enable_reg = 0x3154, 2666c2526597SStephen Boyd .enable_mask = BIT(0), 2667c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2668c2526597SStephen Boyd .name = "camss_csi1pix_clk", 2669c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1_clk_src" }, 2670c2526597SStephen Boyd .num_parents = 1, 2671c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2672c2526597SStephen Boyd .ops = &clk_branch2_ops, 2673c2526597SStephen Boyd }, 2674c2526597SStephen Boyd }, 2675c2526597SStephen Boyd }; 2676c2526597SStephen Boyd 2677c2526597SStephen Boyd static struct clk_branch camss_csi2_clk = { 2678c2526597SStephen Boyd .halt_reg = 0x3184, 2679c2526597SStephen Boyd .clkr = { 2680c2526597SStephen Boyd .enable_reg = 0x3184, 2681c2526597SStephen Boyd .enable_mask = BIT(0), 2682c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2683c2526597SStephen Boyd .name = "camss_csi2_clk", 2684c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2_clk_src" }, 2685c2526597SStephen Boyd .num_parents = 1, 2686c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2687c2526597SStephen Boyd .ops = &clk_branch2_ops, 2688c2526597SStephen Boyd }, 2689c2526597SStephen Boyd }, 2690c2526597SStephen Boyd }; 2691c2526597SStephen Boyd 2692c2526597SStephen Boyd static struct clk_branch camss_csi2_ahb_clk = { 2693c2526597SStephen Boyd .halt_reg = 0x3188, 2694c2526597SStephen Boyd .clkr = { 2695c2526597SStephen Boyd .enable_reg = 0x3188, 2696c2526597SStephen Boyd .enable_mask = BIT(0), 2697c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2698c2526597SStephen Boyd .name = "camss_csi2_ahb_clk", 2699c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2700c2526597SStephen Boyd .num_parents = 1, 2701c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2702c2526597SStephen Boyd .ops = &clk_branch2_ops, 2703c2526597SStephen Boyd }, 2704c2526597SStephen Boyd }, 2705c2526597SStephen Boyd }; 2706c2526597SStephen Boyd 2707c2526597SStephen Boyd static struct clk_branch camss_csi2phy_clk = { 2708c2526597SStephen Boyd .halt_reg = 0x3194, 2709c2526597SStephen Boyd .clkr = { 2710c2526597SStephen Boyd .enable_reg = 0x3194, 2711c2526597SStephen Boyd .enable_mask = BIT(0), 2712c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2713c2526597SStephen Boyd .name = "camss_csi2phy_clk", 2714c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2_clk_src" }, 2715c2526597SStephen Boyd .num_parents = 1, 2716c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2717c2526597SStephen Boyd .ops = &clk_branch2_ops, 2718c2526597SStephen Boyd }, 2719c2526597SStephen Boyd }, 2720c2526597SStephen Boyd }; 2721c2526597SStephen Boyd 2722c2526597SStephen Boyd static struct clk_branch camss_csi2rdi_clk = { 2723c2526597SStephen Boyd .halt_reg = 0x31a4, 2724c2526597SStephen Boyd .clkr = { 2725c2526597SStephen Boyd .enable_reg = 0x31a4, 2726c2526597SStephen Boyd .enable_mask = BIT(0), 2727c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2728c2526597SStephen Boyd .name = "camss_csi2rdi_clk", 2729c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2_clk_src" }, 2730c2526597SStephen Boyd .num_parents = 1, 2731c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2732c2526597SStephen Boyd .ops = &clk_branch2_ops, 2733c2526597SStephen Boyd }, 2734c2526597SStephen Boyd }, 2735c2526597SStephen Boyd }; 2736c2526597SStephen Boyd 2737c2526597SStephen Boyd static struct clk_branch camss_csi2pix_clk = { 2738c2526597SStephen Boyd .halt_reg = 0x31b4, 2739c2526597SStephen Boyd .clkr = { 2740c2526597SStephen Boyd .enable_reg = 0x31b4, 2741c2526597SStephen Boyd .enable_mask = BIT(0), 2742c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2743c2526597SStephen Boyd .name = "camss_csi2pix_clk", 2744c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2_clk_src" }, 2745c2526597SStephen Boyd .num_parents = 1, 2746c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2747c2526597SStephen Boyd .ops = &clk_branch2_ops, 2748c2526597SStephen Boyd }, 2749c2526597SStephen Boyd }, 2750c2526597SStephen Boyd }; 2751c2526597SStephen Boyd 2752c2526597SStephen Boyd static struct clk_branch camss_csi3_clk = { 2753c2526597SStephen Boyd .halt_reg = 0x31e4, 2754c2526597SStephen Boyd .clkr = { 2755c2526597SStephen Boyd .enable_reg = 0x31e4, 2756c2526597SStephen Boyd .enable_mask = BIT(0), 2757c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2758c2526597SStephen Boyd .name = "camss_csi3_clk", 2759c2526597SStephen Boyd .parent_names = (const char *[]){ "csi3_clk_src" }, 2760c2526597SStephen Boyd .num_parents = 1, 2761c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2762c2526597SStephen Boyd .ops = &clk_branch2_ops, 2763c2526597SStephen Boyd }, 2764c2526597SStephen Boyd }, 2765c2526597SStephen Boyd }; 2766c2526597SStephen Boyd 2767c2526597SStephen Boyd static struct clk_branch camss_csi3_ahb_clk = { 2768c2526597SStephen Boyd .halt_reg = 0x31e8, 2769c2526597SStephen Boyd .clkr = { 2770c2526597SStephen Boyd .enable_reg = 0x31e8, 2771c2526597SStephen Boyd .enable_mask = BIT(0), 2772c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2773c2526597SStephen Boyd .name = "camss_csi3_ahb_clk", 2774c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2775c2526597SStephen Boyd .num_parents = 1, 2776c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2777c2526597SStephen Boyd .ops = &clk_branch2_ops, 2778c2526597SStephen Boyd }, 2779c2526597SStephen Boyd }, 2780c2526597SStephen Boyd }; 2781c2526597SStephen Boyd 2782c2526597SStephen Boyd static struct clk_branch camss_csi3phy_clk = { 2783c2526597SStephen Boyd .halt_reg = 0x31f4, 2784c2526597SStephen Boyd .clkr = { 2785c2526597SStephen Boyd .enable_reg = 0x31f4, 2786c2526597SStephen Boyd .enable_mask = BIT(0), 2787c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2788c2526597SStephen Boyd .name = "camss_csi3phy_clk", 2789c2526597SStephen Boyd .parent_names = (const char *[]){ "csi3_clk_src" }, 2790c2526597SStephen Boyd .num_parents = 1, 2791c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2792c2526597SStephen Boyd .ops = &clk_branch2_ops, 2793c2526597SStephen Boyd }, 2794c2526597SStephen Boyd }, 2795c2526597SStephen Boyd }; 2796c2526597SStephen Boyd 2797c2526597SStephen Boyd static struct clk_branch camss_csi3rdi_clk = { 2798c2526597SStephen Boyd .halt_reg = 0x3204, 2799c2526597SStephen Boyd .clkr = { 2800c2526597SStephen Boyd .enable_reg = 0x3204, 2801c2526597SStephen Boyd .enable_mask = BIT(0), 2802c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2803c2526597SStephen Boyd .name = "camss_csi3rdi_clk", 2804c2526597SStephen Boyd .parent_names = (const char *[]){ "csi3_clk_src" }, 2805c2526597SStephen Boyd .num_parents = 1, 2806c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2807c2526597SStephen Boyd .ops = &clk_branch2_ops, 2808c2526597SStephen Boyd }, 2809c2526597SStephen Boyd }, 2810c2526597SStephen Boyd }; 2811c2526597SStephen Boyd 2812c2526597SStephen Boyd static struct clk_branch camss_csi3pix_clk = { 2813c2526597SStephen Boyd .halt_reg = 0x3214, 2814c2526597SStephen Boyd .clkr = { 2815c2526597SStephen Boyd .enable_reg = 0x3214, 2816c2526597SStephen Boyd .enable_mask = BIT(0), 2817c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2818c2526597SStephen Boyd .name = "camss_csi3pix_clk", 2819c2526597SStephen Boyd .parent_names = (const char *[]){ "csi3_clk_src" }, 2820c2526597SStephen Boyd .num_parents = 1, 2821c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2822c2526597SStephen Boyd .ops = &clk_branch2_ops, 2823c2526597SStephen Boyd }, 2824c2526597SStephen Boyd }, 2825c2526597SStephen Boyd }; 2826c2526597SStephen Boyd 2827c2526597SStephen Boyd static struct clk_branch camss_ispif_ahb_clk = { 2828c2526597SStephen Boyd .halt_reg = 0x3224, 2829c2526597SStephen Boyd .clkr = { 2830c2526597SStephen Boyd .enable_reg = 0x3224, 2831c2526597SStephen Boyd .enable_mask = BIT(0), 2832c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2833c2526597SStephen Boyd .name = "camss_ispif_ahb_clk", 2834c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2835c2526597SStephen Boyd .num_parents = 1, 2836c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2837c2526597SStephen Boyd .ops = &clk_branch2_ops, 2838c2526597SStephen Boyd }, 2839c2526597SStephen Boyd }, 2840c2526597SStephen Boyd }; 2841c2526597SStephen Boyd 2842c2526597SStephen Boyd static struct clk_branch fd_core_clk = { 2843c2526597SStephen Boyd .halt_reg = 0x3b68, 2844c2526597SStephen Boyd .clkr = { 2845c2526597SStephen Boyd .enable_reg = 0x3b68, 2846c2526597SStephen Boyd .enable_mask = BIT(0), 2847c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2848c2526597SStephen Boyd .name = "fd_core_clk", 2849c2526597SStephen Boyd .parent_names = (const char *[]){ "fd_core_clk_src" }, 2850c2526597SStephen Boyd .num_parents = 1, 2851c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2852c2526597SStephen Boyd .ops = &clk_branch2_ops, 2853c2526597SStephen Boyd }, 2854c2526597SStephen Boyd }, 2855c2526597SStephen Boyd }; 2856c2526597SStephen Boyd 2857c2526597SStephen Boyd static struct clk_branch fd_core_uar_clk = { 2858c2526597SStephen Boyd .halt_reg = 0x3b6c, 2859c2526597SStephen Boyd .clkr = { 2860c2526597SStephen Boyd .enable_reg = 0x3b6c, 2861c2526597SStephen Boyd .enable_mask = BIT(0), 2862c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2863c2526597SStephen Boyd .name = "fd_core_uar_clk", 2864c2526597SStephen Boyd .parent_names = (const char *[]){ "fd_core_clk_src" }, 2865c2526597SStephen Boyd .num_parents = 1, 2866c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2867c2526597SStephen Boyd .ops = &clk_branch2_ops, 2868c2526597SStephen Boyd }, 2869c2526597SStephen Boyd }, 2870c2526597SStephen Boyd }; 2871c2526597SStephen Boyd 2872c2526597SStephen Boyd static struct clk_branch fd_ahb_clk = { 2873c2526597SStephen Boyd .halt_reg = 0x3ba74, 2874c2526597SStephen Boyd .clkr = { 2875c2526597SStephen Boyd .enable_reg = 0x3ba74, 2876c2526597SStephen Boyd .enable_mask = BIT(0), 2877c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2878c2526597SStephen Boyd .name = "fd_ahb_clk", 2879c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2880c2526597SStephen Boyd .num_parents = 1, 2881c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2882c2526597SStephen Boyd .ops = &clk_branch2_ops, 2883c2526597SStephen Boyd }, 2884c2526597SStephen Boyd }, 2885c2526597SStephen Boyd }; 2886c2526597SStephen Boyd 2887c2526597SStephen Boyd static struct clk_hw *mmcc_msm8996_hws[] = { 2888c2526597SStephen Boyd &gpll0_div.hw, 2889c2526597SStephen Boyd }; 2890c2526597SStephen Boyd 289163bb4fd6SRajendra Nayak static struct gdsc mmagic_bimc_gdsc = { 289263bb4fd6SRajendra Nayak .gdscr = 0x529c, 289363bb4fd6SRajendra Nayak .pd = { 289463bb4fd6SRajendra Nayak .name = "mmagic_bimc", 289563bb4fd6SRajendra Nayak }, 289663bb4fd6SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 289763bb4fd6SRajendra Nayak }; 289863bb4fd6SRajendra Nayak 28997e824d50SRajendra Nayak static struct gdsc mmagic_video_gdsc = { 29007e824d50SRajendra Nayak .gdscr = 0x119c, 29017e824d50SRajendra Nayak .gds_hw_ctrl = 0x120c, 29027e824d50SRajendra Nayak .pd = { 29037e824d50SRajendra Nayak .name = "mmagic_video", 29047e824d50SRajendra Nayak }, 29057e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29067e824d50SRajendra Nayak .flags = VOTABLE, 29077e824d50SRajendra Nayak }; 29087e824d50SRajendra Nayak 29097e824d50SRajendra Nayak static struct gdsc mmagic_mdss_gdsc = { 29107e824d50SRajendra Nayak .gdscr = 0x247c, 29117e824d50SRajendra Nayak .gds_hw_ctrl = 0x2480, 29127e824d50SRajendra Nayak .pd = { 29137e824d50SRajendra Nayak .name = "mmagic_mdss", 29147e824d50SRajendra Nayak }, 29157e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29167e824d50SRajendra Nayak .flags = VOTABLE, 29177e824d50SRajendra Nayak }; 29187e824d50SRajendra Nayak 29197e824d50SRajendra Nayak static struct gdsc mmagic_camss_gdsc = { 29207e824d50SRajendra Nayak .gdscr = 0x3c4c, 29217e824d50SRajendra Nayak .gds_hw_ctrl = 0x3c50, 29227e824d50SRajendra Nayak .pd = { 29237e824d50SRajendra Nayak .name = "mmagic_camss", 29247e824d50SRajendra Nayak }, 29257e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29267e824d50SRajendra Nayak .flags = VOTABLE, 29277e824d50SRajendra Nayak }; 29287e824d50SRajendra Nayak 29297e824d50SRajendra Nayak static struct gdsc venus_gdsc = { 29307e824d50SRajendra Nayak .gdscr = 0x1024, 29317e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 }, 29327e824d50SRajendra Nayak .cxc_count = 3, 29337e824d50SRajendra Nayak .pd = { 29347e824d50SRajendra Nayak .name = "venus", 29357e824d50SRajendra Nayak }, 29367e824d50SRajendra Nayak .parent = &mmagic_video_gdsc.pd, 29377e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29387e824d50SRajendra Nayak }; 29397e824d50SRajendra Nayak 29407e824d50SRajendra Nayak static struct gdsc venus_core0_gdsc = { 29417e824d50SRajendra Nayak .gdscr = 0x1040, 29427e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x1048 }, 29437e824d50SRajendra Nayak .cxc_count = 1, 29447e824d50SRajendra Nayak .pd = { 29457e824d50SRajendra Nayak .name = "venus_core0", 29467e824d50SRajendra Nayak }, 29477e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 294896893e10SSricharan R .flags = HW_CTRL, 29497e824d50SRajendra Nayak }; 29507e824d50SRajendra Nayak 29517e824d50SRajendra Nayak static struct gdsc venus_core1_gdsc = { 29527e824d50SRajendra Nayak .gdscr = 0x1044, 29537e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x104c }, 29547e824d50SRajendra Nayak .cxc_count = 1, 29557e824d50SRajendra Nayak .pd = { 29567e824d50SRajendra Nayak .name = "venus_core1", 29577e824d50SRajendra Nayak }, 29587e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 295996893e10SSricharan R .flags = HW_CTRL, 29607e824d50SRajendra Nayak }; 29617e824d50SRajendra Nayak 29627e824d50SRajendra Nayak static struct gdsc camss_gdsc = { 29637e824d50SRajendra Nayak .gdscr = 0x34a0, 29647e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36bc, 0x36c4 }, 29657e824d50SRajendra Nayak .cxc_count = 2, 29667e824d50SRajendra Nayak .pd = { 29677e824d50SRajendra Nayak .name = "camss", 29687e824d50SRajendra Nayak }, 29697e824d50SRajendra Nayak .parent = &mmagic_camss_gdsc.pd, 29707e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29717e824d50SRajendra Nayak }; 29727e824d50SRajendra Nayak 29737e824d50SRajendra Nayak static struct gdsc vfe0_gdsc = { 29747e824d50SRajendra Nayak .gdscr = 0x3664, 29757e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36a8 }, 29767e824d50SRajendra Nayak .cxc_count = 1, 29777e824d50SRajendra Nayak .pd = { 29787e824d50SRajendra Nayak .name = "vfe0", 29797e824d50SRajendra Nayak }, 29807e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 29817e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29827e824d50SRajendra Nayak }; 29837e824d50SRajendra Nayak 29847e824d50SRajendra Nayak static struct gdsc vfe1_gdsc = { 29857e824d50SRajendra Nayak .gdscr = 0x3674, 29867e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36ac }, 29877e824d50SRajendra Nayak .cxc_count = 1, 29887e824d50SRajendra Nayak .pd = { 29897e824d50SRajendra Nayak .name = "vfe0", 29907e824d50SRajendra Nayak }, 29917e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 29927e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29937e824d50SRajendra Nayak }; 29947e824d50SRajendra Nayak 29957e824d50SRajendra Nayak static struct gdsc jpeg_gdsc = { 29967e824d50SRajendra Nayak .gdscr = 0x35a4, 29977e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 }, 29987e824d50SRajendra Nayak .cxc_count = 4, 29997e824d50SRajendra Nayak .pd = { 30007e824d50SRajendra Nayak .name = "jpeg", 30017e824d50SRajendra Nayak }, 30027e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 30037e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30047e824d50SRajendra Nayak }; 30057e824d50SRajendra Nayak 30067e824d50SRajendra Nayak static struct gdsc cpp_gdsc = { 30077e824d50SRajendra Nayak .gdscr = 0x36d4, 30087e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36b0 }, 30097e824d50SRajendra Nayak .cxc_count = 1, 30107e824d50SRajendra Nayak .pd = { 30117e824d50SRajendra Nayak .name = "cpp", 30127e824d50SRajendra Nayak }, 30137e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 30147e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30157e824d50SRajendra Nayak }; 30167e824d50SRajendra Nayak 30177e824d50SRajendra Nayak static struct gdsc fd_gdsc = { 30187e824d50SRajendra Nayak .gdscr = 0x3b64, 30197e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x3b68, 0x3b6c }, 30207e824d50SRajendra Nayak .cxc_count = 2, 30217e824d50SRajendra Nayak .pd = { 30227e824d50SRajendra Nayak .name = "fd", 30237e824d50SRajendra Nayak }, 30247e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 30257e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30267e824d50SRajendra Nayak }; 30277e824d50SRajendra Nayak 30287e824d50SRajendra Nayak static struct gdsc mdss_gdsc = { 30297e824d50SRajendra Nayak .gdscr = 0x2304, 30307e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x2310, 0x231c }, 30317e824d50SRajendra Nayak .cxc_count = 2, 30327e824d50SRajendra Nayak .pd = { 30337e824d50SRajendra Nayak .name = "mdss", 30347e824d50SRajendra Nayak }, 30357e824d50SRajendra Nayak .parent = &mmagic_mdss_gdsc.pd, 30367e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30377e824d50SRajendra Nayak }; 30387e824d50SRajendra Nayak 30394154f619SRajendra Nayak static struct gdsc gpu_gdsc = { 30404154f619SRajendra Nayak .gdscr = 0x4034, 30414154f619SRajendra Nayak .gds_hw_ctrl = 0x4038, 30424154f619SRajendra Nayak .pd = { 30434154f619SRajendra Nayak .name = "gpu", 30444154f619SRajendra Nayak }, 30454154f619SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30464154f619SRajendra Nayak .flags = VOTABLE, 30474154f619SRajendra Nayak }; 30484154f619SRajendra Nayak 30494154f619SRajendra Nayak static struct gdsc gpu_gx_gdsc = { 30504154f619SRajendra Nayak .gdscr = 0x4024, 30514154f619SRajendra Nayak .clamp_io_ctrl = 0x4300, 30524154f619SRajendra Nayak .cxcs = (unsigned int []){ 0x4028 }, 30534154f619SRajendra Nayak .cxc_count = 1, 30544154f619SRajendra Nayak .pd = { 30554154f619SRajendra Nayak .name = "gpu_gx", 30564154f619SRajendra Nayak }, 30574154f619SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30584154f619SRajendra Nayak .flags = CLAMP_IO, 30594154f619SRajendra Nayak }; 30604154f619SRajendra Nayak 3061c2526597SStephen Boyd static struct clk_regmap *mmcc_msm8996_clocks[] = { 3062c2526597SStephen Boyd [MMPLL0_EARLY] = &mmpll0_early.clkr, 3063c2526597SStephen Boyd [MMPLL0_PLL] = &mmpll0.clkr, 3064c2526597SStephen Boyd [MMPLL1_EARLY] = &mmpll1_early.clkr, 3065c2526597SStephen Boyd [MMPLL1_PLL] = &mmpll1.clkr, 3066c2526597SStephen Boyd [MMPLL2_EARLY] = &mmpll2_early.clkr, 3067c2526597SStephen Boyd [MMPLL2_PLL] = &mmpll2.clkr, 3068c2526597SStephen Boyd [MMPLL3_EARLY] = &mmpll3_early.clkr, 3069c2526597SStephen Boyd [MMPLL3_PLL] = &mmpll3.clkr, 3070c2526597SStephen Boyd [MMPLL4_EARLY] = &mmpll4_early.clkr, 3071c2526597SStephen Boyd [MMPLL4_PLL] = &mmpll4.clkr, 3072c2526597SStephen Boyd [MMPLL5_EARLY] = &mmpll5_early.clkr, 3073c2526597SStephen Boyd [MMPLL5_PLL] = &mmpll5.clkr, 3074c2526597SStephen Boyd [MMPLL8_EARLY] = &mmpll8_early.clkr, 3075c2526597SStephen Boyd [MMPLL8_PLL] = &mmpll8.clkr, 3076c2526597SStephen Boyd [MMPLL9_EARLY] = &mmpll9_early.clkr, 3077c2526597SStephen Boyd [MMPLL9_PLL] = &mmpll9.clkr, 3078c2526597SStephen Boyd [AHB_CLK_SRC] = &ahb_clk_src.clkr, 3079c2526597SStephen Boyd [AXI_CLK_SRC] = &axi_clk_src.clkr, 3080c2526597SStephen Boyd [MAXI_CLK_SRC] = &maxi_clk_src.clkr, 3081c2526597SStephen Boyd [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 3082c2526597SStephen Boyd [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 3083c2526597SStephen Boyd [ISENSE_CLK_SRC] = &isense_clk_src.clkr, 3084c2526597SStephen Boyd [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 3085c2526597SStephen Boyd [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, 3086c2526597SStephen Boyd [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr, 3087c2526597SStephen Boyd [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr, 3088c2526597SStephen Boyd [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3089c2526597SStephen Boyd [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 3090c2526597SStephen Boyd [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3091c2526597SStephen Boyd [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 3092c2526597SStephen Boyd [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3093c2526597SStephen Boyd [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 3094c2526597SStephen Boyd [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3095c2526597SStephen Boyd [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 3096c2526597SStephen Boyd [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3097c2526597SStephen Boyd [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 3098c2526597SStephen Boyd [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3099c2526597SStephen Boyd [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3100c2526597SStephen Boyd [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3101c2526597SStephen Boyd [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3102c2526597SStephen Boyd [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 3103c2526597SStephen Boyd [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 3104c2526597SStephen Boyd [CCI_CLK_SRC] = &cci_clk_src.clkr, 3105c2526597SStephen Boyd [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3106c2526597SStephen Boyd [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3107c2526597SStephen Boyd [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 3108c2526597SStephen Boyd [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr, 3109c2526597SStephen Boyd [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr, 3110c2526597SStephen Boyd [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr, 3111c2526597SStephen Boyd [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3112c2526597SStephen Boyd [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, 3113c2526597SStephen Boyd [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr, 3114c2526597SStephen Boyd [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3115c2526597SStephen Boyd [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 3116c2526597SStephen Boyd [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3117c2526597SStephen Boyd [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3118c2526597SStephen Boyd [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3119c2526597SStephen Boyd [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 3120c2526597SStephen Boyd [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 3121c2526597SStephen Boyd [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr, 3122c2526597SStephen Boyd [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr, 3123c2526597SStephen Boyd [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr, 3124c2526597SStephen Boyd [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, 3125c2526597SStephen Boyd [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, 3126c2526597SStephen Boyd [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr, 3127c2526597SStephen Boyd [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr, 3128c2526597SStephen Boyd [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr, 3129c2526597SStephen Boyd [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr, 3130c2526597SStephen Boyd [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr, 3131c2526597SStephen Boyd [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr, 3132c2526597SStephen Boyd [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr, 3133c2526597SStephen Boyd [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr, 3134c2526597SStephen Boyd [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr, 3135c2526597SStephen Boyd [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr, 3136c2526597SStephen Boyd [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr, 3137c2526597SStephen Boyd [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr, 3138c2526597SStephen Boyd [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr, 3139c2526597SStephen Boyd [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr, 3140c2526597SStephen Boyd [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr, 3141c2526597SStephen Boyd [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr, 3142c2526597SStephen Boyd [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr, 3143c2526597SStephen Boyd [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr, 3144c2526597SStephen Boyd [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr, 3145c2526597SStephen Boyd [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr, 3146c2526597SStephen Boyd [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr, 3147c2526597SStephen Boyd [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr, 3148c2526597SStephen Boyd [GPU_AHB_CLK] = &gpu_ahb_clk.clkr, 3149c2526597SStephen Boyd [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr, 3150c2526597SStephen Boyd [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr, 3151c2526597SStephen Boyd [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr, 3152c2526597SStephen Boyd [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr, 3153c2526597SStephen Boyd [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr, 3154c2526597SStephen Boyd [VIDEO_CORE_CLK] = &video_core_clk.clkr, 3155c2526597SStephen Boyd [VIDEO_AXI_CLK] = &video_axi_clk.clkr, 3156c2526597SStephen Boyd [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr, 3157c2526597SStephen Boyd [VIDEO_AHB_CLK] = &video_ahb_clk.clkr, 3158c2526597SStephen Boyd [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr, 3159c2526597SStephen Boyd [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr, 3160c2526597SStephen Boyd [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 3161c2526597SStephen Boyd [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, 3162c2526597SStephen Boyd [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 3163c2526597SStephen Boyd [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 3164c2526597SStephen Boyd [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 3165c2526597SStephen Boyd [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 3166c2526597SStephen Boyd [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 3167c2526597SStephen Boyd [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 3168c2526597SStephen Boyd [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 3169c2526597SStephen Boyd [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 3170c2526597SStephen Boyd [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 3171c2526597SStephen Boyd [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 3172c2526597SStephen Boyd [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 3173c2526597SStephen Boyd [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 3174c2526597SStephen Boyd [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, 3175c2526597SStephen Boyd [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 3176c2526597SStephen Boyd [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 3177c2526597SStephen Boyd [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 3178c2526597SStephen Boyd [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 3179c2526597SStephen Boyd [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 3180c2526597SStephen Boyd [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 3181c2526597SStephen Boyd [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 3182c2526597SStephen Boyd [CAMSS_CCI_CLK] = &camss_cci_clk.clkr, 3183c2526597SStephen Boyd [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr, 3184c2526597SStephen Boyd [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr, 3185c2526597SStephen Boyd [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr, 3186c2526597SStephen Boyd [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr, 3187c2526597SStephen Boyd [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr, 3188c2526597SStephen Boyd [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr, 3189c2526597SStephen Boyd [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr, 3190c2526597SStephen Boyd [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr, 3191c2526597SStephen Boyd [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr, 3192c2526597SStephen Boyd [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr, 3193c2526597SStephen Boyd [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr, 3194c2526597SStephen Boyd [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr, 3195c2526597SStephen Boyd [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr, 3196c2526597SStephen Boyd [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr, 3197c2526597SStephen Boyd [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr, 3198c2526597SStephen Boyd [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr, 3199c2526597SStephen Boyd [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr, 3200c2526597SStephen Boyd [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr, 3201c2526597SStephen Boyd [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr, 3202c2526597SStephen Boyd [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr, 3203c2526597SStephen Boyd [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 3204c2526597SStephen Boyd [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 3205c2526597SStephen Boyd [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr, 3206c2526597SStephen Boyd [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr, 3207c2526597SStephen Boyd [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr, 3208c2526597SStephen Boyd [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr, 3209c2526597SStephen Boyd [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 3210c2526597SStephen Boyd [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 3211c2526597SStephen Boyd [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, 3212c2526597SStephen Boyd [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 3213c2526597SStephen Boyd [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 3214c2526597SStephen Boyd [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 3215c2526597SStephen Boyd [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 3216c2526597SStephen Boyd [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, 3217c2526597SStephen Boyd [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 3218c2526597SStephen Boyd [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 3219c2526597SStephen Boyd [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 3220c2526597SStephen Boyd [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 3221c2526597SStephen Boyd [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, 3222c2526597SStephen Boyd [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 3223c2526597SStephen Boyd [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 3224c2526597SStephen Boyd [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 3225c2526597SStephen Boyd [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 3226c2526597SStephen Boyd [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, 3227c2526597SStephen Boyd [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 3228c2526597SStephen Boyd [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 3229c2526597SStephen Boyd [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 3230c2526597SStephen Boyd [FD_CORE_CLK] = &fd_core_clk.clkr, 3231c2526597SStephen Boyd [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr, 3232c2526597SStephen Boyd [FD_AHB_CLK] = &fd_ahb_clk.clkr, 3233c2526597SStephen Boyd }; 3234c2526597SStephen Boyd 32357e824d50SRajendra Nayak static struct gdsc *mmcc_msm8996_gdscs[] = { 323663bb4fd6SRajendra Nayak [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc, 32377e824d50SRajendra Nayak [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc, 32387e824d50SRajendra Nayak [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc, 32397e824d50SRajendra Nayak [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc, 32407e824d50SRajendra Nayak [VENUS_GDSC] = &venus_gdsc, 32417e824d50SRajendra Nayak [VENUS_CORE0_GDSC] = &venus_core0_gdsc, 32427e824d50SRajendra Nayak [VENUS_CORE1_GDSC] = &venus_core1_gdsc, 32437e824d50SRajendra Nayak [CAMSS_GDSC] = &camss_gdsc, 32447e824d50SRajendra Nayak [VFE0_GDSC] = &vfe0_gdsc, 32457e824d50SRajendra Nayak [VFE1_GDSC] = &vfe1_gdsc, 32467e824d50SRajendra Nayak [JPEG_GDSC] = &jpeg_gdsc, 32477e824d50SRajendra Nayak [CPP_GDSC] = &cpp_gdsc, 32487e824d50SRajendra Nayak [FD_GDSC] = &fd_gdsc, 32497e824d50SRajendra Nayak [MDSS_GDSC] = &mdss_gdsc, 32504154f619SRajendra Nayak [GPU_GDSC] = &gpu_gdsc, 32514154f619SRajendra Nayak [GPU_GX_GDSC] = &gpu_gx_gdsc, 32527e824d50SRajendra Nayak }; 32537e824d50SRajendra Nayak 3254c2526597SStephen Boyd static const struct qcom_reset_map mmcc_msm8996_resets[] = { 3255c2526597SStephen Boyd [MMAGICAHB_BCR] = { 0x5020 }, 3256c2526597SStephen Boyd [MMAGIC_CFG_BCR] = { 0x5050 }, 3257c2526597SStephen Boyd [MISC_BCR] = { 0x5010 }, 3258c2526597SStephen Boyd [BTO_BCR] = { 0x5030 }, 3259c2526597SStephen Boyd [MMAGICAXI_BCR] = { 0x5060 }, 3260c2526597SStephen Boyd [MMAGICMAXI_BCR] = { 0x5070 }, 3261c2526597SStephen Boyd [DSA_BCR] = { 0x50a0 }, 3262c2526597SStephen Boyd [MMAGIC_CAMSS_BCR] = { 0x3c40 }, 3263c2526597SStephen Boyd [THROTTLE_CAMSS_BCR] = { 0x3c30 }, 3264c2526597SStephen Boyd [SMMU_VFE_BCR] = { 0x3c00 }, 3265c2526597SStephen Boyd [SMMU_CPP_BCR] = { 0x3c10 }, 3266c2526597SStephen Boyd [SMMU_JPEG_BCR] = { 0x3c20 }, 3267c2526597SStephen Boyd [MMAGIC_MDSS_BCR] = { 0x2470 }, 3268c2526597SStephen Boyd [THROTTLE_MDSS_BCR] = { 0x2460 }, 3269c2526597SStephen Boyd [SMMU_ROT_BCR] = { 0x2440 }, 3270c2526597SStephen Boyd [SMMU_MDP_BCR] = { 0x2450 }, 3271c2526597SStephen Boyd [MMAGIC_VIDEO_BCR] = { 0x1190 }, 3272c2526597SStephen Boyd [THROTTLE_VIDEO_BCR] = { 0x1180 }, 3273c2526597SStephen Boyd [SMMU_VIDEO_BCR] = { 0x1170 }, 3274c2526597SStephen Boyd [MMAGIC_BIMC_BCR] = { 0x5290 }, 3275c2526597SStephen Boyd [GPU_GX_BCR] = { 0x4020 }, 3276c2526597SStephen Boyd [GPU_BCR] = { 0x4030 }, 3277c2526597SStephen Boyd [GPU_AON_BCR] = { 0x4040 }, 3278c2526597SStephen Boyd [VMEM_BCR] = { 0x1200 }, 3279c2526597SStephen Boyd [MMSS_RBCPR_BCR] = { 0x4080 }, 3280c2526597SStephen Boyd [VIDEO_BCR] = { 0x1020 }, 3281c2526597SStephen Boyd [MDSS_BCR] = { 0x2300 }, 3282c2526597SStephen Boyd [CAMSS_TOP_BCR] = { 0x3480 }, 3283c2526597SStephen Boyd [CAMSS_AHB_BCR] = { 0x3488 }, 3284c2526597SStephen Boyd [CAMSS_MICRO_BCR] = { 0x3490 }, 3285c2526597SStephen Boyd [CAMSS_CCI_BCR] = { 0x3340 }, 3286c2526597SStephen Boyd [CAMSS_PHY0_BCR] = { 0x3020 }, 3287c2526597SStephen Boyd [CAMSS_PHY1_BCR] = { 0x3050 }, 3288c2526597SStephen Boyd [CAMSS_PHY2_BCR] = { 0x3080 }, 3289c2526597SStephen Boyd [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 }, 3290c2526597SStephen Boyd [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 }, 3291c2526597SStephen Boyd [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 }, 3292c2526597SStephen Boyd [CAMSS_JPEG_BCR] = { 0x35a0 }, 3293c2526597SStephen Boyd [CAMSS_VFE_BCR] = { 0x36a0 }, 3294c2526597SStephen Boyd [CAMSS_VFE0_BCR] = { 0x3660 }, 3295c2526597SStephen Boyd [CAMSS_VFE1_BCR] = { 0x3670 }, 3296c2526597SStephen Boyd [CAMSS_CSI_VFE0_BCR] = { 0x3700 }, 3297c2526597SStephen Boyd [CAMSS_CSI_VFE1_BCR] = { 0x3710 }, 3298c2526597SStephen Boyd [CAMSS_CPP_TOP_BCR] = { 0x36c0 }, 3299c2526597SStephen Boyd [CAMSS_CPP_BCR] = { 0x36d0 }, 3300c2526597SStephen Boyd [CAMSS_CSI0_BCR] = { 0x30b0 }, 3301c2526597SStephen Boyd [CAMSS_CSI0RDI_BCR] = { 0x30d0 }, 3302c2526597SStephen Boyd [CAMSS_CSI0PIX_BCR] = { 0x30e0 }, 3303c2526597SStephen Boyd [CAMSS_CSI1_BCR] = { 0x3120 }, 3304c2526597SStephen Boyd [CAMSS_CSI1RDI_BCR] = { 0x3140 }, 3305c2526597SStephen Boyd [CAMSS_CSI1PIX_BCR] = { 0x3150 }, 3306c2526597SStephen Boyd [CAMSS_CSI2_BCR] = { 0x3180 }, 3307c2526597SStephen Boyd [CAMSS_CSI2RDI_BCR] = { 0x31a0 }, 3308c2526597SStephen Boyd [CAMSS_CSI2PIX_BCR] = { 0x31b0 }, 3309c2526597SStephen Boyd [CAMSS_CSI3_BCR] = { 0x31e0 }, 3310c2526597SStephen Boyd [CAMSS_CSI3RDI_BCR] = { 0x3200 }, 3311c2526597SStephen Boyd [CAMSS_CSI3PIX_BCR] = { 0x3210 }, 3312c2526597SStephen Boyd [CAMSS_ISPIF_BCR] = { 0x3220 }, 3313c2526597SStephen Boyd [FD_BCR] = { 0x3b60 }, 3314c2526597SStephen Boyd [MMSS_SPDM_RM_BCR] = { 0x300 }, 3315c2526597SStephen Boyd }; 3316c2526597SStephen Boyd 3317c2526597SStephen Boyd static const struct regmap_config mmcc_msm8996_regmap_config = { 3318c2526597SStephen Boyd .reg_bits = 32, 3319c2526597SStephen Boyd .reg_stride = 4, 3320c2526597SStephen Boyd .val_bits = 32, 3321c2526597SStephen Boyd .max_register = 0xb008, 3322c2526597SStephen Boyd .fast_io = true, 3323c2526597SStephen Boyd }; 3324c2526597SStephen Boyd 3325c2526597SStephen Boyd static const struct qcom_cc_desc mmcc_msm8996_desc = { 3326c2526597SStephen Boyd .config = &mmcc_msm8996_regmap_config, 3327c2526597SStephen Boyd .clks = mmcc_msm8996_clocks, 3328c2526597SStephen Boyd .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks), 3329c2526597SStephen Boyd .resets = mmcc_msm8996_resets, 3330c2526597SStephen Boyd .num_resets = ARRAY_SIZE(mmcc_msm8996_resets), 33317e824d50SRajendra Nayak .gdscs = mmcc_msm8996_gdscs, 33327e824d50SRajendra Nayak .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs), 3333c2526597SStephen Boyd }; 3334c2526597SStephen Boyd 3335c2526597SStephen Boyd static const struct of_device_id mmcc_msm8996_match_table[] = { 3336c2526597SStephen Boyd { .compatible = "qcom,mmcc-msm8996" }, 3337c2526597SStephen Boyd { } 3338c2526597SStephen Boyd }; 3339c2526597SStephen Boyd MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table); 3340c2526597SStephen Boyd 3341c2526597SStephen Boyd static int mmcc_msm8996_probe(struct platform_device *pdev) 3342c2526597SStephen Boyd { 3343c2526597SStephen Boyd struct device *dev = &pdev->dev; 3344120c1552SStephen Boyd int i, ret; 3345c2526597SStephen Boyd struct regmap *regmap; 3346c2526597SStephen Boyd 3347c2526597SStephen Boyd regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc); 3348c2526597SStephen Boyd if (IS_ERR(regmap)) 3349c2526597SStephen Boyd return PTR_ERR(regmap); 3350c2526597SStephen Boyd 3351c2526597SStephen Boyd /* Disable the AHB DCD */ 3352c2526597SStephen Boyd regmap_update_bits(regmap, 0x50d8, BIT(31), 0); 3353c2526597SStephen Boyd /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */ 3354c2526597SStephen Boyd regmap_update_bits(regmap, 0x5054, BIT(15), 0); 3355c2526597SStephen Boyd 3356c2526597SStephen Boyd for (i = 0; i < ARRAY_SIZE(mmcc_msm8996_hws); i++) { 3357120c1552SStephen Boyd ret = devm_clk_hw_register(dev, mmcc_msm8996_hws[i]); 3358120c1552SStephen Boyd if (ret) 3359120c1552SStephen Boyd return ret; 3360c2526597SStephen Boyd } 3361c2526597SStephen Boyd 3362c2526597SStephen Boyd return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap); 3363c2526597SStephen Boyd } 3364c2526597SStephen Boyd 3365c2526597SStephen Boyd static struct platform_driver mmcc_msm8996_driver = { 3366c2526597SStephen Boyd .probe = mmcc_msm8996_probe, 3367c2526597SStephen Boyd .driver = { 3368c2526597SStephen Boyd .name = "mmcc-msm8996", 3369c2526597SStephen Boyd .of_match_table = mmcc_msm8996_match_table, 3370c2526597SStephen Boyd }, 3371c2526597SStephen Boyd }; 3372c2526597SStephen Boyd module_platform_driver(mmcc_msm8996_driver); 3373c2526597SStephen Boyd 3374c2526597SStephen Boyd MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver"); 3375c2526597SStephen Boyd MODULE_LICENSE("GPL v2"); 3376c2526597SStephen Boyd MODULE_ALIAS("platform:mmcc-msm8996"); 3377