19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2c2526597SStephen Boyd /*x 3c2526597SStephen Boyd * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4c2526597SStephen Boyd */ 5c2526597SStephen Boyd 6c2526597SStephen Boyd #include <linux/kernel.h> 7c2526597SStephen Boyd #include <linux/bitops.h> 8c2526597SStephen Boyd #include <linux/err.h> 9c2526597SStephen Boyd #include <linux/platform_device.h> 10c2526597SStephen Boyd #include <linux/module.h> 11c2526597SStephen Boyd #include <linux/of.h> 12c2526597SStephen Boyd #include <linux/of_device.h> 13c2526597SStephen Boyd #include <linux/clk-provider.h> 14c2526597SStephen Boyd #include <linux/regmap.h> 15c2526597SStephen Boyd #include <linux/reset-controller.h> 16c2526597SStephen Boyd #include <linux/clk.h> 17c2526597SStephen Boyd 18c2526597SStephen Boyd #include <dt-bindings/clock/qcom,mmcc-msm8996.h> 19c2526597SStephen Boyd 20c2526597SStephen Boyd #include "common.h" 21c2526597SStephen Boyd #include "clk-regmap.h" 22c2526597SStephen Boyd #include "clk-regmap-divider.h" 23c2526597SStephen Boyd #include "clk-alpha-pll.h" 24c2526597SStephen Boyd #include "clk-rcg.h" 25c2526597SStephen Boyd #include "clk-branch.h" 26c2526597SStephen Boyd #include "reset.h" 277e824d50SRajendra Nayak #include "gdsc.h" 28c2526597SStephen Boyd 29c2526597SStephen Boyd enum { 30c2526597SStephen Boyd P_XO, 31c2526597SStephen Boyd P_MMPLL0, 32c2526597SStephen Boyd P_GPLL0, 33c2526597SStephen Boyd P_GPLL0_DIV, 34c2526597SStephen Boyd P_MMPLL1, 35c2526597SStephen Boyd P_MMPLL9, 36c2526597SStephen Boyd P_MMPLL2, 37c2526597SStephen Boyd P_MMPLL8, 38c2526597SStephen Boyd P_MMPLL3, 39c2526597SStephen Boyd P_DSI0PLL, 40c2526597SStephen Boyd P_DSI1PLL, 41c2526597SStephen Boyd P_MMPLL5, 42c2526597SStephen Boyd P_HDMIPLL, 43c2526597SStephen Boyd P_DSI0PLL_BYTE, 44c2526597SStephen Boyd P_DSI1PLL_BYTE, 45c2526597SStephen Boyd P_MMPLL4, 46c2526597SStephen Boyd }; 47c2526597SStephen Boyd 48c2526597SStephen Boyd static const struct parent_map mmss_xo_hdmi_map[] = { 49c2526597SStephen Boyd { P_XO, 0 }, 50c2526597SStephen Boyd { P_HDMIPLL, 1 } 51c2526597SStephen Boyd }; 52c2526597SStephen Boyd 53c2526597SStephen Boyd static const char * const mmss_xo_hdmi[] = { 54c2526597SStephen Boyd "xo", 55c2526597SStephen Boyd "hdmipll" 56c2526597SStephen Boyd }; 57c2526597SStephen Boyd 58c2526597SStephen Boyd static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { 59c2526597SStephen Boyd { P_XO, 0 }, 60c2526597SStephen Boyd { P_DSI0PLL, 1 }, 61c2526597SStephen Boyd { P_DSI1PLL, 2 } 62c2526597SStephen Boyd }; 63c2526597SStephen Boyd 64c2526597SStephen Boyd static const char * const mmss_xo_dsi0pll_dsi1pll[] = { 65c2526597SStephen Boyd "xo", 66c2526597SStephen Boyd "dsi0pll", 67c2526597SStephen Boyd "dsi1pll" 68c2526597SStephen Boyd }; 69c2526597SStephen Boyd 70c2526597SStephen Boyd static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { 71c2526597SStephen Boyd { P_XO, 0 }, 72c2526597SStephen Boyd { P_GPLL0, 5 }, 73c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 74c2526597SStephen Boyd }; 75c2526597SStephen Boyd 76c2526597SStephen Boyd static const char * const mmss_xo_gpll0_gpll0_div[] = { 77c2526597SStephen Boyd "xo", 78c2526597SStephen Boyd "gpll0", 79c2526597SStephen Boyd "gpll0_div" 80c2526597SStephen Boyd }; 81c2526597SStephen Boyd 82c2526597SStephen Boyd static const struct parent_map mmss_xo_dsibyte_map[] = { 83c2526597SStephen Boyd { P_XO, 0 }, 84c2526597SStephen Boyd { P_DSI0PLL_BYTE, 1 }, 85c2526597SStephen Boyd { P_DSI1PLL_BYTE, 2 } 86c2526597SStephen Boyd }; 87c2526597SStephen Boyd 88c2526597SStephen Boyd static const char * const mmss_xo_dsibyte[] = { 89c2526597SStephen Boyd "xo", 90c2526597SStephen Boyd "dsi0pllbyte", 91c2526597SStephen Boyd "dsi1pllbyte" 92c2526597SStephen Boyd }; 93c2526597SStephen Boyd 94c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { 95c2526597SStephen Boyd { P_XO, 0 }, 96c2526597SStephen Boyd { P_MMPLL0, 1 }, 97c2526597SStephen Boyd { P_GPLL0, 5 }, 98c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 99c2526597SStephen Boyd }; 100c2526597SStephen Boyd 101c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = { 102c2526597SStephen Boyd "xo", 103c2526597SStephen Boyd "mmpll0", 104c2526597SStephen Boyd "gpll0", 105c2526597SStephen Boyd "gpll0_div" 106c2526597SStephen Boyd }; 107c2526597SStephen Boyd 108c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { 109c2526597SStephen Boyd { P_XO, 0 }, 110c2526597SStephen Boyd { P_MMPLL0, 1 }, 111c2526597SStephen Boyd { P_MMPLL1, 2 }, 112c2526597SStephen Boyd { P_GPLL0, 5 }, 113c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 114c2526597SStephen Boyd }; 115c2526597SStephen Boyd 116c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { 117c2526597SStephen Boyd "xo", 118c2526597SStephen Boyd "mmpll0", 119c2526597SStephen Boyd "mmpll1", 120c2526597SStephen Boyd "gpll0", 121c2526597SStephen Boyd "gpll0_div" 122c2526597SStephen Boyd }; 123c2526597SStephen Boyd 124c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { 125c2526597SStephen Boyd { P_XO, 0 }, 126c2526597SStephen Boyd { P_MMPLL0, 1 }, 127c2526597SStephen Boyd { P_MMPLL3, 3 }, 128c2526597SStephen Boyd { P_GPLL0, 5 }, 129c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 130c2526597SStephen Boyd }; 131c2526597SStephen Boyd 132c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { 133c2526597SStephen Boyd "xo", 134c2526597SStephen Boyd "mmpll0", 135c2526597SStephen Boyd "mmpll3", 136c2526597SStephen Boyd "gpll0", 137c2526597SStephen Boyd "gpll0_div" 138c2526597SStephen Boyd }; 139c2526597SStephen Boyd 140c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { 141c2526597SStephen Boyd { P_XO, 0 }, 142c2526597SStephen Boyd { P_MMPLL0, 1 }, 143c2526597SStephen Boyd { P_MMPLL5, 2 }, 144c2526597SStephen Boyd { P_GPLL0, 5 }, 145c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 146c2526597SStephen Boyd }; 147c2526597SStephen Boyd 148c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { 149c2526597SStephen Boyd "xo", 150c2526597SStephen Boyd "mmpll0", 151c2526597SStephen Boyd "mmpll5", 152c2526597SStephen Boyd "gpll0", 153c2526597SStephen Boyd "gpll0_div" 154c2526597SStephen Boyd }; 155c2526597SStephen Boyd 156c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { 157c2526597SStephen Boyd { P_XO, 0 }, 158c2526597SStephen Boyd { P_MMPLL0, 1 }, 159c2526597SStephen Boyd { P_MMPLL4, 3 }, 160c2526597SStephen Boyd { P_GPLL0, 5 }, 161c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 162c2526597SStephen Boyd }; 163c2526597SStephen Boyd 164c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { 165c2526597SStephen Boyd "xo", 166c2526597SStephen Boyd "mmpll0", 167c2526597SStephen Boyd "mmpll4", 168c2526597SStephen Boyd "gpll0", 169c2526597SStephen Boyd "gpll0_div" 170c2526597SStephen Boyd }; 171c2526597SStephen Boyd 172c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { 173c2526597SStephen Boyd { P_XO, 0 }, 174c2526597SStephen Boyd { P_MMPLL0, 1 }, 175c2526597SStephen Boyd { P_MMPLL9, 2 }, 176c2526597SStephen Boyd { P_MMPLL2, 3 }, 177c2526597SStephen Boyd { P_MMPLL8, 4 }, 178c2526597SStephen Boyd { P_GPLL0, 5 } 179c2526597SStephen Boyd }; 180c2526597SStephen Boyd 181c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { 182c2526597SStephen Boyd "xo", 183c2526597SStephen Boyd "mmpll0", 184c2526597SStephen Boyd "mmpll9", 185c2526597SStephen Boyd "mmpll2", 186c2526597SStephen Boyd "mmpll8", 187c2526597SStephen Boyd "gpll0" 188c2526597SStephen Boyd }; 189c2526597SStephen Boyd 190c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { 191c2526597SStephen Boyd { P_XO, 0 }, 192c2526597SStephen Boyd { P_MMPLL0, 1 }, 193c2526597SStephen Boyd { P_MMPLL9, 2 }, 194c2526597SStephen Boyd { P_MMPLL2, 3 }, 195c2526597SStephen Boyd { P_MMPLL8, 4 }, 196c2526597SStephen Boyd { P_GPLL0, 5 }, 197c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 198c2526597SStephen Boyd }; 199c2526597SStephen Boyd 200c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { 201c2526597SStephen Boyd "xo", 202c2526597SStephen Boyd "mmpll0", 203c2526597SStephen Boyd "mmpll9", 204c2526597SStephen Boyd "mmpll2", 205c2526597SStephen Boyd "mmpll8", 206c2526597SStephen Boyd "gpll0", 207c2526597SStephen Boyd "gpll0_div" 208c2526597SStephen Boyd }; 209c2526597SStephen Boyd 210c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { 211c2526597SStephen Boyd { P_XO, 0 }, 212c2526597SStephen Boyd { P_MMPLL0, 1 }, 213c2526597SStephen Boyd { P_MMPLL1, 2 }, 214c2526597SStephen Boyd { P_MMPLL4, 3 }, 215c2526597SStephen Boyd { P_MMPLL3, 4 }, 216c2526597SStephen Boyd { P_GPLL0, 5 }, 217c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 218c2526597SStephen Boyd }; 219c2526597SStephen Boyd 220c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { 221c2526597SStephen Boyd "xo", 222c2526597SStephen Boyd "mmpll0", 223c2526597SStephen Boyd "mmpll1", 224c2526597SStephen Boyd "mmpll4", 225c2526597SStephen Boyd "mmpll3", 226c2526597SStephen Boyd "gpll0", 227c2526597SStephen Boyd "gpll0_div" 228c2526597SStephen Boyd }; 229c2526597SStephen Boyd 230c2526597SStephen Boyd static struct clk_fixed_factor gpll0_div = { 231c2526597SStephen Boyd .mult = 1, 232c2526597SStephen Boyd .div = 2, 233c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 234c2526597SStephen Boyd .name = "gpll0_div", 235c2526597SStephen Boyd .parent_names = (const char *[]){ "gpll0" }, 236c2526597SStephen Boyd .num_parents = 1, 237c2526597SStephen Boyd .ops = &clk_fixed_factor_ops, 238c2526597SStephen Boyd }, 239c2526597SStephen Boyd }; 240c2526597SStephen Boyd 241c2526597SStephen Boyd static struct pll_vco mmpll_p_vco[] = { 242c2526597SStephen Boyd { 250000000, 500000000, 3 }, 243c2526597SStephen Boyd { 500000000, 1000000000, 2 }, 244c2526597SStephen Boyd { 1000000000, 1500000000, 1 }, 245c2526597SStephen Boyd { 1500000000, 2000000000, 0 }, 246c2526597SStephen Boyd }; 247c2526597SStephen Boyd 248c2526597SStephen Boyd static struct pll_vco mmpll_gfx_vco[] = { 249c2526597SStephen Boyd { 400000000, 1000000000, 2 }, 250c2526597SStephen Boyd { 1000000000, 1500000000, 1 }, 251c2526597SStephen Boyd { 1500000000, 2000000000, 0 }, 252c2526597SStephen Boyd }; 253c2526597SStephen Boyd 254c2526597SStephen Boyd static struct pll_vco mmpll_t_vco[] = { 255c2526597SStephen Boyd { 500000000, 1500000000, 0 }, 256c2526597SStephen Boyd }; 257c2526597SStephen Boyd 258c2526597SStephen Boyd static struct clk_alpha_pll mmpll0_early = { 259c2526597SStephen Boyd .offset = 0x0, 26028d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 261c2526597SStephen Boyd .vco_table = mmpll_p_vco, 262c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 263c2526597SStephen Boyd .clkr = { 264c2526597SStephen Boyd .enable_reg = 0x100, 265c2526597SStephen Boyd .enable_mask = BIT(0), 266c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 267c2526597SStephen Boyd .name = "mmpll0_early", 268c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 269c2526597SStephen Boyd .num_parents = 1, 270c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 271c2526597SStephen Boyd }, 272c2526597SStephen Boyd }, 273c2526597SStephen Boyd }; 274c2526597SStephen Boyd 275c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll0 = { 276c2526597SStephen Boyd .offset = 0x0, 27728d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 278c2526597SStephen Boyd .width = 4, 279c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 280c2526597SStephen Boyd .name = "mmpll0", 281c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll0_early" }, 282c2526597SStephen Boyd .num_parents = 1, 283c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 284c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 285c2526597SStephen Boyd }, 286c2526597SStephen Boyd }; 287c2526597SStephen Boyd 288c2526597SStephen Boyd static struct clk_alpha_pll mmpll1_early = { 289c2526597SStephen Boyd .offset = 0x30, 29028d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 291c2526597SStephen Boyd .vco_table = mmpll_p_vco, 292c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 293c2526597SStephen Boyd .clkr = { 294c2526597SStephen Boyd .enable_reg = 0x100, 295c2526597SStephen Boyd .enable_mask = BIT(1), 296c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 297c2526597SStephen Boyd .name = "mmpll1_early", 298c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 299c2526597SStephen Boyd .num_parents = 1, 300c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 301c2526597SStephen Boyd } 302c2526597SStephen Boyd }, 303c2526597SStephen Boyd }; 304c2526597SStephen Boyd 305c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll1 = { 306c2526597SStephen Boyd .offset = 0x30, 30728d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 308c2526597SStephen Boyd .width = 4, 309c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 310c2526597SStephen Boyd .name = "mmpll1", 311c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll1_early" }, 312c2526597SStephen Boyd .num_parents = 1, 313c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 314c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 315c2526597SStephen Boyd }, 316c2526597SStephen Boyd }; 317c2526597SStephen Boyd 318c2526597SStephen Boyd static struct clk_alpha_pll mmpll2_early = { 319c2526597SStephen Boyd .offset = 0x4100, 32028d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 321c2526597SStephen Boyd .vco_table = mmpll_gfx_vco, 322c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 323c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 324c2526597SStephen Boyd .name = "mmpll2_early", 325c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 326c2526597SStephen Boyd .num_parents = 1, 327c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 328c2526597SStephen Boyd }, 329c2526597SStephen Boyd }; 330c2526597SStephen Boyd 331c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll2 = { 332c2526597SStephen Boyd .offset = 0x4100, 33328d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 334c2526597SStephen Boyd .width = 4, 335c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 336c2526597SStephen Boyd .name = "mmpll2", 337c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll2_early" }, 338c2526597SStephen Boyd .num_parents = 1, 339c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 340c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 341c2526597SStephen Boyd }, 342c2526597SStephen Boyd }; 343c2526597SStephen Boyd 344c2526597SStephen Boyd static struct clk_alpha_pll mmpll3_early = { 345c2526597SStephen Boyd .offset = 0x60, 34628d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 347c2526597SStephen Boyd .vco_table = mmpll_p_vco, 348c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 349c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 350c2526597SStephen Boyd .name = "mmpll3_early", 351c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 352c2526597SStephen Boyd .num_parents = 1, 353c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 354c2526597SStephen Boyd }, 355c2526597SStephen Boyd }; 356c2526597SStephen Boyd 357c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll3 = { 358c2526597SStephen Boyd .offset = 0x60, 35928d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 360c2526597SStephen Boyd .width = 4, 361c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 362c2526597SStephen Boyd .name = "mmpll3", 363c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll3_early" }, 364c2526597SStephen Boyd .num_parents = 1, 365c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 366c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 367c2526597SStephen Boyd }, 368c2526597SStephen Boyd }; 369c2526597SStephen Boyd 370c2526597SStephen Boyd static struct clk_alpha_pll mmpll4_early = { 371c2526597SStephen Boyd .offset = 0x90, 37228d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 373c2526597SStephen Boyd .vco_table = mmpll_t_vco, 374c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_t_vco), 375c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 376c2526597SStephen Boyd .name = "mmpll4_early", 377c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 378c2526597SStephen Boyd .num_parents = 1, 379c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 380c2526597SStephen Boyd }, 381c2526597SStephen Boyd }; 382c2526597SStephen Boyd 383c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll4 = { 384c2526597SStephen Boyd .offset = 0x90, 38528d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 386c2526597SStephen Boyd .width = 2, 387c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 388c2526597SStephen Boyd .name = "mmpll4", 389c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll4_early" }, 390c2526597SStephen Boyd .num_parents = 1, 391c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 392c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 393c2526597SStephen Boyd }, 394c2526597SStephen Boyd }; 395c2526597SStephen Boyd 396c2526597SStephen Boyd static struct clk_alpha_pll mmpll5_early = { 397c2526597SStephen Boyd .offset = 0xc0, 39828d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 399c2526597SStephen Boyd .vco_table = mmpll_p_vco, 400c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 401c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 402c2526597SStephen Boyd .name = "mmpll5_early", 403c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 404c2526597SStephen Boyd .num_parents = 1, 405c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 406c2526597SStephen Boyd }, 407c2526597SStephen Boyd }; 408c2526597SStephen Boyd 409c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll5 = { 410c2526597SStephen Boyd .offset = 0xc0, 41128d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 412c2526597SStephen Boyd .width = 4, 413c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 414c2526597SStephen Boyd .name = "mmpll5", 415c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll5_early" }, 416c2526597SStephen Boyd .num_parents = 1, 417c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 418c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 419c2526597SStephen Boyd }, 420c2526597SStephen Boyd }; 421c2526597SStephen Boyd 422c2526597SStephen Boyd static struct clk_alpha_pll mmpll8_early = { 423c2526597SStephen Boyd .offset = 0x4130, 42428d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 425c2526597SStephen Boyd .vco_table = mmpll_gfx_vco, 426c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 427c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 428c2526597SStephen Boyd .name = "mmpll8_early", 429c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 430c2526597SStephen Boyd .num_parents = 1, 431c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 432c2526597SStephen Boyd }, 433c2526597SStephen Boyd }; 434c2526597SStephen Boyd 435c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll8 = { 436c2526597SStephen Boyd .offset = 0x4130, 43728d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 438c2526597SStephen Boyd .width = 4, 439c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 440c2526597SStephen Boyd .name = "mmpll8", 441c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll8_early" }, 442c2526597SStephen Boyd .num_parents = 1, 443c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 444c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 445c2526597SStephen Boyd }, 446c2526597SStephen Boyd }; 447c2526597SStephen Boyd 448c2526597SStephen Boyd static struct clk_alpha_pll mmpll9_early = { 449c2526597SStephen Boyd .offset = 0x4200, 45028d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 451c2526597SStephen Boyd .vco_table = mmpll_t_vco, 452c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_t_vco), 453c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 454c2526597SStephen Boyd .name = "mmpll9_early", 455c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 456c2526597SStephen Boyd .num_parents = 1, 457c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 458c2526597SStephen Boyd }, 459c2526597SStephen Boyd }; 460c2526597SStephen Boyd 461c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll9 = { 462c2526597SStephen Boyd .offset = 0x4200, 46328d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 464c2526597SStephen Boyd .width = 2, 465c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 466c2526597SStephen Boyd .name = "mmpll9", 467c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll9_early" }, 468c2526597SStephen Boyd .num_parents = 1, 469c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 470c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 471c2526597SStephen Boyd }, 472c2526597SStephen Boyd }; 473c2526597SStephen Boyd 474c2526597SStephen Boyd static const struct freq_tbl ftbl_ahb_clk_src[] = { 475c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 476c2526597SStephen Boyd F(40000000, P_GPLL0_DIV, 7.5, 0, 0), 477c2526597SStephen Boyd F(80000000, P_MMPLL0, 10, 0, 0), 478c2526597SStephen Boyd { } 479c2526597SStephen Boyd }; 480c2526597SStephen Boyd 481c2526597SStephen Boyd static struct clk_rcg2 ahb_clk_src = { 482c2526597SStephen Boyd .cmd_rcgr = 0x5000, 483c2526597SStephen Boyd .hid_width = 5, 484c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 485c2526597SStephen Boyd .freq_tbl = ftbl_ahb_clk_src, 486c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 487c2526597SStephen Boyd .name = "ahb_clk_src", 488c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 489c2526597SStephen Boyd .num_parents = 4, 490c2526597SStephen Boyd .ops = &clk_rcg2_ops, 491c2526597SStephen Boyd }, 492c2526597SStephen Boyd }; 493c2526597SStephen Boyd 494c2526597SStephen Boyd static const struct freq_tbl ftbl_axi_clk_src[] = { 495c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 496c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 497c2526597SStephen Boyd F(100000000, P_GPLL0, 6, 0, 0), 498c2526597SStephen Boyd F(171430000, P_GPLL0, 3.5, 0, 0), 499c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 500c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 501c2526597SStephen Boyd F(400000000, P_MMPLL0, 2, 0, 0), 502c2526597SStephen Boyd { } 503c2526597SStephen Boyd }; 504c2526597SStephen Boyd 505c2526597SStephen Boyd static struct clk_rcg2 axi_clk_src = { 506c2526597SStephen Boyd .cmd_rcgr = 0x5040, 507c2526597SStephen Boyd .hid_width = 5, 508c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 509c2526597SStephen Boyd .freq_tbl = ftbl_axi_clk_src, 510c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 511c2526597SStephen Boyd .name = "axi_clk_src", 512c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 513c2526597SStephen Boyd .num_parents = 5, 514c2526597SStephen Boyd .ops = &clk_rcg2_ops, 515c2526597SStephen Boyd }, 516c2526597SStephen Boyd }; 517c2526597SStephen Boyd 518c2526597SStephen Boyd static struct clk_rcg2 maxi_clk_src = { 519c2526597SStephen Boyd .cmd_rcgr = 0x5090, 520c2526597SStephen Boyd .hid_width = 5, 521c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 522c2526597SStephen Boyd .freq_tbl = ftbl_axi_clk_src, 523c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 524c2526597SStephen Boyd .name = "maxi_clk_src", 525c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 526c2526597SStephen Boyd .num_parents = 5, 527c2526597SStephen Boyd .ops = &clk_rcg2_ops, 528c2526597SStephen Boyd }, 529c2526597SStephen Boyd }; 530c2526597SStephen Boyd 531c2526597SStephen Boyd static struct clk_rcg2 gfx3d_clk_src = { 532c2526597SStephen Boyd .cmd_rcgr = 0x4000, 533c2526597SStephen Boyd .hid_width = 5, 534c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map, 535c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 536c2526597SStephen Boyd .name = "gfx3d_clk_src", 537c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, 538c2526597SStephen Boyd .num_parents = 6, 539c2526597SStephen Boyd .ops = &clk_gfx3d_ops, 540c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 541c2526597SStephen Boyd }, 542c2526597SStephen Boyd }; 543c2526597SStephen Boyd 544c2526597SStephen Boyd static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { 545c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 546c2526597SStephen Boyd { } 547c2526597SStephen Boyd }; 548c2526597SStephen Boyd 549c2526597SStephen Boyd static struct clk_rcg2 rbbmtimer_clk_src = { 550c2526597SStephen Boyd .cmd_rcgr = 0x4090, 551c2526597SStephen Boyd .hid_width = 5, 552c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 553c2526597SStephen Boyd .freq_tbl = ftbl_rbbmtimer_clk_src, 554c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 555c2526597SStephen Boyd .name = "rbbmtimer_clk_src", 556c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 557c2526597SStephen Boyd .num_parents = 4, 558c2526597SStephen Boyd .ops = &clk_rcg2_ops, 559c2526597SStephen Boyd }, 560c2526597SStephen Boyd }; 561c2526597SStephen Boyd 562c2526597SStephen Boyd static struct clk_rcg2 isense_clk_src = { 563c2526597SStephen Boyd .cmd_rcgr = 0x4010, 564c2526597SStephen Boyd .hid_width = 5, 565c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map, 566c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 567c2526597SStephen Boyd .name = "isense_clk_src", 568c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div, 569c2526597SStephen Boyd .num_parents = 7, 570c2526597SStephen Boyd .ops = &clk_rcg2_ops, 571c2526597SStephen Boyd }, 572c2526597SStephen Boyd }; 573c2526597SStephen Boyd 574c2526597SStephen Boyd static const struct freq_tbl ftbl_rbcpr_clk_src[] = { 575c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 576c2526597SStephen Boyd F(50000000, P_GPLL0, 12, 0, 0), 577c2526597SStephen Boyd { } 578c2526597SStephen Boyd }; 579c2526597SStephen Boyd 580c2526597SStephen Boyd static struct clk_rcg2 rbcpr_clk_src = { 581c2526597SStephen Boyd .cmd_rcgr = 0x4060, 582c2526597SStephen Boyd .hid_width = 5, 583c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 584c2526597SStephen Boyd .freq_tbl = ftbl_rbcpr_clk_src, 585c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 586c2526597SStephen Boyd .name = "rbcpr_clk_src", 587c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 588c2526597SStephen Boyd .num_parents = 4, 589c2526597SStephen Boyd .ops = &clk_rcg2_ops, 590c2526597SStephen Boyd }, 591c2526597SStephen Boyd }; 592c2526597SStephen Boyd 593c2526597SStephen Boyd static const struct freq_tbl ftbl_video_core_clk_src[] = { 594c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 595c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 596c2526597SStephen Boyd F(346666667, P_MMPLL3, 3, 0, 0), 597c2526597SStephen Boyd F(520000000, P_MMPLL3, 2, 0, 0), 598c2526597SStephen Boyd { } 599c2526597SStephen Boyd }; 600c2526597SStephen Boyd 601c2526597SStephen Boyd static struct clk_rcg2 video_core_clk_src = { 602c2526597SStephen Boyd .cmd_rcgr = 0x1000, 603c2526597SStephen Boyd .mnd_width = 8, 604c2526597SStephen Boyd .hid_width = 5, 605c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 606c2526597SStephen Boyd .freq_tbl = ftbl_video_core_clk_src, 607c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 608c2526597SStephen Boyd .name = "video_core_clk_src", 609c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 610c2526597SStephen Boyd .num_parents = 5, 611c2526597SStephen Boyd .ops = &clk_rcg2_ops, 612c2526597SStephen Boyd }, 613c2526597SStephen Boyd }; 614c2526597SStephen Boyd 615c2526597SStephen Boyd static struct clk_rcg2 video_subcore0_clk_src = { 616c2526597SStephen Boyd .cmd_rcgr = 0x1060, 617c2526597SStephen Boyd .mnd_width = 8, 618c2526597SStephen Boyd .hid_width = 5, 619c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 620c2526597SStephen Boyd .freq_tbl = ftbl_video_core_clk_src, 621c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 622c2526597SStephen Boyd .name = "video_subcore0_clk_src", 623c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 624c2526597SStephen Boyd .num_parents = 5, 625c2526597SStephen Boyd .ops = &clk_rcg2_ops, 626c2526597SStephen Boyd }, 627c2526597SStephen Boyd }; 628c2526597SStephen Boyd 629c2526597SStephen Boyd static struct clk_rcg2 video_subcore1_clk_src = { 630c2526597SStephen Boyd .cmd_rcgr = 0x1080, 631c2526597SStephen Boyd .mnd_width = 8, 632c2526597SStephen Boyd .hid_width = 5, 633c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 634c2526597SStephen Boyd .freq_tbl = ftbl_video_core_clk_src, 635c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 636c2526597SStephen Boyd .name = "video_subcore1_clk_src", 637c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 638c2526597SStephen Boyd .num_parents = 5, 639c2526597SStephen Boyd .ops = &clk_rcg2_ops, 640c2526597SStephen Boyd }, 641c2526597SStephen Boyd }; 642c2526597SStephen Boyd 643c2526597SStephen Boyd static struct clk_rcg2 pclk0_clk_src = { 644c2526597SStephen Boyd .cmd_rcgr = 0x2000, 645c2526597SStephen Boyd .mnd_width = 8, 646c2526597SStephen Boyd .hid_width = 5, 647c2526597SStephen Boyd .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 648c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 649c2526597SStephen Boyd .name = "pclk0_clk_src", 650c2526597SStephen Boyd .parent_names = mmss_xo_dsi0pll_dsi1pll, 651c2526597SStephen Boyd .num_parents = 3, 652c2526597SStephen Boyd .ops = &clk_pixel_ops, 653c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 654c2526597SStephen Boyd }, 655c2526597SStephen Boyd }; 656c2526597SStephen Boyd 657c2526597SStephen Boyd static struct clk_rcg2 pclk1_clk_src = { 658c2526597SStephen Boyd .cmd_rcgr = 0x2020, 659c2526597SStephen Boyd .mnd_width = 8, 660c2526597SStephen Boyd .hid_width = 5, 661c2526597SStephen Boyd .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 662c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 663c2526597SStephen Boyd .name = "pclk1_clk_src", 664c2526597SStephen Boyd .parent_names = mmss_xo_dsi0pll_dsi1pll, 665c2526597SStephen Boyd .num_parents = 3, 666c2526597SStephen Boyd .ops = &clk_pixel_ops, 667c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 668c2526597SStephen Boyd }, 669c2526597SStephen Boyd }; 670c2526597SStephen Boyd 671c2526597SStephen Boyd static const struct freq_tbl ftbl_mdp_clk_src[] = { 672c2526597SStephen Boyd F(85714286, P_GPLL0, 7, 0, 0), 673c2526597SStephen Boyd F(100000000, P_GPLL0, 6, 0, 0), 674c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 675c2526597SStephen Boyd F(171428571, P_GPLL0, 3.5, 0, 0), 676c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 677c2526597SStephen Boyd F(275000000, P_MMPLL5, 3, 0, 0), 678c2526597SStephen Boyd F(300000000, P_GPLL0, 2, 0, 0), 679c2526597SStephen Boyd F(330000000, P_MMPLL5, 2.5, 0, 0), 680c2526597SStephen Boyd F(412500000, P_MMPLL5, 2, 0, 0), 681c2526597SStephen Boyd { } 682c2526597SStephen Boyd }; 683c2526597SStephen Boyd 684c2526597SStephen Boyd static struct clk_rcg2 mdp_clk_src = { 685c2526597SStephen Boyd .cmd_rcgr = 0x2040, 686c2526597SStephen Boyd .hid_width = 5, 687c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map, 688c2526597SStephen Boyd .freq_tbl = ftbl_mdp_clk_src, 689c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 690c2526597SStephen Boyd .name = "mdp_clk_src", 691c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, 692c2526597SStephen Boyd .num_parents = 5, 693c2526597SStephen Boyd .ops = &clk_rcg2_ops, 694c2526597SStephen Boyd }, 695c2526597SStephen Boyd }; 696c2526597SStephen Boyd 697c2526597SStephen Boyd static struct freq_tbl extpclk_freq_tbl[] = { 698c2526597SStephen Boyd { .src = P_HDMIPLL }, 699c2526597SStephen Boyd { } 700c2526597SStephen Boyd }; 701c2526597SStephen Boyd 702c2526597SStephen Boyd static struct clk_rcg2 extpclk_clk_src = { 703c2526597SStephen Boyd .cmd_rcgr = 0x2060, 704c2526597SStephen Boyd .hid_width = 5, 705c2526597SStephen Boyd .parent_map = mmss_xo_hdmi_map, 706c2526597SStephen Boyd .freq_tbl = extpclk_freq_tbl, 707c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 708c2526597SStephen Boyd .name = "extpclk_clk_src", 709c2526597SStephen Boyd .parent_names = mmss_xo_hdmi, 710c2526597SStephen Boyd .num_parents = 2, 711c2526597SStephen Boyd .ops = &clk_byte_ops, 712c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 713c2526597SStephen Boyd }, 714c2526597SStephen Boyd }; 715c2526597SStephen Boyd 716c2526597SStephen Boyd static struct freq_tbl ftbl_mdss_vsync_clk[] = { 717c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 718c2526597SStephen Boyd { } 719c2526597SStephen Boyd }; 720c2526597SStephen Boyd 721c2526597SStephen Boyd static struct clk_rcg2 vsync_clk_src = { 722c2526597SStephen Boyd .cmd_rcgr = 0x2080, 723c2526597SStephen Boyd .hid_width = 5, 724c2526597SStephen Boyd .parent_map = mmss_xo_gpll0_gpll0_div_map, 725c2526597SStephen Boyd .freq_tbl = ftbl_mdss_vsync_clk, 726c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 727c2526597SStephen Boyd .name = "vsync_clk_src", 728c2526597SStephen Boyd .parent_names = mmss_xo_gpll0_gpll0_div, 729c2526597SStephen Boyd .num_parents = 3, 730c2526597SStephen Boyd .ops = &clk_rcg2_ops, 731c2526597SStephen Boyd }, 732c2526597SStephen Boyd }; 733c2526597SStephen Boyd 734c2526597SStephen Boyd static struct freq_tbl ftbl_mdss_hdmi_clk[] = { 735c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 736c2526597SStephen Boyd { } 737c2526597SStephen Boyd }; 738c2526597SStephen Boyd 739c2526597SStephen Boyd static struct clk_rcg2 hdmi_clk_src = { 740c2526597SStephen Boyd .cmd_rcgr = 0x2100, 741c2526597SStephen Boyd .hid_width = 5, 742c2526597SStephen Boyd .parent_map = mmss_xo_gpll0_gpll0_div_map, 743c2526597SStephen Boyd .freq_tbl = ftbl_mdss_hdmi_clk, 744c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 745c2526597SStephen Boyd .name = "hdmi_clk_src", 746c2526597SStephen Boyd .parent_names = mmss_xo_gpll0_gpll0_div, 747c2526597SStephen Boyd .num_parents = 3, 748c2526597SStephen Boyd .ops = &clk_rcg2_ops, 749c2526597SStephen Boyd }, 750c2526597SStephen Boyd }; 751c2526597SStephen Boyd 752c2526597SStephen Boyd static struct clk_rcg2 byte0_clk_src = { 753c2526597SStephen Boyd .cmd_rcgr = 0x2120, 754c2526597SStephen Boyd .hid_width = 5, 755c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 756c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 757c2526597SStephen Boyd .name = "byte0_clk_src", 758c2526597SStephen Boyd .parent_names = mmss_xo_dsibyte, 759c2526597SStephen Boyd .num_parents = 3, 760c2526597SStephen Boyd .ops = &clk_byte2_ops, 761c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 762c2526597SStephen Boyd }, 763c2526597SStephen Boyd }; 764c2526597SStephen Boyd 765c2526597SStephen Boyd static struct clk_rcg2 byte1_clk_src = { 766c2526597SStephen Boyd .cmd_rcgr = 0x2140, 767c2526597SStephen Boyd .hid_width = 5, 768c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 769c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 770c2526597SStephen Boyd .name = "byte1_clk_src", 771c2526597SStephen Boyd .parent_names = mmss_xo_dsibyte, 772c2526597SStephen Boyd .num_parents = 3, 773c2526597SStephen Boyd .ops = &clk_byte2_ops, 774c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 775c2526597SStephen Boyd }, 776c2526597SStephen Boyd }; 777c2526597SStephen Boyd 778c2526597SStephen Boyd static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { 779c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 780c2526597SStephen Boyd { } 781c2526597SStephen Boyd }; 782c2526597SStephen Boyd 783c2526597SStephen Boyd static struct clk_rcg2 esc0_clk_src = { 784c2526597SStephen Boyd .cmd_rcgr = 0x2160, 785c2526597SStephen Boyd .hid_width = 5, 786c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 787c2526597SStephen Boyd .freq_tbl = ftbl_mdss_esc0_1_clk, 788c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 789c2526597SStephen Boyd .name = "esc0_clk_src", 790c2526597SStephen Boyd .parent_names = mmss_xo_dsibyte, 791c2526597SStephen Boyd .num_parents = 3, 792c2526597SStephen Boyd .ops = &clk_rcg2_ops, 793c2526597SStephen Boyd }, 794c2526597SStephen Boyd }; 795c2526597SStephen Boyd 796c2526597SStephen Boyd static struct clk_rcg2 esc1_clk_src = { 797c2526597SStephen Boyd .cmd_rcgr = 0x2180, 798c2526597SStephen Boyd .hid_width = 5, 799c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 800c2526597SStephen Boyd .freq_tbl = ftbl_mdss_esc0_1_clk, 801c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 802c2526597SStephen Boyd .name = "esc1_clk_src", 803c2526597SStephen Boyd .parent_names = mmss_xo_dsibyte, 804c2526597SStephen Boyd .num_parents = 3, 805c2526597SStephen Boyd .ops = &clk_rcg2_ops, 806c2526597SStephen Boyd }, 807c2526597SStephen Boyd }; 808c2526597SStephen Boyd 809c2526597SStephen Boyd static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { 810c2526597SStephen Boyd F(10000, P_XO, 16, 1, 120), 811c2526597SStephen Boyd F(24000, P_XO, 16, 1, 50), 812c2526597SStephen Boyd F(6000000, P_GPLL0_DIV, 10, 1, 5), 813c2526597SStephen Boyd F(12000000, P_GPLL0_DIV, 1, 1, 25), 814c2526597SStephen Boyd F(13000000, P_GPLL0_DIV, 2, 13, 150), 815c2526597SStephen Boyd F(24000000, P_GPLL0_DIV, 1, 2, 25), 816c2526597SStephen Boyd { } 817c2526597SStephen Boyd }; 818c2526597SStephen Boyd 819c2526597SStephen Boyd static struct clk_rcg2 camss_gp0_clk_src = { 820c2526597SStephen Boyd .cmd_rcgr = 0x3420, 821c2526597SStephen Boyd .mnd_width = 8, 822c2526597SStephen Boyd .hid_width = 5, 823c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 824c2526597SStephen Boyd .freq_tbl = ftbl_camss_gp0_clk_src, 825c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 826c2526597SStephen Boyd .name = "camss_gp0_clk_src", 827c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 828c2526597SStephen Boyd .num_parents = 5, 829c2526597SStephen Boyd .ops = &clk_rcg2_ops, 830c2526597SStephen Boyd }, 831c2526597SStephen Boyd }; 832c2526597SStephen Boyd 833c2526597SStephen Boyd static struct clk_rcg2 camss_gp1_clk_src = { 834c2526597SStephen Boyd .cmd_rcgr = 0x3450, 835c2526597SStephen Boyd .mnd_width = 8, 836c2526597SStephen Boyd .hid_width = 5, 837c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 838c2526597SStephen Boyd .freq_tbl = ftbl_camss_gp0_clk_src, 839c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 840c2526597SStephen Boyd .name = "camss_gp1_clk_src", 841c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 842c2526597SStephen Boyd .num_parents = 5, 843c2526597SStephen Boyd .ops = &clk_rcg2_ops, 844c2526597SStephen Boyd }, 845c2526597SStephen Boyd }; 846c2526597SStephen Boyd 847c2526597SStephen Boyd static const struct freq_tbl ftbl_mclk0_clk_src[] = { 848c2526597SStephen Boyd F(4800000, P_XO, 4, 0, 0), 849c2526597SStephen Boyd F(6000000, P_GPLL0_DIV, 10, 1, 5), 850c2526597SStephen Boyd F(8000000, P_GPLL0_DIV, 1, 2, 75), 851c2526597SStephen Boyd F(9600000, P_XO, 2, 0, 0), 852c2526597SStephen Boyd F(16666667, P_GPLL0_DIV, 2, 1, 9), 853c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 854c2526597SStephen Boyd F(24000000, P_GPLL0_DIV, 1, 2, 25), 855c2526597SStephen Boyd F(33333333, P_GPLL0_DIV, 1, 1, 9), 856c2526597SStephen Boyd F(48000000, P_GPLL0, 1, 2, 25), 857c2526597SStephen Boyd F(66666667, P_GPLL0, 1, 1, 9), 858c2526597SStephen Boyd { } 859c2526597SStephen Boyd }; 860c2526597SStephen Boyd 861c2526597SStephen Boyd static struct clk_rcg2 mclk0_clk_src = { 862c2526597SStephen Boyd .cmd_rcgr = 0x3360, 863c2526597SStephen Boyd .mnd_width = 8, 864c2526597SStephen Boyd .hid_width = 5, 865c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 866c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 867c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 868c2526597SStephen Boyd .name = "mclk0_clk_src", 869c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 870c2526597SStephen Boyd .num_parents = 5, 871c2526597SStephen Boyd .ops = &clk_rcg2_ops, 872c2526597SStephen Boyd }, 873c2526597SStephen Boyd }; 874c2526597SStephen Boyd 875c2526597SStephen Boyd static struct clk_rcg2 mclk1_clk_src = { 876c2526597SStephen Boyd .cmd_rcgr = 0x3390, 877c2526597SStephen Boyd .mnd_width = 8, 878c2526597SStephen Boyd .hid_width = 5, 879c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 880c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 881c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 882c2526597SStephen Boyd .name = "mclk1_clk_src", 883c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 884c2526597SStephen Boyd .num_parents = 5, 885c2526597SStephen Boyd .ops = &clk_rcg2_ops, 886c2526597SStephen Boyd }, 887c2526597SStephen Boyd }; 888c2526597SStephen Boyd 889c2526597SStephen Boyd static struct clk_rcg2 mclk2_clk_src = { 890c2526597SStephen Boyd .cmd_rcgr = 0x33c0, 891c2526597SStephen Boyd .mnd_width = 8, 892c2526597SStephen Boyd .hid_width = 5, 893c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 894c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 895c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 896c2526597SStephen Boyd .name = "mclk2_clk_src", 897c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 898c2526597SStephen Boyd .num_parents = 5, 899c2526597SStephen Boyd .ops = &clk_rcg2_ops, 900c2526597SStephen Boyd }, 901c2526597SStephen Boyd }; 902c2526597SStephen Boyd 903c2526597SStephen Boyd static struct clk_rcg2 mclk3_clk_src = { 904c2526597SStephen Boyd .cmd_rcgr = 0x33f0, 905c2526597SStephen Boyd .mnd_width = 8, 906c2526597SStephen Boyd .hid_width = 5, 907c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 908c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 909c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 910c2526597SStephen Boyd .name = "mclk3_clk_src", 911c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 912c2526597SStephen Boyd .num_parents = 5, 913c2526597SStephen Boyd .ops = &clk_rcg2_ops, 914c2526597SStephen Boyd }, 915c2526597SStephen Boyd }; 916c2526597SStephen Boyd 917c2526597SStephen Boyd static const struct freq_tbl ftbl_cci_clk_src[] = { 918c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 919c2526597SStephen Boyd F(37500000, P_GPLL0, 16, 0, 0), 920c2526597SStephen Boyd F(50000000, P_GPLL0, 12, 0, 0), 921c2526597SStephen Boyd F(100000000, P_GPLL0, 6, 0, 0), 922c2526597SStephen Boyd { } 923c2526597SStephen Boyd }; 924c2526597SStephen Boyd 925c2526597SStephen Boyd static struct clk_rcg2 cci_clk_src = { 926c2526597SStephen Boyd .cmd_rcgr = 0x3300, 927c2526597SStephen Boyd .mnd_width = 8, 928c2526597SStephen Boyd .hid_width = 5, 929c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 930c2526597SStephen Boyd .freq_tbl = ftbl_cci_clk_src, 931c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 932c2526597SStephen Boyd .name = "cci_clk_src", 933c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 934c2526597SStephen Boyd .num_parents = 5, 935c2526597SStephen Boyd .ops = &clk_rcg2_ops, 936c2526597SStephen Boyd }, 937c2526597SStephen Boyd }; 938c2526597SStephen Boyd 939c2526597SStephen Boyd static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { 940c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 941c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 942c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 943c2526597SStephen Boyd { } 944c2526597SStephen Boyd }; 945c2526597SStephen Boyd 946c2526597SStephen Boyd static struct clk_rcg2 csi0phytimer_clk_src = { 947c2526597SStephen Boyd .cmd_rcgr = 0x3000, 948c2526597SStephen Boyd .hid_width = 5, 949c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 950c2526597SStephen Boyd .freq_tbl = ftbl_csi0phytimer_clk_src, 951c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 952c2526597SStephen Boyd .name = "csi0phytimer_clk_src", 953c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 954c2526597SStephen Boyd .num_parents = 7, 955c2526597SStephen Boyd .ops = &clk_rcg2_ops, 956c2526597SStephen Boyd }, 957c2526597SStephen Boyd }; 958c2526597SStephen Boyd 959c2526597SStephen Boyd static struct clk_rcg2 csi1phytimer_clk_src = { 960c2526597SStephen Boyd .cmd_rcgr = 0x3030, 961c2526597SStephen Boyd .hid_width = 5, 962c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 963c2526597SStephen Boyd .freq_tbl = ftbl_csi0phytimer_clk_src, 964c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 965c2526597SStephen Boyd .name = "csi1phytimer_clk_src", 966c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 967c2526597SStephen Boyd .num_parents = 7, 968c2526597SStephen Boyd .ops = &clk_rcg2_ops, 969c2526597SStephen Boyd }, 970c2526597SStephen Boyd }; 971c2526597SStephen Boyd 972c2526597SStephen Boyd static struct clk_rcg2 csi2phytimer_clk_src = { 973c2526597SStephen Boyd .cmd_rcgr = 0x3060, 974c2526597SStephen Boyd .hid_width = 5, 975c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 976c2526597SStephen Boyd .freq_tbl = ftbl_csi0phytimer_clk_src, 977c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 978c2526597SStephen Boyd .name = "csi2phytimer_clk_src", 979c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 980c2526597SStephen Boyd .num_parents = 7, 981c2526597SStephen Boyd .ops = &clk_rcg2_ops, 982c2526597SStephen Boyd }, 983c2526597SStephen Boyd }; 984c2526597SStephen Boyd 985c2526597SStephen Boyd static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = { 986c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 987c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 988c2526597SStephen Boyd F(320000000, P_MMPLL4, 3, 0, 0), 989c2526597SStephen Boyd F(384000000, P_MMPLL4, 2.5, 0, 0), 990c2526597SStephen Boyd { } 991c2526597SStephen Boyd }; 992c2526597SStephen Boyd 993c2526597SStephen Boyd static struct clk_rcg2 csiphy0_3p_clk_src = { 994c2526597SStephen Boyd .cmd_rcgr = 0x3240, 995c2526597SStephen Boyd .hid_width = 5, 996c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 997c2526597SStephen Boyd .freq_tbl = ftbl_csiphy0_3p_clk_src, 998c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 999c2526597SStephen Boyd .name = "csiphy0_3p_clk_src", 1000c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1001c2526597SStephen Boyd .num_parents = 7, 1002c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1003c2526597SStephen Boyd }, 1004c2526597SStephen Boyd }; 1005c2526597SStephen Boyd 1006c2526597SStephen Boyd static struct clk_rcg2 csiphy1_3p_clk_src = { 1007c2526597SStephen Boyd .cmd_rcgr = 0x3260, 1008c2526597SStephen Boyd .hid_width = 5, 1009c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1010c2526597SStephen Boyd .freq_tbl = ftbl_csiphy0_3p_clk_src, 1011c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1012c2526597SStephen Boyd .name = "csiphy1_3p_clk_src", 1013c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1014c2526597SStephen Boyd .num_parents = 7, 1015c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1016c2526597SStephen Boyd }, 1017c2526597SStephen Boyd }; 1018c2526597SStephen Boyd 1019c2526597SStephen Boyd static struct clk_rcg2 csiphy2_3p_clk_src = { 1020c2526597SStephen Boyd .cmd_rcgr = 0x3280, 1021c2526597SStephen Boyd .hid_width = 5, 1022c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1023c2526597SStephen Boyd .freq_tbl = ftbl_csiphy0_3p_clk_src, 1024c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1025c2526597SStephen Boyd .name = "csiphy2_3p_clk_src", 1026c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1027c2526597SStephen Boyd .num_parents = 7, 1028c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1029c2526597SStephen Boyd }, 1030c2526597SStephen Boyd }; 1031c2526597SStephen Boyd 1032c2526597SStephen Boyd static const struct freq_tbl ftbl_jpeg0_clk_src[] = { 1033c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 1034c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 1035c2526597SStephen Boyd F(228571429, P_MMPLL0, 3.5, 0, 0), 1036c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 1037c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1038c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1039c2526597SStephen Boyd { } 1040c2526597SStephen Boyd }; 1041c2526597SStephen Boyd 1042c2526597SStephen Boyd static struct clk_rcg2 jpeg0_clk_src = { 1043c2526597SStephen Boyd .cmd_rcgr = 0x3500, 1044c2526597SStephen Boyd .hid_width = 5, 1045c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1046c2526597SStephen Boyd .freq_tbl = ftbl_jpeg0_clk_src, 1047c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1048c2526597SStephen Boyd .name = "jpeg0_clk_src", 1049c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1050c2526597SStephen Boyd .num_parents = 7, 1051c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1052c2526597SStephen Boyd }, 1053c2526597SStephen Boyd }; 1054c2526597SStephen Boyd 1055c2526597SStephen Boyd static const struct freq_tbl ftbl_jpeg2_clk_src[] = { 1056c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 1057c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 1058c2526597SStephen Boyd F(228571429, P_MMPLL0, 3.5, 0, 0), 1059c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 1060c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1061c2526597SStephen Boyd { } 1062c2526597SStephen Boyd }; 1063c2526597SStephen Boyd 1064c2526597SStephen Boyd static struct clk_rcg2 jpeg2_clk_src = { 1065c2526597SStephen Boyd .cmd_rcgr = 0x3540, 1066c2526597SStephen Boyd .hid_width = 5, 1067c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1068c2526597SStephen Boyd .freq_tbl = ftbl_jpeg2_clk_src, 1069c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1070c2526597SStephen Boyd .name = "jpeg2_clk_src", 1071c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1072c2526597SStephen Boyd .num_parents = 7, 1073c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1074c2526597SStephen Boyd }, 1075c2526597SStephen Boyd }; 1076c2526597SStephen Boyd 1077c2526597SStephen Boyd static struct clk_rcg2 jpeg_dma_clk_src = { 1078c2526597SStephen Boyd .cmd_rcgr = 0x3560, 1079c2526597SStephen Boyd .hid_width = 5, 1080c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1081c2526597SStephen Boyd .freq_tbl = ftbl_jpeg0_clk_src, 1082c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1083c2526597SStephen Boyd .name = "jpeg_dma_clk_src", 1084c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1085c2526597SStephen Boyd .num_parents = 7, 1086c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1087c2526597SStephen Boyd }, 1088c2526597SStephen Boyd }; 1089c2526597SStephen Boyd 1090c2526597SStephen Boyd static const struct freq_tbl ftbl_vfe0_clk_src[] = { 1091c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 1092c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1093c2526597SStephen Boyd F(300000000, P_GPLL0, 2, 0, 0), 1094c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1095c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1096c2526597SStephen Boyd F(600000000, P_GPLL0, 1, 0, 0), 1097c2526597SStephen Boyd { } 1098c2526597SStephen Boyd }; 1099c2526597SStephen Boyd 1100c2526597SStephen Boyd static struct clk_rcg2 vfe0_clk_src = { 1101c2526597SStephen Boyd .cmd_rcgr = 0x3600, 1102c2526597SStephen Boyd .hid_width = 5, 1103c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1104c2526597SStephen Boyd .freq_tbl = ftbl_vfe0_clk_src, 1105c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1106c2526597SStephen Boyd .name = "vfe0_clk_src", 1107c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1108c2526597SStephen Boyd .num_parents = 7, 1109c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1110c2526597SStephen Boyd }, 1111c2526597SStephen Boyd }; 1112c2526597SStephen Boyd 1113c2526597SStephen Boyd static struct clk_rcg2 vfe1_clk_src = { 1114c2526597SStephen Boyd .cmd_rcgr = 0x3620, 1115c2526597SStephen Boyd .hid_width = 5, 1116c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1117c2526597SStephen Boyd .freq_tbl = ftbl_vfe0_clk_src, 1118c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1119c2526597SStephen Boyd .name = "vfe1_clk_src", 1120c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1121c2526597SStephen Boyd .num_parents = 7, 1122c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1123c2526597SStephen Boyd }, 1124c2526597SStephen Boyd }; 1125c2526597SStephen Boyd 1126c2526597SStephen Boyd static const struct freq_tbl ftbl_cpp_clk_src[] = { 1127c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1128c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1129c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1130c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1131c2526597SStephen Boyd F(640000000, P_MMPLL4, 1.5, 0, 0), 1132c2526597SStephen Boyd { } 1133c2526597SStephen Boyd }; 1134c2526597SStephen Boyd 1135c2526597SStephen Boyd static struct clk_rcg2 cpp_clk_src = { 1136c2526597SStephen Boyd .cmd_rcgr = 0x3640, 1137c2526597SStephen Boyd .hid_width = 5, 1138c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1139c2526597SStephen Boyd .freq_tbl = ftbl_cpp_clk_src, 1140c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1141c2526597SStephen Boyd .name = "cpp_clk_src", 1142c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1143c2526597SStephen Boyd .num_parents = 7, 1144c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1145c2526597SStephen Boyd }, 1146c2526597SStephen Boyd }; 1147c2526597SStephen Boyd 1148c2526597SStephen Boyd static const struct freq_tbl ftbl_csi0_clk_src[] = { 1149c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1150c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1151c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 1152c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1153c2526597SStephen Boyd F(600000000, P_GPLL0, 1, 0, 0), 1154c2526597SStephen Boyd { } 1155c2526597SStephen Boyd }; 1156c2526597SStephen Boyd 1157c2526597SStephen Boyd static struct clk_rcg2 csi0_clk_src = { 1158c2526597SStephen Boyd .cmd_rcgr = 0x3090, 1159c2526597SStephen Boyd .hid_width = 5, 1160c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1161c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1162c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1163c2526597SStephen Boyd .name = "csi0_clk_src", 1164c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1165c2526597SStephen Boyd .num_parents = 7, 1166c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1167c2526597SStephen Boyd }, 1168c2526597SStephen Boyd }; 1169c2526597SStephen Boyd 1170c2526597SStephen Boyd static struct clk_rcg2 csi1_clk_src = { 1171c2526597SStephen Boyd .cmd_rcgr = 0x3100, 1172c2526597SStephen Boyd .hid_width = 5, 1173c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1174c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1175c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1176c2526597SStephen Boyd .name = "csi1_clk_src", 1177c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1178c2526597SStephen Boyd .num_parents = 7, 1179c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1180c2526597SStephen Boyd }, 1181c2526597SStephen Boyd }; 1182c2526597SStephen Boyd 1183c2526597SStephen Boyd static struct clk_rcg2 csi2_clk_src = { 1184c2526597SStephen Boyd .cmd_rcgr = 0x3160, 1185c2526597SStephen Boyd .hid_width = 5, 1186c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1187c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1188c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1189c2526597SStephen Boyd .name = "csi2_clk_src", 1190c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1191c2526597SStephen Boyd .num_parents = 7, 1192c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1193c2526597SStephen Boyd }, 1194c2526597SStephen Boyd }; 1195c2526597SStephen Boyd 1196c2526597SStephen Boyd static struct clk_rcg2 csi3_clk_src = { 1197c2526597SStephen Boyd .cmd_rcgr = 0x31c0, 1198c2526597SStephen Boyd .hid_width = 5, 1199c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1200c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1201c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1202c2526597SStephen Boyd .name = "csi3_clk_src", 1203c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1204c2526597SStephen Boyd .num_parents = 7, 1205c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1206c2526597SStephen Boyd }, 1207c2526597SStephen Boyd }; 1208c2526597SStephen Boyd 1209c2526597SStephen Boyd static const struct freq_tbl ftbl_fd_core_clk_src[] = { 1210c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1211c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1212c2526597SStephen Boyd F(400000000, P_MMPLL0, 2, 0, 0), 1213c2526597SStephen Boyd { } 1214c2526597SStephen Boyd }; 1215c2526597SStephen Boyd 1216c2526597SStephen Boyd static struct clk_rcg2 fd_core_clk_src = { 1217c2526597SStephen Boyd .cmd_rcgr = 0x3b00, 1218c2526597SStephen Boyd .hid_width = 5, 1219c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 1220c2526597SStephen Boyd .freq_tbl = ftbl_fd_core_clk_src, 1221c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1222c2526597SStephen Boyd .name = "fd_core_clk_src", 1223c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 1224c2526597SStephen Boyd .num_parents = 5, 1225c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1226c2526597SStephen Boyd }, 1227c2526597SStephen Boyd }; 1228c2526597SStephen Boyd 1229c2526597SStephen Boyd static struct clk_branch mmss_mmagic_ahb_clk = { 1230c2526597SStephen Boyd .halt_reg = 0x5024, 1231c2526597SStephen Boyd .clkr = { 1232c2526597SStephen Boyd .enable_reg = 0x5024, 1233c2526597SStephen Boyd .enable_mask = BIT(0), 1234c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1235c2526597SStephen Boyd .name = "mmss_mmagic_ahb_clk", 1236c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1237c2526597SStephen Boyd .num_parents = 1, 12387705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1239c2526597SStephen Boyd .ops = &clk_branch2_ops, 1240c2526597SStephen Boyd }, 1241c2526597SStephen Boyd }, 1242c2526597SStephen Boyd }; 1243c2526597SStephen Boyd 1244c2526597SStephen Boyd static struct clk_branch mmss_mmagic_cfg_ahb_clk = { 1245c2526597SStephen Boyd .halt_reg = 0x5054, 1246c2526597SStephen Boyd .clkr = { 1247c2526597SStephen Boyd .enable_reg = 0x5054, 1248c2526597SStephen Boyd .enable_mask = BIT(0), 1249c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1250c2526597SStephen Boyd .name = "mmss_mmagic_cfg_ahb_clk", 1251c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1252c2526597SStephen Boyd .num_parents = 1, 12537705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1254c2526597SStephen Boyd .ops = &clk_branch2_ops, 1255c2526597SStephen Boyd }, 1256c2526597SStephen Boyd }, 1257c2526597SStephen Boyd }; 1258c2526597SStephen Boyd 1259c2526597SStephen Boyd static struct clk_branch mmss_misc_ahb_clk = { 1260c2526597SStephen Boyd .halt_reg = 0x5018, 1261c2526597SStephen Boyd .clkr = { 1262c2526597SStephen Boyd .enable_reg = 0x5018, 1263c2526597SStephen Boyd .enable_mask = BIT(0), 1264c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1265c2526597SStephen Boyd .name = "mmss_misc_ahb_clk", 1266c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1267c2526597SStephen Boyd .num_parents = 1, 1268c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1269c2526597SStephen Boyd .ops = &clk_branch2_ops, 1270c2526597SStephen Boyd }, 1271c2526597SStephen Boyd }, 1272c2526597SStephen Boyd }; 1273c2526597SStephen Boyd 1274c2526597SStephen Boyd static struct clk_branch mmss_misc_cxo_clk = { 1275c2526597SStephen Boyd .halt_reg = 0x5014, 1276c2526597SStephen Boyd .clkr = { 1277c2526597SStephen Boyd .enable_reg = 0x5014, 1278c2526597SStephen Boyd .enable_mask = BIT(0), 1279c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1280c2526597SStephen Boyd .name = "mmss_misc_cxo_clk", 1281c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 1282c2526597SStephen Boyd .num_parents = 1, 1283c2526597SStephen Boyd .ops = &clk_branch2_ops, 1284c2526597SStephen Boyd }, 1285c2526597SStephen Boyd }, 1286c2526597SStephen Boyd }; 1287c2526597SStephen Boyd 1288c2526597SStephen Boyd static struct clk_branch mmss_mmagic_maxi_clk = { 1289c2526597SStephen Boyd .halt_reg = 0x5074, 1290c2526597SStephen Boyd .clkr = { 1291c2526597SStephen Boyd .enable_reg = 0x5074, 1292c2526597SStephen Boyd .enable_mask = BIT(0), 1293c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1294c2526597SStephen Boyd .name = "mmss_mmagic_maxi_clk", 1295c2526597SStephen Boyd .parent_names = (const char *[]){ "maxi_clk_src" }, 1296c2526597SStephen Boyd .num_parents = 1, 1297c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1298c2526597SStephen Boyd .ops = &clk_branch2_ops, 1299c2526597SStephen Boyd }, 1300c2526597SStephen Boyd }, 1301c2526597SStephen Boyd }; 1302c2526597SStephen Boyd 1303c2526597SStephen Boyd static struct clk_branch mmagic_camss_axi_clk = { 1304c2526597SStephen Boyd .halt_reg = 0x3c44, 1305c2526597SStephen Boyd .clkr = { 1306c2526597SStephen Boyd .enable_reg = 0x3c44, 1307c2526597SStephen Boyd .enable_mask = BIT(0), 1308c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1309c2526597SStephen Boyd .name = "mmagic_camss_axi_clk", 1310c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1311c2526597SStephen Boyd .num_parents = 1, 13127705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1313c2526597SStephen Boyd .ops = &clk_branch2_ops, 1314c2526597SStephen Boyd }, 1315c2526597SStephen Boyd }, 1316c2526597SStephen Boyd }; 1317c2526597SStephen Boyd 1318c2526597SStephen Boyd static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = { 1319c2526597SStephen Boyd .halt_reg = 0x3c48, 1320c2526597SStephen Boyd .clkr = { 1321c2526597SStephen Boyd .enable_reg = 0x3c48, 1322c2526597SStephen Boyd .enable_mask = BIT(0), 1323c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1324c2526597SStephen Boyd .name = "mmagic_camss_noc_cfg_ahb_clk", 1325c2526597SStephen Boyd .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1326c2526597SStephen Boyd .num_parents = 1, 13277705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1328c2526597SStephen Boyd .ops = &clk_branch2_ops, 1329c2526597SStephen Boyd }, 1330c2526597SStephen Boyd }, 1331c2526597SStephen Boyd }; 1332c2526597SStephen Boyd 1333c2526597SStephen Boyd static struct clk_branch smmu_vfe_ahb_clk = { 1334c2526597SStephen Boyd .halt_reg = 0x3c04, 1335c2526597SStephen Boyd .clkr = { 1336c2526597SStephen Boyd .enable_reg = 0x3c04, 1337c2526597SStephen Boyd .enable_mask = BIT(0), 1338c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1339c2526597SStephen Boyd .name = "smmu_vfe_ahb_clk", 1340c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1341c2526597SStephen Boyd .num_parents = 1, 1342c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1343c2526597SStephen Boyd .ops = &clk_branch2_ops, 1344c2526597SStephen Boyd }, 1345c2526597SStephen Boyd }, 1346c2526597SStephen Boyd }; 1347c2526597SStephen Boyd 1348c2526597SStephen Boyd static struct clk_branch smmu_vfe_axi_clk = { 1349c2526597SStephen Boyd .halt_reg = 0x3c08, 1350c2526597SStephen Boyd .clkr = { 1351c2526597SStephen Boyd .enable_reg = 0x3c08, 1352c2526597SStephen Boyd .enable_mask = BIT(0), 1353c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1354c2526597SStephen Boyd .name = "smmu_vfe_axi_clk", 1355c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1356c2526597SStephen Boyd .num_parents = 1, 1357c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1358c2526597SStephen Boyd .ops = &clk_branch2_ops, 1359c2526597SStephen Boyd }, 1360c2526597SStephen Boyd }, 1361c2526597SStephen Boyd }; 1362c2526597SStephen Boyd 1363c2526597SStephen Boyd static struct clk_branch smmu_cpp_ahb_clk = { 1364c2526597SStephen Boyd .halt_reg = 0x3c14, 1365c2526597SStephen Boyd .clkr = { 1366c2526597SStephen Boyd .enable_reg = 0x3c14, 1367c2526597SStephen Boyd .enable_mask = BIT(0), 1368c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1369c2526597SStephen Boyd .name = "smmu_cpp_ahb_clk", 1370c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1371c2526597SStephen Boyd .num_parents = 1, 1372c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1373c2526597SStephen Boyd .ops = &clk_branch2_ops, 1374c2526597SStephen Boyd }, 1375c2526597SStephen Boyd }, 1376c2526597SStephen Boyd }; 1377c2526597SStephen Boyd 1378c2526597SStephen Boyd static struct clk_branch smmu_cpp_axi_clk = { 1379c2526597SStephen Boyd .halt_reg = 0x3c18, 1380c2526597SStephen Boyd .clkr = { 1381c2526597SStephen Boyd .enable_reg = 0x3c18, 1382c2526597SStephen Boyd .enable_mask = BIT(0), 1383c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1384c2526597SStephen Boyd .name = "smmu_cpp_axi_clk", 1385c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1386c2526597SStephen Boyd .num_parents = 1, 1387c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1388c2526597SStephen Boyd .ops = &clk_branch2_ops, 1389c2526597SStephen Boyd }, 1390c2526597SStephen Boyd }, 1391c2526597SStephen Boyd }; 1392c2526597SStephen Boyd 1393c2526597SStephen Boyd static struct clk_branch smmu_jpeg_ahb_clk = { 1394c2526597SStephen Boyd .halt_reg = 0x3c24, 1395c2526597SStephen Boyd .clkr = { 1396c2526597SStephen Boyd .enable_reg = 0x3c24, 1397c2526597SStephen Boyd .enable_mask = BIT(0), 1398c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1399c2526597SStephen Boyd .name = "smmu_jpeg_ahb_clk", 1400c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1401c2526597SStephen Boyd .num_parents = 1, 1402c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1403c2526597SStephen Boyd .ops = &clk_branch2_ops, 1404c2526597SStephen Boyd }, 1405c2526597SStephen Boyd }, 1406c2526597SStephen Boyd }; 1407c2526597SStephen Boyd 1408c2526597SStephen Boyd static struct clk_branch smmu_jpeg_axi_clk = { 1409c2526597SStephen Boyd .halt_reg = 0x3c28, 1410c2526597SStephen Boyd .clkr = { 1411c2526597SStephen Boyd .enable_reg = 0x3c28, 1412c2526597SStephen Boyd .enable_mask = BIT(0), 1413c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1414c2526597SStephen Boyd .name = "smmu_jpeg_axi_clk", 1415c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1416c2526597SStephen Boyd .num_parents = 1, 1417c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1418c2526597SStephen Boyd .ops = &clk_branch2_ops, 1419c2526597SStephen Boyd }, 1420c2526597SStephen Boyd }, 1421c2526597SStephen Boyd }; 1422c2526597SStephen Boyd 1423c2526597SStephen Boyd static struct clk_branch mmagic_mdss_axi_clk = { 1424c2526597SStephen Boyd .halt_reg = 0x2474, 1425c2526597SStephen Boyd .clkr = { 1426c2526597SStephen Boyd .enable_reg = 0x2474, 1427c2526597SStephen Boyd .enable_mask = BIT(0), 1428c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1429c2526597SStephen Boyd .name = "mmagic_mdss_axi_clk", 1430c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1431c2526597SStephen Boyd .num_parents = 1, 14327705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1433c2526597SStephen Boyd .ops = &clk_branch2_ops, 1434c2526597SStephen Boyd }, 1435c2526597SStephen Boyd }, 1436c2526597SStephen Boyd }; 1437c2526597SStephen Boyd 1438c2526597SStephen Boyd static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = { 1439c2526597SStephen Boyd .halt_reg = 0x2478, 1440c2526597SStephen Boyd .clkr = { 1441c2526597SStephen Boyd .enable_reg = 0x2478, 1442c2526597SStephen Boyd .enable_mask = BIT(0), 1443c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1444c2526597SStephen Boyd .name = "mmagic_mdss_noc_cfg_ahb_clk", 1445c2526597SStephen Boyd .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1446c2526597SStephen Boyd .num_parents = 1, 14477705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1448c2526597SStephen Boyd .ops = &clk_branch2_ops, 1449c2526597SStephen Boyd }, 1450c2526597SStephen Boyd }, 1451c2526597SStephen Boyd }; 1452c2526597SStephen Boyd 1453c2526597SStephen Boyd static struct clk_branch smmu_rot_ahb_clk = { 1454c2526597SStephen Boyd .halt_reg = 0x2444, 1455c2526597SStephen Boyd .clkr = { 1456c2526597SStephen Boyd .enable_reg = 0x2444, 1457c2526597SStephen Boyd .enable_mask = BIT(0), 1458c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1459c2526597SStephen Boyd .name = "smmu_rot_ahb_clk", 1460c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1461c2526597SStephen Boyd .num_parents = 1, 1462c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1463c2526597SStephen Boyd .ops = &clk_branch2_ops, 1464c2526597SStephen Boyd }, 1465c2526597SStephen Boyd }, 1466c2526597SStephen Boyd }; 1467c2526597SStephen Boyd 1468c2526597SStephen Boyd static struct clk_branch smmu_rot_axi_clk = { 1469c2526597SStephen Boyd .halt_reg = 0x2448, 1470c2526597SStephen Boyd .clkr = { 1471c2526597SStephen Boyd .enable_reg = 0x2448, 1472c2526597SStephen Boyd .enable_mask = BIT(0), 1473c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1474c2526597SStephen Boyd .name = "smmu_rot_axi_clk", 1475c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1476c2526597SStephen Boyd .num_parents = 1, 1477c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1478c2526597SStephen Boyd .ops = &clk_branch2_ops, 1479c2526597SStephen Boyd }, 1480c2526597SStephen Boyd }, 1481c2526597SStephen Boyd }; 1482c2526597SStephen Boyd 1483c2526597SStephen Boyd static struct clk_branch smmu_mdp_ahb_clk = { 1484c2526597SStephen Boyd .halt_reg = 0x2454, 1485c2526597SStephen Boyd .clkr = { 1486c2526597SStephen Boyd .enable_reg = 0x2454, 1487c2526597SStephen Boyd .enable_mask = BIT(0), 1488c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1489c2526597SStephen Boyd .name = "smmu_mdp_ahb_clk", 1490c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1491c2526597SStephen Boyd .num_parents = 1, 1492c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1493c2526597SStephen Boyd .ops = &clk_branch2_ops, 1494c2526597SStephen Boyd }, 1495c2526597SStephen Boyd }, 1496c2526597SStephen Boyd }; 1497c2526597SStephen Boyd 1498c2526597SStephen Boyd static struct clk_branch smmu_mdp_axi_clk = { 1499c2526597SStephen Boyd .halt_reg = 0x2458, 1500c2526597SStephen Boyd .clkr = { 1501c2526597SStephen Boyd .enable_reg = 0x2458, 1502c2526597SStephen Boyd .enable_mask = BIT(0), 1503c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1504c2526597SStephen Boyd .name = "smmu_mdp_axi_clk", 1505c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1506c2526597SStephen Boyd .num_parents = 1, 1507c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1508c2526597SStephen Boyd .ops = &clk_branch2_ops, 1509c2526597SStephen Boyd }, 1510c2526597SStephen Boyd }, 1511c2526597SStephen Boyd }; 1512c2526597SStephen Boyd 1513c2526597SStephen Boyd static struct clk_branch mmagic_video_axi_clk = { 1514c2526597SStephen Boyd .halt_reg = 0x1194, 1515c2526597SStephen Boyd .clkr = { 1516c2526597SStephen Boyd .enable_reg = 0x1194, 1517c2526597SStephen Boyd .enable_mask = BIT(0), 1518c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1519c2526597SStephen Boyd .name = "mmagic_video_axi_clk", 1520c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1521c2526597SStephen Boyd .num_parents = 1, 15227705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1523c2526597SStephen Boyd .ops = &clk_branch2_ops, 1524c2526597SStephen Boyd }, 1525c2526597SStephen Boyd }, 1526c2526597SStephen Boyd }; 1527c2526597SStephen Boyd 1528c2526597SStephen Boyd static struct clk_branch mmagic_video_noc_cfg_ahb_clk = { 1529c2526597SStephen Boyd .halt_reg = 0x1198, 1530c2526597SStephen Boyd .clkr = { 1531c2526597SStephen Boyd .enable_reg = 0x1198, 1532c2526597SStephen Boyd .enable_mask = BIT(0), 1533c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1534c2526597SStephen Boyd .name = "mmagic_video_noc_cfg_ahb_clk", 1535c2526597SStephen Boyd .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1536c2526597SStephen Boyd .num_parents = 1, 15377705bb71SRajendra Nayak .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1538c2526597SStephen Boyd .ops = &clk_branch2_ops, 1539c2526597SStephen Boyd }, 1540c2526597SStephen Boyd }, 1541c2526597SStephen Boyd }; 1542c2526597SStephen Boyd 1543c2526597SStephen Boyd static struct clk_branch smmu_video_ahb_clk = { 1544c2526597SStephen Boyd .halt_reg = 0x1174, 1545c2526597SStephen Boyd .clkr = { 1546c2526597SStephen Boyd .enable_reg = 0x1174, 1547c2526597SStephen Boyd .enable_mask = BIT(0), 1548c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1549c2526597SStephen Boyd .name = "smmu_video_ahb_clk", 1550c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1551c2526597SStephen Boyd .num_parents = 1, 1552c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1553c2526597SStephen Boyd .ops = &clk_branch2_ops, 1554c2526597SStephen Boyd }, 1555c2526597SStephen Boyd }, 1556c2526597SStephen Boyd }; 1557c2526597SStephen Boyd 1558c2526597SStephen Boyd static struct clk_branch smmu_video_axi_clk = { 1559c2526597SStephen Boyd .halt_reg = 0x1178, 1560c2526597SStephen Boyd .clkr = { 1561c2526597SStephen Boyd .enable_reg = 0x1178, 1562c2526597SStephen Boyd .enable_mask = BIT(0), 1563c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1564c2526597SStephen Boyd .name = "smmu_video_axi_clk", 1565c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1566c2526597SStephen Boyd .num_parents = 1, 1567c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1568c2526597SStephen Boyd .ops = &clk_branch2_ops, 1569c2526597SStephen Boyd }, 1570c2526597SStephen Boyd }, 1571c2526597SStephen Boyd }; 1572c2526597SStephen Boyd 1573c2526597SStephen Boyd static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { 1574c2526597SStephen Boyd .halt_reg = 0x5298, 1575c2526597SStephen Boyd .clkr = { 1576c2526597SStephen Boyd .enable_reg = 0x5298, 1577c2526597SStephen Boyd .enable_mask = BIT(0), 1578c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1579c2526597SStephen Boyd .name = "mmagic_bimc_noc_cfg_ahb_clk", 1580c2526597SStephen Boyd .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1581c2526597SStephen Boyd .num_parents = 1, 1582c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1583c2526597SStephen Boyd .ops = &clk_branch2_ops, 1584c2526597SStephen Boyd }, 1585c2526597SStephen Boyd }, 1586c2526597SStephen Boyd }; 1587c2526597SStephen Boyd 1588c2526597SStephen Boyd static struct clk_branch gpu_gx_gfx3d_clk = { 1589c2526597SStephen Boyd .halt_reg = 0x4028, 1590c2526597SStephen Boyd .clkr = { 1591c2526597SStephen Boyd .enable_reg = 0x4028, 1592c2526597SStephen Boyd .enable_mask = BIT(0), 1593c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1594c2526597SStephen Boyd .name = "gpu_gx_gfx3d_clk", 1595c2526597SStephen Boyd .parent_names = (const char *[]){ "gfx3d_clk_src" }, 1596c2526597SStephen Boyd .num_parents = 1, 1597c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1598c2526597SStephen Boyd .ops = &clk_branch2_ops, 1599c2526597SStephen Boyd }, 1600c2526597SStephen Boyd }, 1601c2526597SStephen Boyd }; 1602c2526597SStephen Boyd 1603c2526597SStephen Boyd static struct clk_branch gpu_gx_rbbmtimer_clk = { 1604c2526597SStephen Boyd .halt_reg = 0x40b0, 1605c2526597SStephen Boyd .clkr = { 1606c2526597SStephen Boyd .enable_reg = 0x40b0, 1607c2526597SStephen Boyd .enable_mask = BIT(0), 1608c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1609c2526597SStephen Boyd .name = "gpu_gx_rbbmtimer_clk", 1610c2526597SStephen Boyd .parent_names = (const char *[]){ "rbbmtimer_clk_src" }, 1611c2526597SStephen Boyd .num_parents = 1, 1612c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1613c2526597SStephen Boyd .ops = &clk_branch2_ops, 1614c2526597SStephen Boyd }, 1615c2526597SStephen Boyd }, 1616c2526597SStephen Boyd }; 1617c2526597SStephen Boyd 1618c2526597SStephen Boyd static struct clk_branch gpu_ahb_clk = { 1619c2526597SStephen Boyd .halt_reg = 0x403c, 1620c2526597SStephen Boyd .clkr = { 1621c2526597SStephen Boyd .enable_reg = 0x403c, 1622c2526597SStephen Boyd .enable_mask = BIT(0), 1623c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1624c2526597SStephen Boyd .name = "gpu_ahb_clk", 1625c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1626c2526597SStephen Boyd .num_parents = 1, 1627c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1628c2526597SStephen Boyd .ops = &clk_branch2_ops, 1629c2526597SStephen Boyd }, 1630c2526597SStephen Boyd }, 1631c2526597SStephen Boyd }; 1632c2526597SStephen Boyd 1633c2526597SStephen Boyd static struct clk_branch gpu_aon_isense_clk = { 1634c2526597SStephen Boyd .halt_reg = 0x4044, 1635c2526597SStephen Boyd .clkr = { 1636c2526597SStephen Boyd .enable_reg = 0x4044, 1637c2526597SStephen Boyd .enable_mask = BIT(0), 1638c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1639c2526597SStephen Boyd .name = "gpu_aon_isense_clk", 1640c2526597SStephen Boyd .parent_names = (const char *[]){ "isense_clk_src" }, 1641c2526597SStephen Boyd .num_parents = 1, 1642c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1643c2526597SStephen Boyd .ops = &clk_branch2_ops, 1644c2526597SStephen Boyd }, 1645c2526597SStephen Boyd }, 1646c2526597SStephen Boyd }; 1647c2526597SStephen Boyd 1648c2526597SStephen Boyd static struct clk_branch vmem_maxi_clk = { 1649c2526597SStephen Boyd .halt_reg = 0x1204, 1650c2526597SStephen Boyd .clkr = { 1651c2526597SStephen Boyd .enable_reg = 0x1204, 1652c2526597SStephen Boyd .enable_mask = BIT(0), 1653c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1654c2526597SStephen Boyd .name = "vmem_maxi_clk", 1655c2526597SStephen Boyd .parent_names = (const char *[]){ "maxi_clk_src" }, 1656c2526597SStephen Boyd .num_parents = 1, 1657c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1658c2526597SStephen Boyd .ops = &clk_branch2_ops, 1659c2526597SStephen Boyd }, 1660c2526597SStephen Boyd }, 1661c2526597SStephen Boyd }; 1662c2526597SStephen Boyd 1663c2526597SStephen Boyd static struct clk_branch vmem_ahb_clk = { 1664c2526597SStephen Boyd .halt_reg = 0x1208, 1665c2526597SStephen Boyd .clkr = { 1666c2526597SStephen Boyd .enable_reg = 0x1208, 1667c2526597SStephen Boyd .enable_mask = BIT(0), 1668c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1669c2526597SStephen Boyd .name = "vmem_ahb_clk", 1670c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1671c2526597SStephen Boyd .num_parents = 1, 1672c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1673c2526597SStephen Boyd .ops = &clk_branch2_ops, 1674c2526597SStephen Boyd }, 1675c2526597SStephen Boyd }, 1676c2526597SStephen Boyd }; 1677c2526597SStephen Boyd 1678c2526597SStephen Boyd static struct clk_branch mmss_rbcpr_clk = { 1679c2526597SStephen Boyd .halt_reg = 0x4084, 1680c2526597SStephen Boyd .clkr = { 1681c2526597SStephen Boyd .enable_reg = 0x4084, 1682c2526597SStephen Boyd .enable_mask = BIT(0), 1683c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1684c2526597SStephen Boyd .name = "mmss_rbcpr_clk", 1685c2526597SStephen Boyd .parent_names = (const char *[]){ "rbcpr_clk_src" }, 1686c2526597SStephen Boyd .num_parents = 1, 1687c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1688c2526597SStephen Boyd .ops = &clk_branch2_ops, 1689c2526597SStephen Boyd }, 1690c2526597SStephen Boyd }, 1691c2526597SStephen Boyd }; 1692c2526597SStephen Boyd 1693c2526597SStephen Boyd static struct clk_branch mmss_rbcpr_ahb_clk = { 1694c2526597SStephen Boyd .halt_reg = 0x4088, 1695c2526597SStephen Boyd .clkr = { 1696c2526597SStephen Boyd .enable_reg = 0x4088, 1697c2526597SStephen Boyd .enable_mask = BIT(0), 1698c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1699c2526597SStephen Boyd .name = "mmss_rbcpr_ahb_clk", 1700c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1701c2526597SStephen Boyd .num_parents = 1, 1702c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1703c2526597SStephen Boyd .ops = &clk_branch2_ops, 1704c2526597SStephen Boyd }, 1705c2526597SStephen Boyd }, 1706c2526597SStephen Boyd }; 1707c2526597SStephen Boyd 1708c2526597SStephen Boyd static struct clk_branch video_core_clk = { 1709c2526597SStephen Boyd .halt_reg = 0x1028, 1710c2526597SStephen Boyd .clkr = { 1711c2526597SStephen Boyd .enable_reg = 0x1028, 1712c2526597SStephen Boyd .enable_mask = BIT(0), 1713c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1714c2526597SStephen Boyd .name = "video_core_clk", 1715c2526597SStephen Boyd .parent_names = (const char *[]){ "video_core_clk_src" }, 1716c2526597SStephen Boyd .num_parents = 1, 1717c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1718c2526597SStephen Boyd .ops = &clk_branch2_ops, 1719c2526597SStephen Boyd }, 1720c2526597SStephen Boyd }, 1721c2526597SStephen Boyd }; 1722c2526597SStephen Boyd 1723c2526597SStephen Boyd static struct clk_branch video_axi_clk = { 1724c2526597SStephen Boyd .halt_reg = 0x1034, 1725c2526597SStephen Boyd .clkr = { 1726c2526597SStephen Boyd .enable_reg = 0x1034, 1727c2526597SStephen Boyd .enable_mask = BIT(0), 1728c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1729c2526597SStephen Boyd .name = "video_axi_clk", 1730c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1731c2526597SStephen Boyd .num_parents = 1, 1732c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1733c2526597SStephen Boyd .ops = &clk_branch2_ops, 1734c2526597SStephen Boyd }, 1735c2526597SStephen Boyd }, 1736c2526597SStephen Boyd }; 1737c2526597SStephen Boyd 1738c2526597SStephen Boyd static struct clk_branch video_maxi_clk = { 1739c2526597SStephen Boyd .halt_reg = 0x1038, 1740c2526597SStephen Boyd .clkr = { 1741c2526597SStephen Boyd .enable_reg = 0x1038, 1742c2526597SStephen Boyd .enable_mask = BIT(0), 1743c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1744c2526597SStephen Boyd .name = "video_maxi_clk", 1745c2526597SStephen Boyd .parent_names = (const char *[]){ "maxi_clk_src" }, 1746c2526597SStephen Boyd .num_parents = 1, 1747c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1748c2526597SStephen Boyd .ops = &clk_branch2_ops, 1749c2526597SStephen Boyd }, 1750c2526597SStephen Boyd }, 1751c2526597SStephen Boyd }; 1752c2526597SStephen Boyd 1753c2526597SStephen Boyd static struct clk_branch video_ahb_clk = { 1754c2526597SStephen Boyd .halt_reg = 0x1030, 1755c2526597SStephen Boyd .clkr = { 1756c2526597SStephen Boyd .enable_reg = 0x1030, 1757c2526597SStephen Boyd .enable_mask = BIT(0), 1758c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1759c2526597SStephen Boyd .name = "video_ahb_clk", 1760c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1761c2526597SStephen Boyd .num_parents = 1, 1762c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1763c2526597SStephen Boyd .ops = &clk_branch2_ops, 1764c2526597SStephen Boyd }, 1765c2526597SStephen Boyd }, 1766c2526597SStephen Boyd }; 1767c2526597SStephen Boyd 1768c2526597SStephen Boyd static struct clk_branch video_subcore0_clk = { 1769c2526597SStephen Boyd .halt_reg = 0x1048, 1770c2526597SStephen Boyd .clkr = { 1771c2526597SStephen Boyd .enable_reg = 0x1048, 1772c2526597SStephen Boyd .enable_mask = BIT(0), 1773c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1774c2526597SStephen Boyd .name = "video_subcore0_clk", 1775c2526597SStephen Boyd .parent_names = (const char *[]){ "video_subcore0_clk_src" }, 1776c2526597SStephen Boyd .num_parents = 1, 1777c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1778c2526597SStephen Boyd .ops = &clk_branch2_ops, 1779c2526597SStephen Boyd }, 1780c2526597SStephen Boyd }, 1781c2526597SStephen Boyd }; 1782c2526597SStephen Boyd 1783c2526597SStephen Boyd static struct clk_branch video_subcore1_clk = { 1784c2526597SStephen Boyd .halt_reg = 0x104c, 1785c2526597SStephen Boyd .clkr = { 1786c2526597SStephen Boyd .enable_reg = 0x104c, 1787c2526597SStephen Boyd .enable_mask = BIT(0), 1788c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1789c2526597SStephen Boyd .name = "video_subcore1_clk", 1790c2526597SStephen Boyd .parent_names = (const char *[]){ "video_subcore1_clk_src" }, 1791c2526597SStephen Boyd .num_parents = 1, 1792c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1793c2526597SStephen Boyd .ops = &clk_branch2_ops, 1794c2526597SStephen Boyd }, 1795c2526597SStephen Boyd }, 1796c2526597SStephen Boyd }; 1797c2526597SStephen Boyd 1798c2526597SStephen Boyd static struct clk_branch mdss_ahb_clk = { 1799c2526597SStephen Boyd .halt_reg = 0x2308, 1800c2526597SStephen Boyd .clkr = { 1801c2526597SStephen Boyd .enable_reg = 0x2308, 1802c2526597SStephen Boyd .enable_mask = BIT(0), 1803c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1804c2526597SStephen Boyd .name = "mdss_ahb_clk", 1805c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1806c2526597SStephen Boyd .num_parents = 1, 1807c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1808c2526597SStephen Boyd .ops = &clk_branch2_ops, 1809c2526597SStephen Boyd }, 1810c2526597SStephen Boyd }, 1811c2526597SStephen Boyd }; 1812c2526597SStephen Boyd 1813c2526597SStephen Boyd static struct clk_branch mdss_hdmi_ahb_clk = { 1814c2526597SStephen Boyd .halt_reg = 0x230c, 1815c2526597SStephen Boyd .clkr = { 1816c2526597SStephen Boyd .enable_reg = 0x230c, 1817c2526597SStephen Boyd .enable_mask = BIT(0), 1818c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1819c2526597SStephen Boyd .name = "mdss_hdmi_ahb_clk", 1820c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1821c2526597SStephen Boyd .num_parents = 1, 1822c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1823c2526597SStephen Boyd .ops = &clk_branch2_ops, 1824c2526597SStephen Boyd }, 1825c2526597SStephen Boyd }, 1826c2526597SStephen Boyd }; 1827c2526597SStephen Boyd 1828c2526597SStephen Boyd static struct clk_branch mdss_axi_clk = { 1829c2526597SStephen Boyd .halt_reg = 0x2310, 1830c2526597SStephen Boyd .clkr = { 1831c2526597SStephen Boyd .enable_reg = 0x2310, 1832c2526597SStephen Boyd .enable_mask = BIT(0), 1833c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1834c2526597SStephen Boyd .name = "mdss_axi_clk", 1835c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1836c2526597SStephen Boyd .num_parents = 1, 1837c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1838c2526597SStephen Boyd .ops = &clk_branch2_ops, 1839c2526597SStephen Boyd }, 1840c2526597SStephen Boyd }, 1841c2526597SStephen Boyd }; 1842c2526597SStephen Boyd 1843c2526597SStephen Boyd static struct clk_branch mdss_pclk0_clk = { 1844c2526597SStephen Boyd .halt_reg = 0x2314, 1845c2526597SStephen Boyd .clkr = { 1846c2526597SStephen Boyd .enable_reg = 0x2314, 1847c2526597SStephen Boyd .enable_mask = BIT(0), 1848c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1849c2526597SStephen Boyd .name = "mdss_pclk0_clk", 1850c2526597SStephen Boyd .parent_names = (const char *[]){ "pclk0_clk_src" }, 1851c2526597SStephen Boyd .num_parents = 1, 1852c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1853c2526597SStephen Boyd .ops = &clk_branch2_ops, 1854c2526597SStephen Boyd }, 1855c2526597SStephen Boyd }, 1856c2526597SStephen Boyd }; 1857c2526597SStephen Boyd 1858c2526597SStephen Boyd static struct clk_branch mdss_pclk1_clk = { 1859c2526597SStephen Boyd .halt_reg = 0x2318, 1860c2526597SStephen Boyd .clkr = { 1861c2526597SStephen Boyd .enable_reg = 0x2318, 1862c2526597SStephen Boyd .enable_mask = BIT(0), 1863c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1864c2526597SStephen Boyd .name = "mdss_pclk1_clk", 1865c2526597SStephen Boyd .parent_names = (const char *[]){ "pclk1_clk_src" }, 1866c2526597SStephen Boyd .num_parents = 1, 1867c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1868c2526597SStephen Boyd .ops = &clk_branch2_ops, 1869c2526597SStephen Boyd }, 1870c2526597SStephen Boyd }, 1871c2526597SStephen Boyd }; 1872c2526597SStephen Boyd 1873c2526597SStephen Boyd static struct clk_branch mdss_mdp_clk = { 1874c2526597SStephen Boyd .halt_reg = 0x231c, 1875c2526597SStephen Boyd .clkr = { 1876c2526597SStephen Boyd .enable_reg = 0x231c, 1877c2526597SStephen Boyd .enable_mask = BIT(0), 1878c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1879c2526597SStephen Boyd .name = "mdss_mdp_clk", 1880c2526597SStephen Boyd .parent_names = (const char *[]){ "mdp_clk_src" }, 1881c2526597SStephen Boyd .num_parents = 1, 1882c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1883c2526597SStephen Boyd .ops = &clk_branch2_ops, 1884c2526597SStephen Boyd }, 1885c2526597SStephen Boyd }, 1886c2526597SStephen Boyd }; 1887c2526597SStephen Boyd 1888c2526597SStephen Boyd static struct clk_branch mdss_extpclk_clk = { 1889c2526597SStephen Boyd .halt_reg = 0x2324, 1890c2526597SStephen Boyd .clkr = { 1891c2526597SStephen Boyd .enable_reg = 0x2324, 1892c2526597SStephen Boyd .enable_mask = BIT(0), 1893c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1894c2526597SStephen Boyd .name = "mdss_extpclk_clk", 1895c2526597SStephen Boyd .parent_names = (const char *[]){ "extpclk_clk_src" }, 1896c2526597SStephen Boyd .num_parents = 1, 1897c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1898c2526597SStephen Boyd .ops = &clk_branch2_ops, 1899c2526597SStephen Boyd }, 1900c2526597SStephen Boyd }, 1901c2526597SStephen Boyd }; 1902c2526597SStephen Boyd 1903c2526597SStephen Boyd static struct clk_branch mdss_vsync_clk = { 1904c2526597SStephen Boyd .halt_reg = 0x2328, 1905c2526597SStephen Boyd .clkr = { 1906c2526597SStephen Boyd .enable_reg = 0x2328, 1907c2526597SStephen Boyd .enable_mask = BIT(0), 1908c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1909c2526597SStephen Boyd .name = "mdss_vsync_clk", 1910c2526597SStephen Boyd .parent_names = (const char *[]){ "vsync_clk_src" }, 1911c2526597SStephen Boyd .num_parents = 1, 1912c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1913c2526597SStephen Boyd .ops = &clk_branch2_ops, 1914c2526597SStephen Boyd }, 1915c2526597SStephen Boyd }, 1916c2526597SStephen Boyd }; 1917c2526597SStephen Boyd 1918c2526597SStephen Boyd static struct clk_branch mdss_hdmi_clk = { 1919c2526597SStephen Boyd .halt_reg = 0x2338, 1920c2526597SStephen Boyd .clkr = { 1921c2526597SStephen Boyd .enable_reg = 0x2338, 1922c2526597SStephen Boyd .enable_mask = BIT(0), 1923c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1924c2526597SStephen Boyd .name = "mdss_hdmi_clk", 1925c2526597SStephen Boyd .parent_names = (const char *[]){ "hdmi_clk_src" }, 1926c2526597SStephen Boyd .num_parents = 1, 1927c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1928c2526597SStephen Boyd .ops = &clk_branch2_ops, 1929c2526597SStephen Boyd }, 1930c2526597SStephen Boyd }, 1931c2526597SStephen Boyd }; 1932c2526597SStephen Boyd 1933c2526597SStephen Boyd static struct clk_branch mdss_byte0_clk = { 1934c2526597SStephen Boyd .halt_reg = 0x233c, 1935c2526597SStephen Boyd .clkr = { 1936c2526597SStephen Boyd .enable_reg = 0x233c, 1937c2526597SStephen Boyd .enable_mask = BIT(0), 1938c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1939c2526597SStephen Boyd .name = "mdss_byte0_clk", 1940c2526597SStephen Boyd .parent_names = (const char *[]){ "byte0_clk_src" }, 1941c2526597SStephen Boyd .num_parents = 1, 1942c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1943c2526597SStephen Boyd .ops = &clk_branch2_ops, 1944c2526597SStephen Boyd }, 1945c2526597SStephen Boyd }, 1946c2526597SStephen Boyd }; 1947c2526597SStephen Boyd 1948c2526597SStephen Boyd static struct clk_branch mdss_byte1_clk = { 1949c2526597SStephen Boyd .halt_reg = 0x2340, 1950c2526597SStephen Boyd .clkr = { 1951c2526597SStephen Boyd .enable_reg = 0x2340, 1952c2526597SStephen Boyd .enable_mask = BIT(0), 1953c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1954c2526597SStephen Boyd .name = "mdss_byte1_clk", 1955c2526597SStephen Boyd .parent_names = (const char *[]){ "byte1_clk_src" }, 1956c2526597SStephen Boyd .num_parents = 1, 1957c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1958c2526597SStephen Boyd .ops = &clk_branch2_ops, 1959c2526597SStephen Boyd }, 1960c2526597SStephen Boyd }, 1961c2526597SStephen Boyd }; 1962c2526597SStephen Boyd 1963c2526597SStephen Boyd static struct clk_branch mdss_esc0_clk = { 1964c2526597SStephen Boyd .halt_reg = 0x2344, 1965c2526597SStephen Boyd .clkr = { 1966c2526597SStephen Boyd .enable_reg = 0x2344, 1967c2526597SStephen Boyd .enable_mask = BIT(0), 1968c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1969c2526597SStephen Boyd .name = "mdss_esc0_clk", 1970c2526597SStephen Boyd .parent_names = (const char *[]){ "esc0_clk_src" }, 1971c2526597SStephen Boyd .num_parents = 1, 1972c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1973c2526597SStephen Boyd .ops = &clk_branch2_ops, 1974c2526597SStephen Boyd }, 1975c2526597SStephen Boyd }, 1976c2526597SStephen Boyd }; 1977c2526597SStephen Boyd 1978c2526597SStephen Boyd static struct clk_branch mdss_esc1_clk = { 1979c2526597SStephen Boyd .halt_reg = 0x2348, 1980c2526597SStephen Boyd .clkr = { 1981c2526597SStephen Boyd .enable_reg = 0x2348, 1982c2526597SStephen Boyd .enable_mask = BIT(0), 1983c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1984c2526597SStephen Boyd .name = "mdss_esc1_clk", 1985c2526597SStephen Boyd .parent_names = (const char *[]){ "esc1_clk_src" }, 1986c2526597SStephen Boyd .num_parents = 1, 1987c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1988c2526597SStephen Boyd .ops = &clk_branch2_ops, 1989c2526597SStephen Boyd }, 1990c2526597SStephen Boyd }, 1991c2526597SStephen Boyd }; 1992c2526597SStephen Boyd 1993c2526597SStephen Boyd static struct clk_branch camss_top_ahb_clk = { 1994c2526597SStephen Boyd .halt_reg = 0x3484, 1995c2526597SStephen Boyd .clkr = { 1996c2526597SStephen Boyd .enable_reg = 0x3484, 1997c2526597SStephen Boyd .enable_mask = BIT(0), 1998c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1999c2526597SStephen Boyd .name = "camss_top_ahb_clk", 2000c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2001c2526597SStephen Boyd .num_parents = 1, 2002c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2003c2526597SStephen Boyd .ops = &clk_branch2_ops, 2004c2526597SStephen Boyd }, 2005c2526597SStephen Boyd }, 2006c2526597SStephen Boyd }; 2007c2526597SStephen Boyd 2008c2526597SStephen Boyd static struct clk_branch camss_ahb_clk = { 2009c2526597SStephen Boyd .halt_reg = 0x348c, 2010c2526597SStephen Boyd .clkr = { 2011c2526597SStephen Boyd .enable_reg = 0x348c, 2012c2526597SStephen Boyd .enable_mask = BIT(0), 2013c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2014c2526597SStephen Boyd .name = "camss_ahb_clk", 2015c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2016c2526597SStephen Boyd .num_parents = 1, 2017c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2018c2526597SStephen Boyd .ops = &clk_branch2_ops, 2019c2526597SStephen Boyd }, 2020c2526597SStephen Boyd }, 2021c2526597SStephen Boyd }; 2022c2526597SStephen Boyd 2023c2526597SStephen Boyd static struct clk_branch camss_micro_ahb_clk = { 2024c2526597SStephen Boyd .halt_reg = 0x3494, 2025c2526597SStephen Boyd .clkr = { 2026c2526597SStephen Boyd .enable_reg = 0x3494, 2027c2526597SStephen Boyd .enable_mask = BIT(0), 2028c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2029c2526597SStephen Boyd .name = "camss_micro_ahb_clk", 2030c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2031c2526597SStephen Boyd .num_parents = 1, 2032c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2033c2526597SStephen Boyd .ops = &clk_branch2_ops, 2034c2526597SStephen Boyd }, 2035c2526597SStephen Boyd }, 2036c2526597SStephen Boyd }; 2037c2526597SStephen Boyd 2038c2526597SStephen Boyd static struct clk_branch camss_gp0_clk = { 2039c2526597SStephen Boyd .halt_reg = 0x3444, 2040c2526597SStephen Boyd .clkr = { 2041c2526597SStephen Boyd .enable_reg = 0x3444, 2042c2526597SStephen Boyd .enable_mask = BIT(0), 2043c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2044c2526597SStephen Boyd .name = "camss_gp0_clk", 2045c2526597SStephen Boyd .parent_names = (const char *[]){ "camss_gp0_clk_src" }, 2046c2526597SStephen Boyd .num_parents = 1, 2047c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2048c2526597SStephen Boyd .ops = &clk_branch2_ops, 2049c2526597SStephen Boyd }, 2050c2526597SStephen Boyd }, 2051c2526597SStephen Boyd }; 2052c2526597SStephen Boyd 2053c2526597SStephen Boyd static struct clk_branch camss_gp1_clk = { 2054c2526597SStephen Boyd .halt_reg = 0x3474, 2055c2526597SStephen Boyd .clkr = { 2056c2526597SStephen Boyd .enable_reg = 0x3474, 2057c2526597SStephen Boyd .enable_mask = BIT(0), 2058c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2059c2526597SStephen Boyd .name = "camss_gp1_clk", 2060c2526597SStephen Boyd .parent_names = (const char *[]){ "camss_gp1_clk_src" }, 2061c2526597SStephen Boyd .num_parents = 1, 2062c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2063c2526597SStephen Boyd .ops = &clk_branch2_ops, 2064c2526597SStephen Boyd }, 2065c2526597SStephen Boyd }, 2066c2526597SStephen Boyd }; 2067c2526597SStephen Boyd 2068c2526597SStephen Boyd static struct clk_branch camss_mclk0_clk = { 2069c2526597SStephen Boyd .halt_reg = 0x3384, 2070c2526597SStephen Boyd .clkr = { 2071c2526597SStephen Boyd .enable_reg = 0x3384, 2072c2526597SStephen Boyd .enable_mask = BIT(0), 2073c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2074c2526597SStephen Boyd .name = "camss_mclk0_clk", 2075c2526597SStephen Boyd .parent_names = (const char *[]){ "mclk0_clk_src" }, 2076c2526597SStephen Boyd .num_parents = 1, 2077c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2078c2526597SStephen Boyd .ops = &clk_branch2_ops, 2079c2526597SStephen Boyd }, 2080c2526597SStephen Boyd }, 2081c2526597SStephen Boyd }; 2082c2526597SStephen Boyd 2083c2526597SStephen Boyd static struct clk_branch camss_mclk1_clk = { 2084c2526597SStephen Boyd .halt_reg = 0x33b4, 2085c2526597SStephen Boyd .clkr = { 2086c2526597SStephen Boyd .enable_reg = 0x33b4, 2087c2526597SStephen Boyd .enable_mask = BIT(0), 2088c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2089c2526597SStephen Boyd .name = "camss_mclk1_clk", 2090c2526597SStephen Boyd .parent_names = (const char *[]){ "mclk1_clk_src" }, 2091c2526597SStephen Boyd .num_parents = 1, 2092c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2093c2526597SStephen Boyd .ops = &clk_branch2_ops, 2094c2526597SStephen Boyd }, 2095c2526597SStephen Boyd }, 2096c2526597SStephen Boyd }; 2097c2526597SStephen Boyd 2098c2526597SStephen Boyd static struct clk_branch camss_mclk2_clk = { 2099c2526597SStephen Boyd .halt_reg = 0x33e4, 2100c2526597SStephen Boyd .clkr = { 2101c2526597SStephen Boyd .enable_reg = 0x33e4, 2102c2526597SStephen Boyd .enable_mask = BIT(0), 2103c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2104c2526597SStephen Boyd .name = "camss_mclk2_clk", 2105c2526597SStephen Boyd .parent_names = (const char *[]){ "mclk2_clk_src" }, 2106c2526597SStephen Boyd .num_parents = 1, 2107c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2108c2526597SStephen Boyd .ops = &clk_branch2_ops, 2109c2526597SStephen Boyd }, 2110c2526597SStephen Boyd }, 2111c2526597SStephen Boyd }; 2112c2526597SStephen Boyd 2113c2526597SStephen Boyd static struct clk_branch camss_mclk3_clk = { 2114c2526597SStephen Boyd .halt_reg = 0x3414, 2115c2526597SStephen Boyd .clkr = { 2116c2526597SStephen Boyd .enable_reg = 0x3414, 2117c2526597SStephen Boyd .enable_mask = BIT(0), 2118c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2119c2526597SStephen Boyd .name = "camss_mclk3_clk", 2120c2526597SStephen Boyd .parent_names = (const char *[]){ "mclk3_clk_src" }, 2121c2526597SStephen Boyd .num_parents = 1, 2122c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2123c2526597SStephen Boyd .ops = &clk_branch2_ops, 2124c2526597SStephen Boyd }, 2125c2526597SStephen Boyd }, 2126c2526597SStephen Boyd }; 2127c2526597SStephen Boyd 2128c2526597SStephen Boyd static struct clk_branch camss_cci_clk = { 2129c2526597SStephen Boyd .halt_reg = 0x3344, 2130c2526597SStephen Boyd .clkr = { 2131c2526597SStephen Boyd .enable_reg = 0x3344, 2132c2526597SStephen Boyd .enable_mask = BIT(0), 2133c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2134c2526597SStephen Boyd .name = "camss_cci_clk", 2135c2526597SStephen Boyd .parent_names = (const char *[]){ "cci_clk_src" }, 2136c2526597SStephen Boyd .num_parents = 1, 2137c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2138c2526597SStephen Boyd .ops = &clk_branch2_ops, 2139c2526597SStephen Boyd }, 2140c2526597SStephen Boyd }, 2141c2526597SStephen Boyd }; 2142c2526597SStephen Boyd 2143c2526597SStephen Boyd static struct clk_branch camss_cci_ahb_clk = { 2144c2526597SStephen Boyd .halt_reg = 0x3348, 2145c2526597SStephen Boyd .clkr = { 2146c2526597SStephen Boyd .enable_reg = 0x3348, 2147c2526597SStephen Boyd .enable_mask = BIT(0), 2148c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2149c2526597SStephen Boyd .name = "camss_cci_ahb_clk", 2150c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2151c2526597SStephen Boyd .num_parents = 1, 2152c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2153c2526597SStephen Boyd .ops = &clk_branch2_ops, 2154c2526597SStephen Boyd }, 2155c2526597SStephen Boyd }, 2156c2526597SStephen Boyd }; 2157c2526597SStephen Boyd 2158c2526597SStephen Boyd static struct clk_branch camss_csi0phytimer_clk = { 2159c2526597SStephen Boyd .halt_reg = 0x3024, 2160c2526597SStephen Boyd .clkr = { 2161c2526597SStephen Boyd .enable_reg = 0x3024, 2162c2526597SStephen Boyd .enable_mask = BIT(0), 2163c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2164c2526597SStephen Boyd .name = "camss_csi0phytimer_clk", 2165c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0phytimer_clk_src" }, 2166c2526597SStephen Boyd .num_parents = 1, 2167c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2168c2526597SStephen Boyd .ops = &clk_branch2_ops, 2169c2526597SStephen Boyd }, 2170c2526597SStephen Boyd }, 2171c2526597SStephen Boyd }; 2172c2526597SStephen Boyd 2173c2526597SStephen Boyd static struct clk_branch camss_csi1phytimer_clk = { 2174c2526597SStephen Boyd .halt_reg = 0x3054, 2175c2526597SStephen Boyd .clkr = { 2176c2526597SStephen Boyd .enable_reg = 0x3054, 2177c2526597SStephen Boyd .enable_mask = BIT(0), 2178c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2179c2526597SStephen Boyd .name = "camss_csi1phytimer_clk", 2180c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1phytimer_clk_src" }, 2181c2526597SStephen Boyd .num_parents = 1, 2182c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2183c2526597SStephen Boyd .ops = &clk_branch2_ops, 2184c2526597SStephen Boyd }, 2185c2526597SStephen Boyd }, 2186c2526597SStephen Boyd }; 2187c2526597SStephen Boyd 2188c2526597SStephen Boyd static struct clk_branch camss_csi2phytimer_clk = { 2189c2526597SStephen Boyd .halt_reg = 0x3084, 2190c2526597SStephen Boyd .clkr = { 2191c2526597SStephen Boyd .enable_reg = 0x3084, 2192c2526597SStephen Boyd .enable_mask = BIT(0), 2193c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2194c2526597SStephen Boyd .name = "camss_csi2phytimer_clk", 2195c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2phytimer_clk_src" }, 2196c2526597SStephen Boyd .num_parents = 1, 2197c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2198c2526597SStephen Boyd .ops = &clk_branch2_ops, 2199c2526597SStephen Boyd }, 2200c2526597SStephen Boyd }, 2201c2526597SStephen Boyd }; 2202c2526597SStephen Boyd 2203c2526597SStephen Boyd static struct clk_branch camss_csiphy0_3p_clk = { 2204c2526597SStephen Boyd .halt_reg = 0x3234, 2205c2526597SStephen Boyd .clkr = { 2206c2526597SStephen Boyd .enable_reg = 0x3234, 2207c2526597SStephen Boyd .enable_mask = BIT(0), 2208c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2209c2526597SStephen Boyd .name = "camss_csiphy0_3p_clk", 2210c2526597SStephen Boyd .parent_names = (const char *[]){ "csiphy0_3p_clk_src" }, 2211c2526597SStephen Boyd .num_parents = 1, 2212c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2213c2526597SStephen Boyd .ops = &clk_branch2_ops, 2214c2526597SStephen Boyd }, 2215c2526597SStephen Boyd }, 2216c2526597SStephen Boyd }; 2217c2526597SStephen Boyd 2218c2526597SStephen Boyd static struct clk_branch camss_csiphy1_3p_clk = { 2219c2526597SStephen Boyd .halt_reg = 0x3254, 2220c2526597SStephen Boyd .clkr = { 2221c2526597SStephen Boyd .enable_reg = 0x3254, 2222c2526597SStephen Boyd .enable_mask = BIT(0), 2223c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2224c2526597SStephen Boyd .name = "camss_csiphy1_3p_clk", 2225c2526597SStephen Boyd .parent_names = (const char *[]){ "csiphy1_3p_clk_src" }, 2226c2526597SStephen Boyd .num_parents = 1, 2227c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2228c2526597SStephen Boyd .ops = &clk_branch2_ops, 2229c2526597SStephen Boyd }, 2230c2526597SStephen Boyd }, 2231c2526597SStephen Boyd }; 2232c2526597SStephen Boyd 2233c2526597SStephen Boyd static struct clk_branch camss_csiphy2_3p_clk = { 2234c2526597SStephen Boyd .halt_reg = 0x3274, 2235c2526597SStephen Boyd .clkr = { 2236c2526597SStephen Boyd .enable_reg = 0x3274, 2237c2526597SStephen Boyd .enable_mask = BIT(0), 2238c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2239c2526597SStephen Boyd .name = "camss_csiphy2_3p_clk", 2240c2526597SStephen Boyd .parent_names = (const char *[]){ "csiphy2_3p_clk_src" }, 2241c2526597SStephen Boyd .num_parents = 1, 2242c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2243c2526597SStephen Boyd .ops = &clk_branch2_ops, 2244c2526597SStephen Boyd }, 2245c2526597SStephen Boyd }, 2246c2526597SStephen Boyd }; 2247c2526597SStephen Boyd 2248c2526597SStephen Boyd static struct clk_branch camss_jpeg0_clk = { 2249c2526597SStephen Boyd .halt_reg = 0x35a8, 2250c2526597SStephen Boyd .clkr = { 2251c2526597SStephen Boyd .enable_reg = 0x35a8, 2252c2526597SStephen Boyd .enable_mask = BIT(0), 2253c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2254c2526597SStephen Boyd .name = "camss_jpeg0_clk", 2255c2526597SStephen Boyd .parent_names = (const char *[]){ "jpeg0_clk_src" }, 2256c2526597SStephen Boyd .num_parents = 1, 2257c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2258c2526597SStephen Boyd .ops = &clk_branch2_ops, 2259c2526597SStephen Boyd }, 2260c2526597SStephen Boyd }, 2261c2526597SStephen Boyd }; 2262c2526597SStephen Boyd 2263c2526597SStephen Boyd static struct clk_branch camss_jpeg2_clk = { 2264c2526597SStephen Boyd .halt_reg = 0x35b0, 2265c2526597SStephen Boyd .clkr = { 2266c2526597SStephen Boyd .enable_reg = 0x35b0, 2267c2526597SStephen Boyd .enable_mask = BIT(0), 2268c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2269c2526597SStephen Boyd .name = "camss_jpeg2_clk", 2270c2526597SStephen Boyd .parent_names = (const char *[]){ "jpeg2_clk_src" }, 2271c2526597SStephen Boyd .num_parents = 1, 2272c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2273c2526597SStephen Boyd .ops = &clk_branch2_ops, 2274c2526597SStephen Boyd }, 2275c2526597SStephen Boyd }, 2276c2526597SStephen Boyd }; 2277c2526597SStephen Boyd 2278c2526597SStephen Boyd static struct clk_branch camss_jpeg_dma_clk = { 2279c2526597SStephen Boyd .halt_reg = 0x35c0, 2280c2526597SStephen Boyd .clkr = { 2281c2526597SStephen Boyd .enable_reg = 0x35c0, 2282c2526597SStephen Boyd .enable_mask = BIT(0), 2283c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2284c2526597SStephen Boyd .name = "camss_jpeg_dma_clk", 2285c2526597SStephen Boyd .parent_names = (const char *[]){ "jpeg_dma_clk_src" }, 2286c2526597SStephen Boyd .num_parents = 1, 2287c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2288c2526597SStephen Boyd .ops = &clk_branch2_ops, 2289c2526597SStephen Boyd }, 2290c2526597SStephen Boyd }, 2291c2526597SStephen Boyd }; 2292c2526597SStephen Boyd 2293c2526597SStephen Boyd static struct clk_branch camss_jpeg_ahb_clk = { 2294c2526597SStephen Boyd .halt_reg = 0x35b4, 2295c2526597SStephen Boyd .clkr = { 2296c2526597SStephen Boyd .enable_reg = 0x35b4, 2297c2526597SStephen Boyd .enable_mask = BIT(0), 2298c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2299c2526597SStephen Boyd .name = "camss_jpeg_ahb_clk", 2300c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2301c2526597SStephen Boyd .num_parents = 1, 2302c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2303c2526597SStephen Boyd .ops = &clk_branch2_ops, 2304c2526597SStephen Boyd }, 2305c2526597SStephen Boyd }, 2306c2526597SStephen Boyd }; 2307c2526597SStephen Boyd 2308c2526597SStephen Boyd static struct clk_branch camss_jpeg_axi_clk = { 2309c2526597SStephen Boyd .halt_reg = 0x35b8, 2310c2526597SStephen Boyd .clkr = { 2311c2526597SStephen Boyd .enable_reg = 0x35b8, 2312c2526597SStephen Boyd .enable_mask = BIT(0), 2313c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2314c2526597SStephen Boyd .name = "camss_jpeg_axi_clk", 2315c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 2316c2526597SStephen Boyd .num_parents = 1, 2317c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2318c2526597SStephen Boyd .ops = &clk_branch2_ops, 2319c2526597SStephen Boyd }, 2320c2526597SStephen Boyd }, 2321c2526597SStephen Boyd }; 2322c2526597SStephen Boyd 2323c2526597SStephen Boyd static struct clk_branch camss_vfe_ahb_clk = { 2324c2526597SStephen Boyd .halt_reg = 0x36b8, 2325c2526597SStephen Boyd .clkr = { 2326c2526597SStephen Boyd .enable_reg = 0x36b8, 2327c2526597SStephen Boyd .enable_mask = BIT(0), 2328c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2329c2526597SStephen Boyd .name = "camss_vfe_ahb_clk", 2330c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2331c2526597SStephen Boyd .num_parents = 1, 2332c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2333c2526597SStephen Boyd .ops = &clk_branch2_ops, 2334c2526597SStephen Boyd }, 2335c2526597SStephen Boyd }, 2336c2526597SStephen Boyd }; 2337c2526597SStephen Boyd 2338c2526597SStephen Boyd static struct clk_branch camss_vfe_axi_clk = { 2339c2526597SStephen Boyd .halt_reg = 0x36bc, 2340c2526597SStephen Boyd .clkr = { 2341c2526597SStephen Boyd .enable_reg = 0x36bc, 2342c2526597SStephen Boyd .enable_mask = BIT(0), 2343c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2344c2526597SStephen Boyd .name = "camss_vfe_axi_clk", 2345c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 2346c2526597SStephen Boyd .num_parents = 1, 2347c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2348c2526597SStephen Boyd .ops = &clk_branch2_ops, 2349c2526597SStephen Boyd }, 2350c2526597SStephen Boyd }, 2351c2526597SStephen Boyd }; 2352c2526597SStephen Boyd 2353c2526597SStephen Boyd static struct clk_branch camss_vfe0_clk = { 2354c2526597SStephen Boyd .halt_reg = 0x36a8, 2355c2526597SStephen Boyd .clkr = { 2356c2526597SStephen Boyd .enable_reg = 0x36a8, 2357c2526597SStephen Boyd .enable_mask = BIT(0), 2358c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2359c2526597SStephen Boyd .name = "camss_vfe0_clk", 2360c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe0_clk_src" }, 2361c2526597SStephen Boyd .num_parents = 1, 2362c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2363c2526597SStephen Boyd .ops = &clk_branch2_ops, 2364c2526597SStephen Boyd }, 2365c2526597SStephen Boyd }, 2366c2526597SStephen Boyd }; 2367c2526597SStephen Boyd 2368c2526597SStephen Boyd static struct clk_branch camss_vfe0_stream_clk = { 2369c2526597SStephen Boyd .halt_reg = 0x3720, 2370c2526597SStephen Boyd .clkr = { 2371c2526597SStephen Boyd .enable_reg = 0x3720, 2372c2526597SStephen Boyd .enable_mask = BIT(0), 2373c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2374c2526597SStephen Boyd .name = "camss_vfe0_stream_clk", 2375c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe0_clk_src" }, 2376c2526597SStephen Boyd .num_parents = 1, 2377c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2378c2526597SStephen Boyd .ops = &clk_branch2_ops, 2379c2526597SStephen Boyd }, 2380c2526597SStephen Boyd }, 2381c2526597SStephen Boyd }; 2382c2526597SStephen Boyd 2383c2526597SStephen Boyd static struct clk_branch camss_vfe0_ahb_clk = { 2384c2526597SStephen Boyd .halt_reg = 0x3668, 2385c2526597SStephen Boyd .clkr = { 2386c2526597SStephen Boyd .enable_reg = 0x3668, 2387c2526597SStephen Boyd .enable_mask = BIT(0), 2388c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2389c2526597SStephen Boyd .name = "camss_vfe0_ahb_clk", 2390c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2391c2526597SStephen Boyd .num_parents = 1, 2392c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2393c2526597SStephen Boyd .ops = &clk_branch2_ops, 2394c2526597SStephen Boyd }, 2395c2526597SStephen Boyd }, 2396c2526597SStephen Boyd }; 2397c2526597SStephen Boyd 2398c2526597SStephen Boyd static struct clk_branch camss_vfe1_clk = { 2399c2526597SStephen Boyd .halt_reg = 0x36ac, 2400c2526597SStephen Boyd .clkr = { 2401c2526597SStephen Boyd .enable_reg = 0x36ac, 2402c2526597SStephen Boyd .enable_mask = BIT(0), 2403c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2404c2526597SStephen Boyd .name = "camss_vfe1_clk", 2405c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe1_clk_src" }, 2406c2526597SStephen Boyd .num_parents = 1, 2407c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2408c2526597SStephen Boyd .ops = &clk_branch2_ops, 2409c2526597SStephen Boyd }, 2410c2526597SStephen Boyd }, 2411c2526597SStephen Boyd }; 2412c2526597SStephen Boyd 2413c2526597SStephen Boyd static struct clk_branch camss_vfe1_stream_clk = { 2414c2526597SStephen Boyd .halt_reg = 0x3724, 2415c2526597SStephen Boyd .clkr = { 2416c2526597SStephen Boyd .enable_reg = 0x3724, 2417c2526597SStephen Boyd .enable_mask = BIT(0), 2418c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2419c2526597SStephen Boyd .name = "camss_vfe1_stream_clk", 2420c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe1_clk_src" }, 2421c2526597SStephen Boyd .num_parents = 1, 2422c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2423c2526597SStephen Boyd .ops = &clk_branch2_ops, 2424c2526597SStephen Boyd }, 2425c2526597SStephen Boyd }, 2426c2526597SStephen Boyd }; 2427c2526597SStephen Boyd 2428c2526597SStephen Boyd static struct clk_branch camss_vfe1_ahb_clk = { 2429c2526597SStephen Boyd .halt_reg = 0x3678, 2430c2526597SStephen Boyd .clkr = { 2431c2526597SStephen Boyd .enable_reg = 0x3678, 2432c2526597SStephen Boyd .enable_mask = BIT(0), 2433c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2434c2526597SStephen Boyd .name = "camss_vfe1_ahb_clk", 2435c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2436c2526597SStephen Boyd .num_parents = 1, 2437c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2438c2526597SStephen Boyd .ops = &clk_branch2_ops, 2439c2526597SStephen Boyd }, 2440c2526597SStephen Boyd }, 2441c2526597SStephen Boyd }; 2442c2526597SStephen Boyd 2443c2526597SStephen Boyd static struct clk_branch camss_csi_vfe0_clk = { 2444c2526597SStephen Boyd .halt_reg = 0x3704, 2445c2526597SStephen Boyd .clkr = { 2446c2526597SStephen Boyd .enable_reg = 0x3704, 2447c2526597SStephen Boyd .enable_mask = BIT(0), 2448c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2449c2526597SStephen Boyd .name = "camss_csi_vfe0_clk", 2450c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe0_clk_src" }, 2451c2526597SStephen Boyd .num_parents = 1, 2452c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2453c2526597SStephen Boyd .ops = &clk_branch2_ops, 2454c2526597SStephen Boyd }, 2455c2526597SStephen Boyd }, 2456c2526597SStephen Boyd }; 2457c2526597SStephen Boyd 2458c2526597SStephen Boyd static struct clk_branch camss_csi_vfe1_clk = { 2459c2526597SStephen Boyd .halt_reg = 0x3714, 2460c2526597SStephen Boyd .clkr = { 2461c2526597SStephen Boyd .enable_reg = 0x3714, 2462c2526597SStephen Boyd .enable_mask = BIT(0), 2463c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2464c2526597SStephen Boyd .name = "camss_csi_vfe1_clk", 2465c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe1_clk_src" }, 2466c2526597SStephen Boyd .num_parents = 1, 2467c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2468c2526597SStephen Boyd .ops = &clk_branch2_ops, 2469c2526597SStephen Boyd }, 2470c2526597SStephen Boyd }, 2471c2526597SStephen Boyd }; 2472c2526597SStephen Boyd 2473c2526597SStephen Boyd static struct clk_branch camss_cpp_vbif_ahb_clk = { 2474c2526597SStephen Boyd .halt_reg = 0x36c8, 2475c2526597SStephen Boyd .clkr = { 2476c2526597SStephen Boyd .enable_reg = 0x36c8, 2477c2526597SStephen Boyd .enable_mask = BIT(0), 2478c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2479c2526597SStephen Boyd .name = "camss_cpp_vbif_ahb_clk", 2480c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2481c2526597SStephen Boyd .num_parents = 1, 2482c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2483c2526597SStephen Boyd .ops = &clk_branch2_ops, 2484c2526597SStephen Boyd }, 2485c2526597SStephen Boyd }, 2486c2526597SStephen Boyd }; 2487c2526597SStephen Boyd 2488c2526597SStephen Boyd static struct clk_branch camss_cpp_axi_clk = { 2489c2526597SStephen Boyd .halt_reg = 0x36c4, 2490c2526597SStephen Boyd .clkr = { 2491c2526597SStephen Boyd .enable_reg = 0x36c4, 2492c2526597SStephen Boyd .enable_mask = BIT(0), 2493c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2494c2526597SStephen Boyd .name = "camss_cpp_axi_clk", 2495c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 2496c2526597SStephen Boyd .num_parents = 1, 2497c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2498c2526597SStephen Boyd .ops = &clk_branch2_ops, 2499c2526597SStephen Boyd }, 2500c2526597SStephen Boyd }, 2501c2526597SStephen Boyd }; 2502c2526597SStephen Boyd 2503c2526597SStephen Boyd static struct clk_branch camss_cpp_clk = { 2504c2526597SStephen Boyd .halt_reg = 0x36b0, 2505c2526597SStephen Boyd .clkr = { 2506c2526597SStephen Boyd .enable_reg = 0x36b0, 2507c2526597SStephen Boyd .enable_mask = BIT(0), 2508c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2509c2526597SStephen Boyd .name = "camss_cpp_clk", 2510c2526597SStephen Boyd .parent_names = (const char *[]){ "cpp_clk_src" }, 2511c2526597SStephen Boyd .num_parents = 1, 2512c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2513c2526597SStephen Boyd .ops = &clk_branch2_ops, 2514c2526597SStephen Boyd }, 2515c2526597SStephen Boyd }, 2516c2526597SStephen Boyd }; 2517c2526597SStephen Boyd 2518c2526597SStephen Boyd static struct clk_branch camss_cpp_ahb_clk = { 2519c2526597SStephen Boyd .halt_reg = 0x36b4, 2520c2526597SStephen Boyd .clkr = { 2521c2526597SStephen Boyd .enable_reg = 0x36b4, 2522c2526597SStephen Boyd .enable_mask = BIT(0), 2523c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2524c2526597SStephen Boyd .name = "camss_cpp_ahb_clk", 2525c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2526c2526597SStephen Boyd .num_parents = 1, 2527c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2528c2526597SStephen Boyd .ops = &clk_branch2_ops, 2529c2526597SStephen Boyd }, 2530c2526597SStephen Boyd }, 2531c2526597SStephen Boyd }; 2532c2526597SStephen Boyd 2533c2526597SStephen Boyd static struct clk_branch camss_csi0_clk = { 2534c2526597SStephen Boyd .halt_reg = 0x30b4, 2535c2526597SStephen Boyd .clkr = { 2536c2526597SStephen Boyd .enable_reg = 0x30b4, 2537c2526597SStephen Boyd .enable_mask = BIT(0), 2538c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2539c2526597SStephen Boyd .name = "camss_csi0_clk", 2540c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0_clk_src" }, 2541c2526597SStephen Boyd .num_parents = 1, 2542c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2543c2526597SStephen Boyd .ops = &clk_branch2_ops, 2544c2526597SStephen Boyd }, 2545c2526597SStephen Boyd }, 2546c2526597SStephen Boyd }; 2547c2526597SStephen Boyd 2548c2526597SStephen Boyd static struct clk_branch camss_csi0_ahb_clk = { 2549c2526597SStephen Boyd .halt_reg = 0x30bc, 2550c2526597SStephen Boyd .clkr = { 2551c2526597SStephen Boyd .enable_reg = 0x30bc, 2552c2526597SStephen Boyd .enable_mask = BIT(0), 2553c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2554c2526597SStephen Boyd .name = "camss_csi0_ahb_clk", 2555c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2556c2526597SStephen Boyd .num_parents = 1, 2557c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2558c2526597SStephen Boyd .ops = &clk_branch2_ops, 2559c2526597SStephen Boyd }, 2560c2526597SStephen Boyd }, 2561c2526597SStephen Boyd }; 2562c2526597SStephen Boyd 2563c2526597SStephen Boyd static struct clk_branch camss_csi0phy_clk = { 2564c2526597SStephen Boyd .halt_reg = 0x30c4, 2565c2526597SStephen Boyd .clkr = { 2566c2526597SStephen Boyd .enable_reg = 0x30c4, 2567c2526597SStephen Boyd .enable_mask = BIT(0), 2568c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2569c2526597SStephen Boyd .name = "camss_csi0phy_clk", 2570c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0_clk_src" }, 2571c2526597SStephen Boyd .num_parents = 1, 2572c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2573c2526597SStephen Boyd .ops = &clk_branch2_ops, 2574c2526597SStephen Boyd }, 2575c2526597SStephen Boyd }, 2576c2526597SStephen Boyd }; 2577c2526597SStephen Boyd 2578c2526597SStephen Boyd static struct clk_branch camss_csi0rdi_clk = { 2579c2526597SStephen Boyd .halt_reg = 0x30d4, 2580c2526597SStephen Boyd .clkr = { 2581c2526597SStephen Boyd .enable_reg = 0x30d4, 2582c2526597SStephen Boyd .enable_mask = BIT(0), 2583c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2584c2526597SStephen Boyd .name = "camss_csi0rdi_clk", 2585c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0_clk_src" }, 2586c2526597SStephen Boyd .num_parents = 1, 2587c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2588c2526597SStephen Boyd .ops = &clk_branch2_ops, 2589c2526597SStephen Boyd }, 2590c2526597SStephen Boyd }, 2591c2526597SStephen Boyd }; 2592c2526597SStephen Boyd 2593c2526597SStephen Boyd static struct clk_branch camss_csi0pix_clk = { 2594c2526597SStephen Boyd .halt_reg = 0x30e4, 2595c2526597SStephen Boyd .clkr = { 2596c2526597SStephen Boyd .enable_reg = 0x30e4, 2597c2526597SStephen Boyd .enable_mask = BIT(0), 2598c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2599c2526597SStephen Boyd .name = "camss_csi0pix_clk", 2600c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0_clk_src" }, 2601c2526597SStephen Boyd .num_parents = 1, 2602c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2603c2526597SStephen Boyd .ops = &clk_branch2_ops, 2604c2526597SStephen Boyd }, 2605c2526597SStephen Boyd }, 2606c2526597SStephen Boyd }; 2607c2526597SStephen Boyd 2608c2526597SStephen Boyd static struct clk_branch camss_csi1_clk = { 2609c2526597SStephen Boyd .halt_reg = 0x3124, 2610c2526597SStephen Boyd .clkr = { 2611c2526597SStephen Boyd .enable_reg = 0x3124, 2612c2526597SStephen Boyd .enable_mask = BIT(0), 2613c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2614c2526597SStephen Boyd .name = "camss_csi1_clk", 2615c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1_clk_src" }, 2616c2526597SStephen Boyd .num_parents = 1, 2617c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2618c2526597SStephen Boyd .ops = &clk_branch2_ops, 2619c2526597SStephen Boyd }, 2620c2526597SStephen Boyd }, 2621c2526597SStephen Boyd }; 2622c2526597SStephen Boyd 2623c2526597SStephen Boyd static struct clk_branch camss_csi1_ahb_clk = { 2624c2526597SStephen Boyd .halt_reg = 0x3128, 2625c2526597SStephen Boyd .clkr = { 2626c2526597SStephen Boyd .enable_reg = 0x3128, 2627c2526597SStephen Boyd .enable_mask = BIT(0), 2628c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2629c2526597SStephen Boyd .name = "camss_csi1_ahb_clk", 2630c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2631c2526597SStephen Boyd .num_parents = 1, 2632c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2633c2526597SStephen Boyd .ops = &clk_branch2_ops, 2634c2526597SStephen Boyd }, 2635c2526597SStephen Boyd }, 2636c2526597SStephen Boyd }; 2637c2526597SStephen Boyd 2638c2526597SStephen Boyd static struct clk_branch camss_csi1phy_clk = { 2639c2526597SStephen Boyd .halt_reg = 0x3134, 2640c2526597SStephen Boyd .clkr = { 2641c2526597SStephen Boyd .enable_reg = 0x3134, 2642c2526597SStephen Boyd .enable_mask = BIT(0), 2643c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2644c2526597SStephen Boyd .name = "camss_csi1phy_clk", 2645c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1_clk_src" }, 2646c2526597SStephen Boyd .num_parents = 1, 2647c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2648c2526597SStephen Boyd .ops = &clk_branch2_ops, 2649c2526597SStephen Boyd }, 2650c2526597SStephen Boyd }, 2651c2526597SStephen Boyd }; 2652c2526597SStephen Boyd 2653c2526597SStephen Boyd static struct clk_branch camss_csi1rdi_clk = { 2654c2526597SStephen Boyd .halt_reg = 0x3144, 2655c2526597SStephen Boyd .clkr = { 2656c2526597SStephen Boyd .enable_reg = 0x3144, 2657c2526597SStephen Boyd .enable_mask = BIT(0), 2658c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2659c2526597SStephen Boyd .name = "camss_csi1rdi_clk", 2660c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1_clk_src" }, 2661c2526597SStephen Boyd .num_parents = 1, 2662c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2663c2526597SStephen Boyd .ops = &clk_branch2_ops, 2664c2526597SStephen Boyd }, 2665c2526597SStephen Boyd }, 2666c2526597SStephen Boyd }; 2667c2526597SStephen Boyd 2668c2526597SStephen Boyd static struct clk_branch camss_csi1pix_clk = { 2669c2526597SStephen Boyd .halt_reg = 0x3154, 2670c2526597SStephen Boyd .clkr = { 2671c2526597SStephen Boyd .enable_reg = 0x3154, 2672c2526597SStephen Boyd .enable_mask = BIT(0), 2673c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2674c2526597SStephen Boyd .name = "camss_csi1pix_clk", 2675c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1_clk_src" }, 2676c2526597SStephen Boyd .num_parents = 1, 2677c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2678c2526597SStephen Boyd .ops = &clk_branch2_ops, 2679c2526597SStephen Boyd }, 2680c2526597SStephen Boyd }, 2681c2526597SStephen Boyd }; 2682c2526597SStephen Boyd 2683c2526597SStephen Boyd static struct clk_branch camss_csi2_clk = { 2684c2526597SStephen Boyd .halt_reg = 0x3184, 2685c2526597SStephen Boyd .clkr = { 2686c2526597SStephen Boyd .enable_reg = 0x3184, 2687c2526597SStephen Boyd .enable_mask = BIT(0), 2688c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2689c2526597SStephen Boyd .name = "camss_csi2_clk", 2690c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2_clk_src" }, 2691c2526597SStephen Boyd .num_parents = 1, 2692c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2693c2526597SStephen Boyd .ops = &clk_branch2_ops, 2694c2526597SStephen Boyd }, 2695c2526597SStephen Boyd }, 2696c2526597SStephen Boyd }; 2697c2526597SStephen Boyd 2698c2526597SStephen Boyd static struct clk_branch camss_csi2_ahb_clk = { 2699c2526597SStephen Boyd .halt_reg = 0x3188, 2700c2526597SStephen Boyd .clkr = { 2701c2526597SStephen Boyd .enable_reg = 0x3188, 2702c2526597SStephen Boyd .enable_mask = BIT(0), 2703c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2704c2526597SStephen Boyd .name = "camss_csi2_ahb_clk", 2705c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2706c2526597SStephen Boyd .num_parents = 1, 2707c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2708c2526597SStephen Boyd .ops = &clk_branch2_ops, 2709c2526597SStephen Boyd }, 2710c2526597SStephen Boyd }, 2711c2526597SStephen Boyd }; 2712c2526597SStephen Boyd 2713c2526597SStephen Boyd static struct clk_branch camss_csi2phy_clk = { 2714c2526597SStephen Boyd .halt_reg = 0x3194, 2715c2526597SStephen Boyd .clkr = { 2716c2526597SStephen Boyd .enable_reg = 0x3194, 2717c2526597SStephen Boyd .enable_mask = BIT(0), 2718c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2719c2526597SStephen Boyd .name = "camss_csi2phy_clk", 2720c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2_clk_src" }, 2721c2526597SStephen Boyd .num_parents = 1, 2722c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2723c2526597SStephen Boyd .ops = &clk_branch2_ops, 2724c2526597SStephen Boyd }, 2725c2526597SStephen Boyd }, 2726c2526597SStephen Boyd }; 2727c2526597SStephen Boyd 2728c2526597SStephen Boyd static struct clk_branch camss_csi2rdi_clk = { 2729c2526597SStephen Boyd .halt_reg = 0x31a4, 2730c2526597SStephen Boyd .clkr = { 2731c2526597SStephen Boyd .enable_reg = 0x31a4, 2732c2526597SStephen Boyd .enable_mask = BIT(0), 2733c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2734c2526597SStephen Boyd .name = "camss_csi2rdi_clk", 2735c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2_clk_src" }, 2736c2526597SStephen Boyd .num_parents = 1, 2737c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2738c2526597SStephen Boyd .ops = &clk_branch2_ops, 2739c2526597SStephen Boyd }, 2740c2526597SStephen Boyd }, 2741c2526597SStephen Boyd }; 2742c2526597SStephen Boyd 2743c2526597SStephen Boyd static struct clk_branch camss_csi2pix_clk = { 2744c2526597SStephen Boyd .halt_reg = 0x31b4, 2745c2526597SStephen Boyd .clkr = { 2746c2526597SStephen Boyd .enable_reg = 0x31b4, 2747c2526597SStephen Boyd .enable_mask = BIT(0), 2748c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2749c2526597SStephen Boyd .name = "camss_csi2pix_clk", 2750c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2_clk_src" }, 2751c2526597SStephen Boyd .num_parents = 1, 2752c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2753c2526597SStephen Boyd .ops = &clk_branch2_ops, 2754c2526597SStephen Boyd }, 2755c2526597SStephen Boyd }, 2756c2526597SStephen Boyd }; 2757c2526597SStephen Boyd 2758c2526597SStephen Boyd static struct clk_branch camss_csi3_clk = { 2759c2526597SStephen Boyd .halt_reg = 0x31e4, 2760c2526597SStephen Boyd .clkr = { 2761c2526597SStephen Boyd .enable_reg = 0x31e4, 2762c2526597SStephen Boyd .enable_mask = BIT(0), 2763c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2764c2526597SStephen Boyd .name = "camss_csi3_clk", 2765c2526597SStephen Boyd .parent_names = (const char *[]){ "csi3_clk_src" }, 2766c2526597SStephen Boyd .num_parents = 1, 2767c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2768c2526597SStephen Boyd .ops = &clk_branch2_ops, 2769c2526597SStephen Boyd }, 2770c2526597SStephen Boyd }, 2771c2526597SStephen Boyd }; 2772c2526597SStephen Boyd 2773c2526597SStephen Boyd static struct clk_branch camss_csi3_ahb_clk = { 2774c2526597SStephen Boyd .halt_reg = 0x31e8, 2775c2526597SStephen Boyd .clkr = { 2776c2526597SStephen Boyd .enable_reg = 0x31e8, 2777c2526597SStephen Boyd .enable_mask = BIT(0), 2778c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2779c2526597SStephen Boyd .name = "camss_csi3_ahb_clk", 2780c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2781c2526597SStephen Boyd .num_parents = 1, 2782c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2783c2526597SStephen Boyd .ops = &clk_branch2_ops, 2784c2526597SStephen Boyd }, 2785c2526597SStephen Boyd }, 2786c2526597SStephen Boyd }; 2787c2526597SStephen Boyd 2788c2526597SStephen Boyd static struct clk_branch camss_csi3phy_clk = { 2789c2526597SStephen Boyd .halt_reg = 0x31f4, 2790c2526597SStephen Boyd .clkr = { 2791c2526597SStephen Boyd .enable_reg = 0x31f4, 2792c2526597SStephen Boyd .enable_mask = BIT(0), 2793c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2794c2526597SStephen Boyd .name = "camss_csi3phy_clk", 2795c2526597SStephen Boyd .parent_names = (const char *[]){ "csi3_clk_src" }, 2796c2526597SStephen Boyd .num_parents = 1, 2797c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2798c2526597SStephen Boyd .ops = &clk_branch2_ops, 2799c2526597SStephen Boyd }, 2800c2526597SStephen Boyd }, 2801c2526597SStephen Boyd }; 2802c2526597SStephen Boyd 2803c2526597SStephen Boyd static struct clk_branch camss_csi3rdi_clk = { 2804c2526597SStephen Boyd .halt_reg = 0x3204, 2805c2526597SStephen Boyd .clkr = { 2806c2526597SStephen Boyd .enable_reg = 0x3204, 2807c2526597SStephen Boyd .enable_mask = BIT(0), 2808c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2809c2526597SStephen Boyd .name = "camss_csi3rdi_clk", 2810c2526597SStephen Boyd .parent_names = (const char *[]){ "csi3_clk_src" }, 2811c2526597SStephen Boyd .num_parents = 1, 2812c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2813c2526597SStephen Boyd .ops = &clk_branch2_ops, 2814c2526597SStephen Boyd }, 2815c2526597SStephen Boyd }, 2816c2526597SStephen Boyd }; 2817c2526597SStephen Boyd 2818c2526597SStephen Boyd static struct clk_branch camss_csi3pix_clk = { 2819c2526597SStephen Boyd .halt_reg = 0x3214, 2820c2526597SStephen Boyd .clkr = { 2821c2526597SStephen Boyd .enable_reg = 0x3214, 2822c2526597SStephen Boyd .enable_mask = BIT(0), 2823c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2824c2526597SStephen Boyd .name = "camss_csi3pix_clk", 2825c2526597SStephen Boyd .parent_names = (const char *[]){ "csi3_clk_src" }, 2826c2526597SStephen Boyd .num_parents = 1, 2827c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2828c2526597SStephen Boyd .ops = &clk_branch2_ops, 2829c2526597SStephen Boyd }, 2830c2526597SStephen Boyd }, 2831c2526597SStephen Boyd }; 2832c2526597SStephen Boyd 2833c2526597SStephen Boyd static struct clk_branch camss_ispif_ahb_clk = { 2834c2526597SStephen Boyd .halt_reg = 0x3224, 2835c2526597SStephen Boyd .clkr = { 2836c2526597SStephen Boyd .enable_reg = 0x3224, 2837c2526597SStephen Boyd .enable_mask = BIT(0), 2838c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2839c2526597SStephen Boyd .name = "camss_ispif_ahb_clk", 2840c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2841c2526597SStephen Boyd .num_parents = 1, 2842c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2843c2526597SStephen Boyd .ops = &clk_branch2_ops, 2844c2526597SStephen Boyd }, 2845c2526597SStephen Boyd }, 2846c2526597SStephen Boyd }; 2847c2526597SStephen Boyd 2848c2526597SStephen Boyd static struct clk_branch fd_core_clk = { 2849c2526597SStephen Boyd .halt_reg = 0x3b68, 2850c2526597SStephen Boyd .clkr = { 2851c2526597SStephen Boyd .enable_reg = 0x3b68, 2852c2526597SStephen Boyd .enable_mask = BIT(0), 2853c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2854c2526597SStephen Boyd .name = "fd_core_clk", 2855c2526597SStephen Boyd .parent_names = (const char *[]){ "fd_core_clk_src" }, 2856c2526597SStephen Boyd .num_parents = 1, 2857c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2858c2526597SStephen Boyd .ops = &clk_branch2_ops, 2859c2526597SStephen Boyd }, 2860c2526597SStephen Boyd }, 2861c2526597SStephen Boyd }; 2862c2526597SStephen Boyd 2863c2526597SStephen Boyd static struct clk_branch fd_core_uar_clk = { 2864c2526597SStephen Boyd .halt_reg = 0x3b6c, 2865c2526597SStephen Boyd .clkr = { 2866c2526597SStephen Boyd .enable_reg = 0x3b6c, 2867c2526597SStephen Boyd .enable_mask = BIT(0), 2868c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2869c2526597SStephen Boyd .name = "fd_core_uar_clk", 2870c2526597SStephen Boyd .parent_names = (const char *[]){ "fd_core_clk_src" }, 2871c2526597SStephen Boyd .num_parents = 1, 2872c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2873c2526597SStephen Boyd .ops = &clk_branch2_ops, 2874c2526597SStephen Boyd }, 2875c2526597SStephen Boyd }, 2876c2526597SStephen Boyd }; 2877c2526597SStephen Boyd 2878c2526597SStephen Boyd static struct clk_branch fd_ahb_clk = { 2879c2526597SStephen Boyd .halt_reg = 0x3ba74, 2880c2526597SStephen Boyd .clkr = { 2881c2526597SStephen Boyd .enable_reg = 0x3ba74, 2882c2526597SStephen Boyd .enable_mask = BIT(0), 2883c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2884c2526597SStephen Boyd .name = "fd_ahb_clk", 2885c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2886c2526597SStephen Boyd .num_parents = 1, 2887c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2888c2526597SStephen Boyd .ops = &clk_branch2_ops, 2889c2526597SStephen Boyd }, 2890c2526597SStephen Boyd }, 2891c2526597SStephen Boyd }; 2892c2526597SStephen Boyd 2893c2526597SStephen Boyd static struct clk_hw *mmcc_msm8996_hws[] = { 2894c2526597SStephen Boyd &gpll0_div.hw, 2895c2526597SStephen Boyd }; 2896c2526597SStephen Boyd 289763bb4fd6SRajendra Nayak static struct gdsc mmagic_bimc_gdsc = { 289863bb4fd6SRajendra Nayak .gdscr = 0x529c, 289963bb4fd6SRajendra Nayak .pd = { 290063bb4fd6SRajendra Nayak .name = "mmagic_bimc", 290163bb4fd6SRajendra Nayak }, 290263bb4fd6SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 290353f3abe9SVivek Gautam .flags = ALWAYS_ON, 290463bb4fd6SRajendra Nayak }; 290563bb4fd6SRajendra Nayak 29067e824d50SRajendra Nayak static struct gdsc mmagic_video_gdsc = { 29077e824d50SRajendra Nayak .gdscr = 0x119c, 29087e824d50SRajendra Nayak .gds_hw_ctrl = 0x120c, 29097e824d50SRajendra Nayak .pd = { 29107e824d50SRajendra Nayak .name = "mmagic_video", 29117e824d50SRajendra Nayak }, 29127e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29137705bb71SRajendra Nayak .flags = VOTABLE | ALWAYS_ON, 29147e824d50SRajendra Nayak }; 29157e824d50SRajendra Nayak 29167e824d50SRajendra Nayak static struct gdsc mmagic_mdss_gdsc = { 29177e824d50SRajendra Nayak .gdscr = 0x247c, 29187e824d50SRajendra Nayak .gds_hw_ctrl = 0x2480, 29197e824d50SRajendra Nayak .pd = { 29207e824d50SRajendra Nayak .name = "mmagic_mdss", 29217e824d50SRajendra Nayak }, 29227e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29237705bb71SRajendra Nayak .flags = VOTABLE | ALWAYS_ON, 29247e824d50SRajendra Nayak }; 29257e824d50SRajendra Nayak 29267e824d50SRajendra Nayak static struct gdsc mmagic_camss_gdsc = { 29277e824d50SRajendra Nayak .gdscr = 0x3c4c, 29287e824d50SRajendra Nayak .gds_hw_ctrl = 0x3c50, 29297e824d50SRajendra Nayak .pd = { 29307e824d50SRajendra Nayak .name = "mmagic_camss", 29317e824d50SRajendra Nayak }, 29327e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29337705bb71SRajendra Nayak .flags = VOTABLE | ALWAYS_ON, 29347e824d50SRajendra Nayak }; 29357e824d50SRajendra Nayak 29367e824d50SRajendra Nayak static struct gdsc venus_gdsc = { 29377e824d50SRajendra Nayak .gdscr = 0x1024, 29387e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 }, 29397e824d50SRajendra Nayak .cxc_count = 3, 29407e824d50SRajendra Nayak .pd = { 29417e824d50SRajendra Nayak .name = "venus", 29427e824d50SRajendra Nayak }, 29437e824d50SRajendra Nayak .parent = &mmagic_video_gdsc.pd, 29447e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29457e824d50SRajendra Nayak }; 29467e824d50SRajendra Nayak 29477e824d50SRajendra Nayak static struct gdsc venus_core0_gdsc = { 29487e824d50SRajendra Nayak .gdscr = 0x1040, 29497e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x1048 }, 29507e824d50SRajendra Nayak .cxc_count = 1, 29517e824d50SRajendra Nayak .pd = { 29527e824d50SRajendra Nayak .name = "venus_core0", 29537e824d50SRajendra Nayak }, 29544a43e35dSStanimir Varbanov .parent = &venus_gdsc.pd, 29557e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 295696893e10SSricharan R .flags = HW_CTRL, 29577e824d50SRajendra Nayak }; 29587e824d50SRajendra Nayak 29597e824d50SRajendra Nayak static struct gdsc venus_core1_gdsc = { 29607e824d50SRajendra Nayak .gdscr = 0x1044, 29617e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x104c }, 29627e824d50SRajendra Nayak .cxc_count = 1, 29637e824d50SRajendra Nayak .pd = { 29647e824d50SRajendra Nayak .name = "venus_core1", 29657e824d50SRajendra Nayak }, 29664a43e35dSStanimir Varbanov .parent = &venus_gdsc.pd, 29677e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 296896893e10SSricharan R .flags = HW_CTRL, 29697e824d50SRajendra Nayak }; 29707e824d50SRajendra Nayak 29717e824d50SRajendra Nayak static struct gdsc camss_gdsc = { 29727e824d50SRajendra Nayak .gdscr = 0x34a0, 29737e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36bc, 0x36c4 }, 29747e824d50SRajendra Nayak .cxc_count = 2, 29757e824d50SRajendra Nayak .pd = { 29767e824d50SRajendra Nayak .name = "camss", 29777e824d50SRajendra Nayak }, 29787e824d50SRajendra Nayak .parent = &mmagic_camss_gdsc.pd, 29797e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29807e824d50SRajendra Nayak }; 29817e824d50SRajendra Nayak 29827e824d50SRajendra Nayak static struct gdsc vfe0_gdsc = { 29837e824d50SRajendra Nayak .gdscr = 0x3664, 29847e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36a8 }, 29857e824d50SRajendra Nayak .cxc_count = 1, 29867e824d50SRajendra Nayak .pd = { 29877e824d50SRajendra Nayak .name = "vfe0", 29887e824d50SRajendra Nayak }, 29897e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 29907e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29917e824d50SRajendra Nayak }; 29927e824d50SRajendra Nayak 29937e824d50SRajendra Nayak static struct gdsc vfe1_gdsc = { 29947e824d50SRajendra Nayak .gdscr = 0x3674, 29957e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36ac }, 29967e824d50SRajendra Nayak .cxc_count = 1, 29977e824d50SRajendra Nayak .pd = { 2998a62ca337SRajendra Nayak .name = "vfe1", 29997e824d50SRajendra Nayak }, 30007e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 30017e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30027e824d50SRajendra Nayak }; 30037e824d50SRajendra Nayak 30047e824d50SRajendra Nayak static struct gdsc jpeg_gdsc = { 30057e824d50SRajendra Nayak .gdscr = 0x35a4, 30067e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 }, 30077e824d50SRajendra Nayak .cxc_count = 4, 30087e824d50SRajendra Nayak .pd = { 30097e824d50SRajendra Nayak .name = "jpeg", 30107e824d50SRajendra Nayak }, 30117e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 30127e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30137e824d50SRajendra Nayak }; 30147e824d50SRajendra Nayak 30157e824d50SRajendra Nayak static struct gdsc cpp_gdsc = { 30167e824d50SRajendra Nayak .gdscr = 0x36d4, 30177e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36b0 }, 30187e824d50SRajendra Nayak .cxc_count = 1, 30197e824d50SRajendra Nayak .pd = { 30207e824d50SRajendra Nayak .name = "cpp", 30217e824d50SRajendra Nayak }, 30227e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 30237e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30247e824d50SRajendra Nayak }; 30257e824d50SRajendra Nayak 30267e824d50SRajendra Nayak static struct gdsc fd_gdsc = { 30277e824d50SRajendra Nayak .gdscr = 0x3b64, 30287e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x3b68, 0x3b6c }, 30297e824d50SRajendra Nayak .cxc_count = 2, 30307e824d50SRajendra Nayak .pd = { 30317e824d50SRajendra Nayak .name = "fd", 30327e824d50SRajendra Nayak }, 30337e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 30347e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30357e824d50SRajendra Nayak }; 30367e824d50SRajendra Nayak 30377e824d50SRajendra Nayak static struct gdsc mdss_gdsc = { 30387e824d50SRajendra Nayak .gdscr = 0x2304, 30397e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x2310, 0x231c }, 30407e824d50SRajendra Nayak .cxc_count = 2, 30417e824d50SRajendra Nayak .pd = { 30427e824d50SRajendra Nayak .name = "mdss", 30437e824d50SRajendra Nayak }, 30447e824d50SRajendra Nayak .parent = &mmagic_mdss_gdsc.pd, 30457e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30467e824d50SRajendra Nayak }; 30477e824d50SRajendra Nayak 30484154f619SRajendra Nayak static struct gdsc gpu_gdsc = { 30494154f619SRajendra Nayak .gdscr = 0x4034, 30504154f619SRajendra Nayak .gds_hw_ctrl = 0x4038, 30514154f619SRajendra Nayak .pd = { 30524154f619SRajendra Nayak .name = "gpu", 30534154f619SRajendra Nayak }, 30544154f619SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30554154f619SRajendra Nayak .flags = VOTABLE, 30564154f619SRajendra Nayak }; 30574154f619SRajendra Nayak 30584154f619SRajendra Nayak static struct gdsc gpu_gx_gdsc = { 30594154f619SRajendra Nayak .gdscr = 0x4024, 30604154f619SRajendra Nayak .clamp_io_ctrl = 0x4300, 30614154f619SRajendra Nayak .cxcs = (unsigned int []){ 0x4028 }, 30624154f619SRajendra Nayak .cxc_count = 1, 30634154f619SRajendra Nayak .pd = { 30644154f619SRajendra Nayak .name = "gpu_gx", 30654154f619SRajendra Nayak }, 30664154f619SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 306790a3691eSBjorn Andersson .parent = &gpu_gdsc.pd, 30684154f619SRajendra Nayak .flags = CLAMP_IO, 306990a3691eSBjorn Andersson .supply = "vdd-gfx", 30704154f619SRajendra Nayak }; 30714154f619SRajendra Nayak 3072c2526597SStephen Boyd static struct clk_regmap *mmcc_msm8996_clocks[] = { 3073c2526597SStephen Boyd [MMPLL0_EARLY] = &mmpll0_early.clkr, 3074c2526597SStephen Boyd [MMPLL0_PLL] = &mmpll0.clkr, 3075c2526597SStephen Boyd [MMPLL1_EARLY] = &mmpll1_early.clkr, 3076c2526597SStephen Boyd [MMPLL1_PLL] = &mmpll1.clkr, 3077c2526597SStephen Boyd [MMPLL2_EARLY] = &mmpll2_early.clkr, 3078c2526597SStephen Boyd [MMPLL2_PLL] = &mmpll2.clkr, 3079c2526597SStephen Boyd [MMPLL3_EARLY] = &mmpll3_early.clkr, 3080c2526597SStephen Boyd [MMPLL3_PLL] = &mmpll3.clkr, 3081c2526597SStephen Boyd [MMPLL4_EARLY] = &mmpll4_early.clkr, 3082c2526597SStephen Boyd [MMPLL4_PLL] = &mmpll4.clkr, 3083c2526597SStephen Boyd [MMPLL5_EARLY] = &mmpll5_early.clkr, 3084c2526597SStephen Boyd [MMPLL5_PLL] = &mmpll5.clkr, 3085c2526597SStephen Boyd [MMPLL8_EARLY] = &mmpll8_early.clkr, 3086c2526597SStephen Boyd [MMPLL8_PLL] = &mmpll8.clkr, 3087c2526597SStephen Boyd [MMPLL9_EARLY] = &mmpll9_early.clkr, 3088c2526597SStephen Boyd [MMPLL9_PLL] = &mmpll9.clkr, 3089c2526597SStephen Boyd [AHB_CLK_SRC] = &ahb_clk_src.clkr, 3090c2526597SStephen Boyd [AXI_CLK_SRC] = &axi_clk_src.clkr, 3091c2526597SStephen Boyd [MAXI_CLK_SRC] = &maxi_clk_src.clkr, 3092c2526597SStephen Boyd [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 3093c2526597SStephen Boyd [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 3094c2526597SStephen Boyd [ISENSE_CLK_SRC] = &isense_clk_src.clkr, 3095c2526597SStephen Boyd [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 3096c2526597SStephen Boyd [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, 3097c2526597SStephen Boyd [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr, 3098c2526597SStephen Boyd [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr, 3099c2526597SStephen Boyd [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3100c2526597SStephen Boyd [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 3101c2526597SStephen Boyd [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3102c2526597SStephen Boyd [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 3103c2526597SStephen Boyd [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3104c2526597SStephen Boyd [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 3105c2526597SStephen Boyd [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3106c2526597SStephen Boyd [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 3107c2526597SStephen Boyd [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3108c2526597SStephen Boyd [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 3109c2526597SStephen Boyd [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3110c2526597SStephen Boyd [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3111c2526597SStephen Boyd [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3112c2526597SStephen Boyd [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3113c2526597SStephen Boyd [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 3114c2526597SStephen Boyd [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 3115c2526597SStephen Boyd [CCI_CLK_SRC] = &cci_clk_src.clkr, 3116c2526597SStephen Boyd [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3117c2526597SStephen Boyd [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3118c2526597SStephen Boyd [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 3119c2526597SStephen Boyd [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr, 3120c2526597SStephen Boyd [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr, 3121c2526597SStephen Boyd [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr, 3122c2526597SStephen Boyd [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3123c2526597SStephen Boyd [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, 3124c2526597SStephen Boyd [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr, 3125c2526597SStephen Boyd [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3126c2526597SStephen Boyd [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 3127c2526597SStephen Boyd [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3128c2526597SStephen Boyd [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3129c2526597SStephen Boyd [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3130c2526597SStephen Boyd [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 3131c2526597SStephen Boyd [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 3132c2526597SStephen Boyd [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr, 3133c2526597SStephen Boyd [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr, 3134c2526597SStephen Boyd [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr, 3135c2526597SStephen Boyd [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, 3136c2526597SStephen Boyd [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, 3137c2526597SStephen Boyd [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr, 3138c2526597SStephen Boyd [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr, 3139c2526597SStephen Boyd [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr, 3140c2526597SStephen Boyd [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr, 3141c2526597SStephen Boyd [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr, 3142c2526597SStephen Boyd [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr, 3143c2526597SStephen Boyd [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr, 3144c2526597SStephen Boyd [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr, 3145c2526597SStephen Boyd [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr, 3146c2526597SStephen Boyd [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr, 3147c2526597SStephen Boyd [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr, 3148c2526597SStephen Boyd [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr, 3149c2526597SStephen Boyd [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr, 3150c2526597SStephen Boyd [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr, 3151c2526597SStephen Boyd [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr, 3152c2526597SStephen Boyd [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr, 3153c2526597SStephen Boyd [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr, 3154c2526597SStephen Boyd [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr, 3155c2526597SStephen Boyd [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr, 3156c2526597SStephen Boyd [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr, 3157c2526597SStephen Boyd [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr, 3158c2526597SStephen Boyd [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr, 3159c2526597SStephen Boyd [GPU_AHB_CLK] = &gpu_ahb_clk.clkr, 3160c2526597SStephen Boyd [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr, 3161c2526597SStephen Boyd [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr, 3162c2526597SStephen Boyd [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr, 3163c2526597SStephen Boyd [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr, 3164c2526597SStephen Boyd [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr, 3165c2526597SStephen Boyd [VIDEO_CORE_CLK] = &video_core_clk.clkr, 3166c2526597SStephen Boyd [VIDEO_AXI_CLK] = &video_axi_clk.clkr, 3167c2526597SStephen Boyd [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr, 3168c2526597SStephen Boyd [VIDEO_AHB_CLK] = &video_ahb_clk.clkr, 3169c2526597SStephen Boyd [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr, 3170c2526597SStephen Boyd [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr, 3171c2526597SStephen Boyd [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 3172c2526597SStephen Boyd [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, 3173c2526597SStephen Boyd [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 3174c2526597SStephen Boyd [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 3175c2526597SStephen Boyd [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 3176c2526597SStephen Boyd [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 3177c2526597SStephen Boyd [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 3178c2526597SStephen Boyd [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 3179c2526597SStephen Boyd [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 3180c2526597SStephen Boyd [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 3181c2526597SStephen Boyd [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 3182c2526597SStephen Boyd [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 3183c2526597SStephen Boyd [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 3184c2526597SStephen Boyd [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 3185c2526597SStephen Boyd [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, 3186c2526597SStephen Boyd [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 3187c2526597SStephen Boyd [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 3188c2526597SStephen Boyd [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 3189c2526597SStephen Boyd [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 3190c2526597SStephen Boyd [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 3191c2526597SStephen Boyd [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 3192c2526597SStephen Boyd [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 3193c2526597SStephen Boyd [CAMSS_CCI_CLK] = &camss_cci_clk.clkr, 3194c2526597SStephen Boyd [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr, 3195c2526597SStephen Boyd [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr, 3196c2526597SStephen Boyd [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr, 3197c2526597SStephen Boyd [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr, 3198c2526597SStephen Boyd [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr, 3199c2526597SStephen Boyd [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr, 3200c2526597SStephen Boyd [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr, 3201c2526597SStephen Boyd [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr, 3202c2526597SStephen Boyd [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr, 3203c2526597SStephen Boyd [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr, 3204c2526597SStephen Boyd [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr, 3205c2526597SStephen Boyd [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr, 3206c2526597SStephen Boyd [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr, 3207c2526597SStephen Boyd [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr, 3208c2526597SStephen Boyd [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr, 3209c2526597SStephen Boyd [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr, 3210c2526597SStephen Boyd [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr, 3211c2526597SStephen Boyd [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr, 3212c2526597SStephen Boyd [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr, 3213c2526597SStephen Boyd [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr, 3214c2526597SStephen Boyd [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 3215c2526597SStephen Boyd [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 3216c2526597SStephen Boyd [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr, 3217c2526597SStephen Boyd [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr, 3218c2526597SStephen Boyd [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr, 3219c2526597SStephen Boyd [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr, 3220c2526597SStephen Boyd [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 3221c2526597SStephen Boyd [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 3222c2526597SStephen Boyd [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, 3223c2526597SStephen Boyd [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 3224c2526597SStephen Boyd [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 3225c2526597SStephen Boyd [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 3226c2526597SStephen Boyd [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 3227c2526597SStephen Boyd [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, 3228c2526597SStephen Boyd [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 3229c2526597SStephen Boyd [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 3230c2526597SStephen Boyd [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 3231c2526597SStephen Boyd [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 3232c2526597SStephen Boyd [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, 3233c2526597SStephen Boyd [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 3234c2526597SStephen Boyd [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 3235c2526597SStephen Boyd [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 3236c2526597SStephen Boyd [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 3237c2526597SStephen Boyd [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, 3238c2526597SStephen Boyd [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 3239c2526597SStephen Boyd [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 3240c2526597SStephen Boyd [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 3241c2526597SStephen Boyd [FD_CORE_CLK] = &fd_core_clk.clkr, 3242c2526597SStephen Boyd [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr, 3243c2526597SStephen Boyd [FD_AHB_CLK] = &fd_ahb_clk.clkr, 3244c2526597SStephen Boyd }; 3245c2526597SStephen Boyd 32467e824d50SRajendra Nayak static struct gdsc *mmcc_msm8996_gdscs[] = { 324763bb4fd6SRajendra Nayak [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc, 32487e824d50SRajendra Nayak [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc, 32497e824d50SRajendra Nayak [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc, 32507e824d50SRajendra Nayak [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc, 32517e824d50SRajendra Nayak [VENUS_GDSC] = &venus_gdsc, 32527e824d50SRajendra Nayak [VENUS_CORE0_GDSC] = &venus_core0_gdsc, 32537e824d50SRajendra Nayak [VENUS_CORE1_GDSC] = &venus_core1_gdsc, 32547e824d50SRajendra Nayak [CAMSS_GDSC] = &camss_gdsc, 32557e824d50SRajendra Nayak [VFE0_GDSC] = &vfe0_gdsc, 32567e824d50SRajendra Nayak [VFE1_GDSC] = &vfe1_gdsc, 32577e824d50SRajendra Nayak [JPEG_GDSC] = &jpeg_gdsc, 32587e824d50SRajendra Nayak [CPP_GDSC] = &cpp_gdsc, 32597e824d50SRajendra Nayak [FD_GDSC] = &fd_gdsc, 32607e824d50SRajendra Nayak [MDSS_GDSC] = &mdss_gdsc, 32614154f619SRajendra Nayak [GPU_GDSC] = &gpu_gdsc, 32624154f619SRajendra Nayak [GPU_GX_GDSC] = &gpu_gx_gdsc, 32637e824d50SRajendra Nayak }; 32647e824d50SRajendra Nayak 3265c2526597SStephen Boyd static const struct qcom_reset_map mmcc_msm8996_resets[] = { 3266c2526597SStephen Boyd [MMAGICAHB_BCR] = { 0x5020 }, 3267c2526597SStephen Boyd [MMAGIC_CFG_BCR] = { 0x5050 }, 3268c2526597SStephen Boyd [MISC_BCR] = { 0x5010 }, 3269c2526597SStephen Boyd [BTO_BCR] = { 0x5030 }, 3270c2526597SStephen Boyd [MMAGICAXI_BCR] = { 0x5060 }, 3271c2526597SStephen Boyd [MMAGICMAXI_BCR] = { 0x5070 }, 3272c2526597SStephen Boyd [DSA_BCR] = { 0x50a0 }, 3273c2526597SStephen Boyd [MMAGIC_CAMSS_BCR] = { 0x3c40 }, 3274c2526597SStephen Boyd [THROTTLE_CAMSS_BCR] = { 0x3c30 }, 3275c2526597SStephen Boyd [SMMU_VFE_BCR] = { 0x3c00 }, 3276c2526597SStephen Boyd [SMMU_CPP_BCR] = { 0x3c10 }, 3277c2526597SStephen Boyd [SMMU_JPEG_BCR] = { 0x3c20 }, 3278c2526597SStephen Boyd [MMAGIC_MDSS_BCR] = { 0x2470 }, 3279c2526597SStephen Boyd [THROTTLE_MDSS_BCR] = { 0x2460 }, 3280c2526597SStephen Boyd [SMMU_ROT_BCR] = { 0x2440 }, 3281c2526597SStephen Boyd [SMMU_MDP_BCR] = { 0x2450 }, 3282c2526597SStephen Boyd [MMAGIC_VIDEO_BCR] = { 0x1190 }, 3283c2526597SStephen Boyd [THROTTLE_VIDEO_BCR] = { 0x1180 }, 3284c2526597SStephen Boyd [SMMU_VIDEO_BCR] = { 0x1170 }, 3285c2526597SStephen Boyd [MMAGIC_BIMC_BCR] = { 0x5290 }, 3286c2526597SStephen Boyd [GPU_GX_BCR] = { 0x4020 }, 3287c2526597SStephen Boyd [GPU_BCR] = { 0x4030 }, 3288c2526597SStephen Boyd [GPU_AON_BCR] = { 0x4040 }, 3289c2526597SStephen Boyd [VMEM_BCR] = { 0x1200 }, 3290c2526597SStephen Boyd [MMSS_RBCPR_BCR] = { 0x4080 }, 3291c2526597SStephen Boyd [VIDEO_BCR] = { 0x1020 }, 3292c2526597SStephen Boyd [MDSS_BCR] = { 0x2300 }, 3293c2526597SStephen Boyd [CAMSS_TOP_BCR] = { 0x3480 }, 3294c2526597SStephen Boyd [CAMSS_AHB_BCR] = { 0x3488 }, 3295c2526597SStephen Boyd [CAMSS_MICRO_BCR] = { 0x3490 }, 3296c2526597SStephen Boyd [CAMSS_CCI_BCR] = { 0x3340 }, 3297c2526597SStephen Boyd [CAMSS_PHY0_BCR] = { 0x3020 }, 3298c2526597SStephen Boyd [CAMSS_PHY1_BCR] = { 0x3050 }, 3299c2526597SStephen Boyd [CAMSS_PHY2_BCR] = { 0x3080 }, 3300c2526597SStephen Boyd [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 }, 3301c2526597SStephen Boyd [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 }, 3302c2526597SStephen Boyd [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 }, 3303c2526597SStephen Boyd [CAMSS_JPEG_BCR] = { 0x35a0 }, 3304c2526597SStephen Boyd [CAMSS_VFE_BCR] = { 0x36a0 }, 3305c2526597SStephen Boyd [CAMSS_VFE0_BCR] = { 0x3660 }, 3306c2526597SStephen Boyd [CAMSS_VFE1_BCR] = { 0x3670 }, 3307c2526597SStephen Boyd [CAMSS_CSI_VFE0_BCR] = { 0x3700 }, 3308c2526597SStephen Boyd [CAMSS_CSI_VFE1_BCR] = { 0x3710 }, 3309c2526597SStephen Boyd [CAMSS_CPP_TOP_BCR] = { 0x36c0 }, 3310c2526597SStephen Boyd [CAMSS_CPP_BCR] = { 0x36d0 }, 3311c2526597SStephen Boyd [CAMSS_CSI0_BCR] = { 0x30b0 }, 3312c2526597SStephen Boyd [CAMSS_CSI0RDI_BCR] = { 0x30d0 }, 3313c2526597SStephen Boyd [CAMSS_CSI0PIX_BCR] = { 0x30e0 }, 3314c2526597SStephen Boyd [CAMSS_CSI1_BCR] = { 0x3120 }, 3315c2526597SStephen Boyd [CAMSS_CSI1RDI_BCR] = { 0x3140 }, 3316c2526597SStephen Boyd [CAMSS_CSI1PIX_BCR] = { 0x3150 }, 3317c2526597SStephen Boyd [CAMSS_CSI2_BCR] = { 0x3180 }, 3318c2526597SStephen Boyd [CAMSS_CSI2RDI_BCR] = { 0x31a0 }, 3319c2526597SStephen Boyd [CAMSS_CSI2PIX_BCR] = { 0x31b0 }, 3320c2526597SStephen Boyd [CAMSS_CSI3_BCR] = { 0x31e0 }, 3321c2526597SStephen Boyd [CAMSS_CSI3RDI_BCR] = { 0x3200 }, 3322c2526597SStephen Boyd [CAMSS_CSI3PIX_BCR] = { 0x3210 }, 3323c2526597SStephen Boyd [CAMSS_ISPIF_BCR] = { 0x3220 }, 3324c2526597SStephen Boyd [FD_BCR] = { 0x3b60 }, 3325c2526597SStephen Boyd [MMSS_SPDM_RM_BCR] = { 0x300 }, 3326c2526597SStephen Boyd }; 3327c2526597SStephen Boyd 3328c2526597SStephen Boyd static const struct regmap_config mmcc_msm8996_regmap_config = { 3329c2526597SStephen Boyd .reg_bits = 32, 3330c2526597SStephen Boyd .reg_stride = 4, 3331c2526597SStephen Boyd .val_bits = 32, 3332c2526597SStephen Boyd .max_register = 0xb008, 3333c2526597SStephen Boyd .fast_io = true, 3334c2526597SStephen Boyd }; 3335c2526597SStephen Boyd 3336c2526597SStephen Boyd static const struct qcom_cc_desc mmcc_msm8996_desc = { 3337c2526597SStephen Boyd .config = &mmcc_msm8996_regmap_config, 3338c2526597SStephen Boyd .clks = mmcc_msm8996_clocks, 3339c2526597SStephen Boyd .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks), 3340c2526597SStephen Boyd .resets = mmcc_msm8996_resets, 3341c2526597SStephen Boyd .num_resets = ARRAY_SIZE(mmcc_msm8996_resets), 33427e824d50SRajendra Nayak .gdscs = mmcc_msm8996_gdscs, 33437e824d50SRajendra Nayak .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs), 3344760be658SJeffrey Hugo .clk_hws = mmcc_msm8996_hws, 3345760be658SJeffrey Hugo .num_clk_hws = ARRAY_SIZE(mmcc_msm8996_hws), 3346c2526597SStephen Boyd }; 3347c2526597SStephen Boyd 3348c2526597SStephen Boyd static const struct of_device_id mmcc_msm8996_match_table[] = { 3349c2526597SStephen Boyd { .compatible = "qcom,mmcc-msm8996" }, 3350c2526597SStephen Boyd { } 3351c2526597SStephen Boyd }; 3352c2526597SStephen Boyd MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table); 3353c2526597SStephen Boyd 3354c2526597SStephen Boyd static int mmcc_msm8996_probe(struct platform_device *pdev) 3355c2526597SStephen Boyd { 3356c2526597SStephen Boyd struct regmap *regmap; 3357c2526597SStephen Boyd 3358c2526597SStephen Boyd regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc); 3359c2526597SStephen Boyd if (IS_ERR(regmap)) 3360c2526597SStephen Boyd return PTR_ERR(regmap); 3361c2526597SStephen Boyd 3362c2526597SStephen Boyd /* Disable the AHB DCD */ 3363c2526597SStephen Boyd regmap_update_bits(regmap, 0x50d8, BIT(31), 0); 3364c2526597SStephen Boyd /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */ 3365c2526597SStephen Boyd regmap_update_bits(regmap, 0x5054, BIT(15), 0); 3366c2526597SStephen Boyd 3367c2526597SStephen Boyd return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap); 3368c2526597SStephen Boyd } 3369c2526597SStephen Boyd 3370c2526597SStephen Boyd static struct platform_driver mmcc_msm8996_driver = { 3371c2526597SStephen Boyd .probe = mmcc_msm8996_probe, 3372c2526597SStephen Boyd .driver = { 3373c2526597SStephen Boyd .name = "mmcc-msm8996", 3374c2526597SStephen Boyd .of_match_table = mmcc_msm8996_match_table, 3375c2526597SStephen Boyd }, 3376c2526597SStephen Boyd }; 3377c2526597SStephen Boyd module_platform_driver(mmcc_msm8996_driver); 3378c2526597SStephen Boyd 3379c2526597SStephen Boyd MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver"); 3380c2526597SStephen Boyd MODULE_LICENSE("GPL v2"); 3381c2526597SStephen Boyd MODULE_ALIAS("platform:mmcc-msm8996"); 3382