1c2526597SStephen Boyd /*x 2c2526597SStephen Boyd * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3c2526597SStephen Boyd * 4c2526597SStephen Boyd * This software is licensed under the terms of the GNU General Public 5c2526597SStephen Boyd * License version 2, as published by the Free Software Foundation, and 6c2526597SStephen Boyd * may be copied, distributed, and modified under those terms. 7c2526597SStephen Boyd * 8c2526597SStephen Boyd * This program is distributed in the hope that it will be useful, 9c2526597SStephen Boyd * but WITHOUT ANY WARRANTY; without even the implied warranty of 10c2526597SStephen Boyd * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11c2526597SStephen Boyd * GNU General Public License for more details. 12c2526597SStephen Boyd */ 13c2526597SStephen Boyd 14c2526597SStephen Boyd #include <linux/kernel.h> 15c2526597SStephen Boyd #include <linux/bitops.h> 16c2526597SStephen Boyd #include <linux/err.h> 17c2526597SStephen Boyd #include <linux/platform_device.h> 18c2526597SStephen Boyd #include <linux/module.h> 19c2526597SStephen Boyd #include <linux/of.h> 20c2526597SStephen Boyd #include <linux/of_device.h> 21c2526597SStephen Boyd #include <linux/clk-provider.h> 22c2526597SStephen Boyd #include <linux/regmap.h> 23c2526597SStephen Boyd #include <linux/reset-controller.h> 24c2526597SStephen Boyd #include <linux/clk.h> 25c2526597SStephen Boyd 26c2526597SStephen Boyd #include <dt-bindings/clock/qcom,mmcc-msm8996.h> 27c2526597SStephen Boyd 28c2526597SStephen Boyd #include "common.h" 29c2526597SStephen Boyd #include "clk-regmap.h" 30c2526597SStephen Boyd #include "clk-regmap-divider.h" 31c2526597SStephen Boyd #include "clk-alpha-pll.h" 32c2526597SStephen Boyd #include "clk-rcg.h" 33c2526597SStephen Boyd #include "clk-branch.h" 34c2526597SStephen Boyd #include "reset.h" 357e824d50SRajendra Nayak #include "gdsc.h" 36c2526597SStephen Boyd 37c2526597SStephen Boyd #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 38c2526597SStephen Boyd 39c2526597SStephen Boyd enum { 40c2526597SStephen Boyd P_XO, 41c2526597SStephen Boyd P_MMPLL0, 42c2526597SStephen Boyd P_GPLL0, 43c2526597SStephen Boyd P_GPLL0_DIV, 44c2526597SStephen Boyd P_MMPLL1, 45c2526597SStephen Boyd P_MMPLL9, 46c2526597SStephen Boyd P_MMPLL2, 47c2526597SStephen Boyd P_MMPLL8, 48c2526597SStephen Boyd P_MMPLL3, 49c2526597SStephen Boyd P_DSI0PLL, 50c2526597SStephen Boyd P_DSI1PLL, 51c2526597SStephen Boyd P_MMPLL5, 52c2526597SStephen Boyd P_HDMIPLL, 53c2526597SStephen Boyd P_DSI0PLL_BYTE, 54c2526597SStephen Boyd P_DSI1PLL_BYTE, 55c2526597SStephen Boyd P_MMPLL4, 56c2526597SStephen Boyd }; 57c2526597SStephen Boyd 58c2526597SStephen Boyd static const struct parent_map mmss_xo_hdmi_map[] = { 59c2526597SStephen Boyd { P_XO, 0 }, 60c2526597SStephen Boyd { P_HDMIPLL, 1 } 61c2526597SStephen Boyd }; 62c2526597SStephen Boyd 63c2526597SStephen Boyd static const char * const mmss_xo_hdmi[] = { 64c2526597SStephen Boyd "xo", 65c2526597SStephen Boyd "hdmipll" 66c2526597SStephen Boyd }; 67c2526597SStephen Boyd 68c2526597SStephen Boyd static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { 69c2526597SStephen Boyd { P_XO, 0 }, 70c2526597SStephen Boyd { P_DSI0PLL, 1 }, 71c2526597SStephen Boyd { P_DSI1PLL, 2 } 72c2526597SStephen Boyd }; 73c2526597SStephen Boyd 74c2526597SStephen Boyd static const char * const mmss_xo_dsi0pll_dsi1pll[] = { 75c2526597SStephen Boyd "xo", 76c2526597SStephen Boyd "dsi0pll", 77c2526597SStephen Boyd "dsi1pll" 78c2526597SStephen Boyd }; 79c2526597SStephen Boyd 80c2526597SStephen Boyd static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { 81c2526597SStephen Boyd { P_XO, 0 }, 82c2526597SStephen Boyd { P_GPLL0, 5 }, 83c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 84c2526597SStephen Boyd }; 85c2526597SStephen Boyd 86c2526597SStephen Boyd static const char * const mmss_xo_gpll0_gpll0_div[] = { 87c2526597SStephen Boyd "xo", 88c2526597SStephen Boyd "gpll0", 89c2526597SStephen Boyd "gpll0_div" 90c2526597SStephen Boyd }; 91c2526597SStephen Boyd 92c2526597SStephen Boyd static const struct parent_map mmss_xo_dsibyte_map[] = { 93c2526597SStephen Boyd { P_XO, 0 }, 94c2526597SStephen Boyd { P_DSI0PLL_BYTE, 1 }, 95c2526597SStephen Boyd { P_DSI1PLL_BYTE, 2 } 96c2526597SStephen Boyd }; 97c2526597SStephen Boyd 98c2526597SStephen Boyd static const char * const mmss_xo_dsibyte[] = { 99c2526597SStephen Boyd "xo", 100c2526597SStephen Boyd "dsi0pllbyte", 101c2526597SStephen Boyd "dsi1pllbyte" 102c2526597SStephen Boyd }; 103c2526597SStephen Boyd 104c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { 105c2526597SStephen Boyd { P_XO, 0 }, 106c2526597SStephen Boyd { P_MMPLL0, 1 }, 107c2526597SStephen Boyd { P_GPLL0, 5 }, 108c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 109c2526597SStephen Boyd }; 110c2526597SStephen Boyd 111c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = { 112c2526597SStephen Boyd "xo", 113c2526597SStephen Boyd "mmpll0", 114c2526597SStephen Boyd "gpll0", 115c2526597SStephen Boyd "gpll0_div" 116c2526597SStephen Boyd }; 117c2526597SStephen Boyd 118c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { 119c2526597SStephen Boyd { P_XO, 0 }, 120c2526597SStephen Boyd { P_MMPLL0, 1 }, 121c2526597SStephen Boyd { P_MMPLL1, 2 }, 122c2526597SStephen Boyd { P_GPLL0, 5 }, 123c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 124c2526597SStephen Boyd }; 125c2526597SStephen Boyd 126c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { 127c2526597SStephen Boyd "xo", 128c2526597SStephen Boyd "mmpll0", 129c2526597SStephen Boyd "mmpll1", 130c2526597SStephen Boyd "gpll0", 131c2526597SStephen Boyd "gpll0_div" 132c2526597SStephen Boyd }; 133c2526597SStephen Boyd 134c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { 135c2526597SStephen Boyd { P_XO, 0 }, 136c2526597SStephen Boyd { P_MMPLL0, 1 }, 137c2526597SStephen Boyd { P_MMPLL3, 3 }, 138c2526597SStephen Boyd { P_GPLL0, 5 }, 139c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 140c2526597SStephen Boyd }; 141c2526597SStephen Boyd 142c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { 143c2526597SStephen Boyd "xo", 144c2526597SStephen Boyd "mmpll0", 145c2526597SStephen Boyd "mmpll3", 146c2526597SStephen Boyd "gpll0", 147c2526597SStephen Boyd "gpll0_div" 148c2526597SStephen Boyd }; 149c2526597SStephen Boyd 150c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { 151c2526597SStephen Boyd { P_XO, 0 }, 152c2526597SStephen Boyd { P_MMPLL0, 1 }, 153c2526597SStephen Boyd { P_MMPLL5, 2 }, 154c2526597SStephen Boyd { P_GPLL0, 5 }, 155c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 156c2526597SStephen Boyd }; 157c2526597SStephen Boyd 158c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { 159c2526597SStephen Boyd "xo", 160c2526597SStephen Boyd "mmpll0", 161c2526597SStephen Boyd "mmpll5", 162c2526597SStephen Boyd "gpll0", 163c2526597SStephen Boyd "gpll0_div" 164c2526597SStephen Boyd }; 165c2526597SStephen Boyd 166c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { 167c2526597SStephen Boyd { P_XO, 0 }, 168c2526597SStephen Boyd { P_MMPLL0, 1 }, 169c2526597SStephen Boyd { P_MMPLL4, 3 }, 170c2526597SStephen Boyd { P_GPLL0, 5 }, 171c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 172c2526597SStephen Boyd }; 173c2526597SStephen Boyd 174c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { 175c2526597SStephen Boyd "xo", 176c2526597SStephen Boyd "mmpll0", 177c2526597SStephen Boyd "mmpll4", 178c2526597SStephen Boyd "gpll0", 179c2526597SStephen Boyd "gpll0_div" 180c2526597SStephen Boyd }; 181c2526597SStephen Boyd 182c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { 183c2526597SStephen Boyd { P_XO, 0 }, 184c2526597SStephen Boyd { P_MMPLL0, 1 }, 185c2526597SStephen Boyd { P_MMPLL9, 2 }, 186c2526597SStephen Boyd { P_MMPLL2, 3 }, 187c2526597SStephen Boyd { P_MMPLL8, 4 }, 188c2526597SStephen Boyd { P_GPLL0, 5 } 189c2526597SStephen Boyd }; 190c2526597SStephen Boyd 191c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { 192c2526597SStephen Boyd "xo", 193c2526597SStephen Boyd "mmpll0", 194c2526597SStephen Boyd "mmpll9", 195c2526597SStephen Boyd "mmpll2", 196c2526597SStephen Boyd "mmpll8", 197c2526597SStephen Boyd "gpll0" 198c2526597SStephen Boyd }; 199c2526597SStephen Boyd 200c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { 201c2526597SStephen Boyd { P_XO, 0 }, 202c2526597SStephen Boyd { P_MMPLL0, 1 }, 203c2526597SStephen Boyd { P_MMPLL9, 2 }, 204c2526597SStephen Boyd { P_MMPLL2, 3 }, 205c2526597SStephen Boyd { P_MMPLL8, 4 }, 206c2526597SStephen Boyd { P_GPLL0, 5 }, 207c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 208c2526597SStephen Boyd }; 209c2526597SStephen Boyd 210c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { 211c2526597SStephen Boyd "xo", 212c2526597SStephen Boyd "mmpll0", 213c2526597SStephen Boyd "mmpll9", 214c2526597SStephen Boyd "mmpll2", 215c2526597SStephen Boyd "mmpll8", 216c2526597SStephen Boyd "gpll0", 217c2526597SStephen Boyd "gpll0_div" 218c2526597SStephen Boyd }; 219c2526597SStephen Boyd 220c2526597SStephen Boyd static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { 221c2526597SStephen Boyd { P_XO, 0 }, 222c2526597SStephen Boyd { P_MMPLL0, 1 }, 223c2526597SStephen Boyd { P_MMPLL1, 2 }, 224c2526597SStephen Boyd { P_MMPLL4, 3 }, 225c2526597SStephen Boyd { P_MMPLL3, 4 }, 226c2526597SStephen Boyd { P_GPLL0, 5 }, 227c2526597SStephen Boyd { P_GPLL0_DIV, 6 } 228c2526597SStephen Boyd }; 229c2526597SStephen Boyd 230c2526597SStephen Boyd static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { 231c2526597SStephen Boyd "xo", 232c2526597SStephen Boyd "mmpll0", 233c2526597SStephen Boyd "mmpll1", 234c2526597SStephen Boyd "mmpll4", 235c2526597SStephen Boyd "mmpll3", 236c2526597SStephen Boyd "gpll0", 237c2526597SStephen Boyd "gpll0_div" 238c2526597SStephen Boyd }; 239c2526597SStephen Boyd 240c2526597SStephen Boyd static struct clk_fixed_factor gpll0_div = { 241c2526597SStephen Boyd .mult = 1, 242c2526597SStephen Boyd .div = 2, 243c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 244c2526597SStephen Boyd .name = "gpll0_div", 245c2526597SStephen Boyd .parent_names = (const char *[]){ "gpll0" }, 246c2526597SStephen Boyd .num_parents = 1, 247c2526597SStephen Boyd .ops = &clk_fixed_factor_ops, 248c2526597SStephen Boyd }, 249c2526597SStephen Boyd }; 250c2526597SStephen Boyd 251c2526597SStephen Boyd static struct pll_vco mmpll_p_vco[] = { 252c2526597SStephen Boyd { 250000000, 500000000, 3 }, 253c2526597SStephen Boyd { 500000000, 1000000000, 2 }, 254c2526597SStephen Boyd { 1000000000, 1500000000, 1 }, 255c2526597SStephen Boyd { 1500000000, 2000000000, 0 }, 256c2526597SStephen Boyd }; 257c2526597SStephen Boyd 258c2526597SStephen Boyd static struct pll_vco mmpll_gfx_vco[] = { 259c2526597SStephen Boyd { 400000000, 1000000000, 2 }, 260c2526597SStephen Boyd { 1000000000, 1500000000, 1 }, 261c2526597SStephen Boyd { 1500000000, 2000000000, 0 }, 262c2526597SStephen Boyd }; 263c2526597SStephen Boyd 264c2526597SStephen Boyd static struct pll_vco mmpll_t_vco[] = { 265c2526597SStephen Boyd { 500000000, 1500000000, 0 }, 266c2526597SStephen Boyd }; 267c2526597SStephen Boyd 268c2526597SStephen Boyd static struct clk_alpha_pll mmpll0_early = { 269c2526597SStephen Boyd .offset = 0x0, 27028d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 271c2526597SStephen Boyd .vco_table = mmpll_p_vco, 272c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 273c2526597SStephen Boyd .clkr = { 274c2526597SStephen Boyd .enable_reg = 0x100, 275c2526597SStephen Boyd .enable_mask = BIT(0), 276c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 277c2526597SStephen Boyd .name = "mmpll0_early", 278c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 279c2526597SStephen Boyd .num_parents = 1, 280c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 281c2526597SStephen Boyd }, 282c2526597SStephen Boyd }, 283c2526597SStephen Boyd }; 284c2526597SStephen Boyd 285c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll0 = { 286c2526597SStephen Boyd .offset = 0x0, 28728d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 288c2526597SStephen Boyd .width = 4, 289c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 290c2526597SStephen Boyd .name = "mmpll0", 291c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll0_early" }, 292c2526597SStephen Boyd .num_parents = 1, 293c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 294c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 295c2526597SStephen Boyd }, 296c2526597SStephen Boyd }; 297c2526597SStephen Boyd 298c2526597SStephen Boyd static struct clk_alpha_pll mmpll1_early = { 299c2526597SStephen Boyd .offset = 0x30, 30028d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 301c2526597SStephen Boyd .vco_table = mmpll_p_vco, 302c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 303c2526597SStephen Boyd .clkr = { 304c2526597SStephen Boyd .enable_reg = 0x100, 305c2526597SStephen Boyd .enable_mask = BIT(1), 306c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 307c2526597SStephen Boyd .name = "mmpll1_early", 308c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 309c2526597SStephen Boyd .num_parents = 1, 310c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 311c2526597SStephen Boyd } 312c2526597SStephen Boyd }, 313c2526597SStephen Boyd }; 314c2526597SStephen Boyd 315c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll1 = { 316c2526597SStephen Boyd .offset = 0x30, 31728d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 318c2526597SStephen Boyd .width = 4, 319c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 320c2526597SStephen Boyd .name = "mmpll1", 321c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll1_early" }, 322c2526597SStephen Boyd .num_parents = 1, 323c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 324c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 325c2526597SStephen Boyd }, 326c2526597SStephen Boyd }; 327c2526597SStephen Boyd 328c2526597SStephen Boyd static struct clk_alpha_pll mmpll2_early = { 329c2526597SStephen Boyd .offset = 0x4100, 33028d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 331c2526597SStephen Boyd .vco_table = mmpll_gfx_vco, 332c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 333c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 334c2526597SStephen Boyd .name = "mmpll2_early", 335c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 336c2526597SStephen Boyd .num_parents = 1, 337c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 338c2526597SStephen Boyd }, 339c2526597SStephen Boyd }; 340c2526597SStephen Boyd 341c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll2 = { 342c2526597SStephen Boyd .offset = 0x4100, 34328d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 344c2526597SStephen Boyd .width = 4, 345c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 346c2526597SStephen Boyd .name = "mmpll2", 347c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll2_early" }, 348c2526597SStephen Boyd .num_parents = 1, 349c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 350c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 351c2526597SStephen Boyd }, 352c2526597SStephen Boyd }; 353c2526597SStephen Boyd 354c2526597SStephen Boyd static struct clk_alpha_pll mmpll3_early = { 355c2526597SStephen Boyd .offset = 0x60, 35628d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 357c2526597SStephen Boyd .vco_table = mmpll_p_vco, 358c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 359c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 360c2526597SStephen Boyd .name = "mmpll3_early", 361c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 362c2526597SStephen Boyd .num_parents = 1, 363c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 364c2526597SStephen Boyd }, 365c2526597SStephen Boyd }; 366c2526597SStephen Boyd 367c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll3 = { 368c2526597SStephen Boyd .offset = 0x60, 36928d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 370c2526597SStephen Boyd .width = 4, 371c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 372c2526597SStephen Boyd .name = "mmpll3", 373c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll3_early" }, 374c2526597SStephen Boyd .num_parents = 1, 375c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 376c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 377c2526597SStephen Boyd }, 378c2526597SStephen Boyd }; 379c2526597SStephen Boyd 380c2526597SStephen Boyd static struct clk_alpha_pll mmpll4_early = { 381c2526597SStephen Boyd .offset = 0x90, 38228d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 383c2526597SStephen Boyd .vco_table = mmpll_t_vco, 384c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_t_vco), 385c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 386c2526597SStephen Boyd .name = "mmpll4_early", 387c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 388c2526597SStephen Boyd .num_parents = 1, 389c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 390c2526597SStephen Boyd }, 391c2526597SStephen Boyd }; 392c2526597SStephen Boyd 393c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll4 = { 394c2526597SStephen Boyd .offset = 0x90, 39528d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 396c2526597SStephen Boyd .width = 2, 397c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 398c2526597SStephen Boyd .name = "mmpll4", 399c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll4_early" }, 400c2526597SStephen Boyd .num_parents = 1, 401c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 402c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 403c2526597SStephen Boyd }, 404c2526597SStephen Boyd }; 405c2526597SStephen Boyd 406c2526597SStephen Boyd static struct clk_alpha_pll mmpll5_early = { 407c2526597SStephen Boyd .offset = 0xc0, 40828d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 409c2526597SStephen Boyd .vco_table = mmpll_p_vco, 410c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_p_vco), 411c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 412c2526597SStephen Boyd .name = "mmpll5_early", 413c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 414c2526597SStephen Boyd .num_parents = 1, 415c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 416c2526597SStephen Boyd }, 417c2526597SStephen Boyd }; 418c2526597SStephen Boyd 419c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll5 = { 420c2526597SStephen Boyd .offset = 0xc0, 42128d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 422c2526597SStephen Boyd .width = 4, 423c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 424c2526597SStephen Boyd .name = "mmpll5", 425c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll5_early" }, 426c2526597SStephen Boyd .num_parents = 1, 427c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 428c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 429c2526597SStephen Boyd }, 430c2526597SStephen Boyd }; 431c2526597SStephen Boyd 432c2526597SStephen Boyd static struct clk_alpha_pll mmpll8_early = { 433c2526597SStephen Boyd .offset = 0x4130, 43428d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 435c2526597SStephen Boyd .vco_table = mmpll_gfx_vco, 436c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 437c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 438c2526597SStephen Boyd .name = "mmpll8_early", 439c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 440c2526597SStephen Boyd .num_parents = 1, 441c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 442c2526597SStephen Boyd }, 443c2526597SStephen Boyd }; 444c2526597SStephen Boyd 445c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll8 = { 446c2526597SStephen Boyd .offset = 0x4130, 44728d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 448c2526597SStephen Boyd .width = 4, 449c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 450c2526597SStephen Boyd .name = "mmpll8", 451c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll8_early" }, 452c2526597SStephen Boyd .num_parents = 1, 453c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 454c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 455c2526597SStephen Boyd }, 456c2526597SStephen Boyd }; 457c2526597SStephen Boyd 458c2526597SStephen Boyd static struct clk_alpha_pll mmpll9_early = { 459c2526597SStephen Boyd .offset = 0x4200, 46028d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 461c2526597SStephen Boyd .vco_table = mmpll_t_vco, 462c2526597SStephen Boyd .num_vco = ARRAY_SIZE(mmpll_t_vco), 463c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 464c2526597SStephen Boyd .name = "mmpll9_early", 465c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 466c2526597SStephen Boyd .num_parents = 1, 467c2526597SStephen Boyd .ops = &clk_alpha_pll_ops, 468c2526597SStephen Boyd }, 469c2526597SStephen Boyd }; 470c2526597SStephen Boyd 471c2526597SStephen Boyd static struct clk_alpha_pll_postdiv mmpll9 = { 472c2526597SStephen Boyd .offset = 0x4200, 47328d3f06eSAbhishek Sahu .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 474c2526597SStephen Boyd .width = 2, 475c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 476c2526597SStephen Boyd .name = "mmpll9", 477c2526597SStephen Boyd .parent_names = (const char *[]){ "mmpll9_early" }, 478c2526597SStephen Boyd .num_parents = 1, 479c2526597SStephen Boyd .ops = &clk_alpha_pll_postdiv_ops, 480c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 481c2526597SStephen Boyd }, 482c2526597SStephen Boyd }; 483c2526597SStephen Boyd 484c2526597SStephen Boyd static const struct freq_tbl ftbl_ahb_clk_src[] = { 485c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 486c2526597SStephen Boyd F(40000000, P_GPLL0_DIV, 7.5, 0, 0), 487c2526597SStephen Boyd F(80000000, P_MMPLL0, 10, 0, 0), 488c2526597SStephen Boyd { } 489c2526597SStephen Boyd }; 490c2526597SStephen Boyd 491c2526597SStephen Boyd static struct clk_rcg2 ahb_clk_src = { 492c2526597SStephen Boyd .cmd_rcgr = 0x5000, 493c2526597SStephen Boyd .hid_width = 5, 494c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 495c2526597SStephen Boyd .freq_tbl = ftbl_ahb_clk_src, 496c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 497c2526597SStephen Boyd .name = "ahb_clk_src", 498c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 499c2526597SStephen Boyd .num_parents = 4, 500c2526597SStephen Boyd .ops = &clk_rcg2_ops, 501c2526597SStephen Boyd }, 502c2526597SStephen Boyd }; 503c2526597SStephen Boyd 504c2526597SStephen Boyd static const struct freq_tbl ftbl_axi_clk_src[] = { 505c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 506c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 507c2526597SStephen Boyd F(100000000, P_GPLL0, 6, 0, 0), 508c2526597SStephen Boyd F(171430000, P_GPLL0, 3.5, 0, 0), 509c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 510c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 511c2526597SStephen Boyd F(400000000, P_MMPLL0, 2, 0, 0), 512c2526597SStephen Boyd { } 513c2526597SStephen Boyd }; 514c2526597SStephen Boyd 515c2526597SStephen Boyd static struct clk_rcg2 axi_clk_src = { 516c2526597SStephen Boyd .cmd_rcgr = 0x5040, 517c2526597SStephen Boyd .hid_width = 5, 518c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 519c2526597SStephen Boyd .freq_tbl = ftbl_axi_clk_src, 520c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 521c2526597SStephen Boyd .name = "axi_clk_src", 522c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 523c2526597SStephen Boyd .num_parents = 5, 524c2526597SStephen Boyd .ops = &clk_rcg2_ops, 525c2526597SStephen Boyd }, 526c2526597SStephen Boyd }; 527c2526597SStephen Boyd 528c2526597SStephen Boyd static struct clk_rcg2 maxi_clk_src = { 529c2526597SStephen Boyd .cmd_rcgr = 0x5090, 530c2526597SStephen Boyd .hid_width = 5, 531c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 532c2526597SStephen Boyd .freq_tbl = ftbl_axi_clk_src, 533c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 534c2526597SStephen Boyd .name = "maxi_clk_src", 535c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 536c2526597SStephen Boyd .num_parents = 5, 537c2526597SStephen Boyd .ops = &clk_rcg2_ops, 538c2526597SStephen Boyd }, 539c2526597SStephen Boyd }; 540c2526597SStephen Boyd 541c2526597SStephen Boyd static struct clk_rcg2 gfx3d_clk_src = { 542c2526597SStephen Boyd .cmd_rcgr = 0x4000, 543c2526597SStephen Boyd .hid_width = 5, 544c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map, 545c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 546c2526597SStephen Boyd .name = "gfx3d_clk_src", 547c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, 548c2526597SStephen Boyd .num_parents = 6, 549c2526597SStephen Boyd .ops = &clk_gfx3d_ops, 550c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 551c2526597SStephen Boyd }, 552c2526597SStephen Boyd }; 553c2526597SStephen Boyd 554c2526597SStephen Boyd static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { 555c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 556c2526597SStephen Boyd { } 557c2526597SStephen Boyd }; 558c2526597SStephen Boyd 559c2526597SStephen Boyd static struct clk_rcg2 rbbmtimer_clk_src = { 560c2526597SStephen Boyd .cmd_rcgr = 0x4090, 561c2526597SStephen Boyd .hid_width = 5, 562c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 563c2526597SStephen Boyd .freq_tbl = ftbl_rbbmtimer_clk_src, 564c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 565c2526597SStephen Boyd .name = "rbbmtimer_clk_src", 566c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 567c2526597SStephen Boyd .num_parents = 4, 568c2526597SStephen Boyd .ops = &clk_rcg2_ops, 569c2526597SStephen Boyd }, 570c2526597SStephen Boyd }; 571c2526597SStephen Boyd 572c2526597SStephen Boyd static struct clk_rcg2 isense_clk_src = { 573c2526597SStephen Boyd .cmd_rcgr = 0x4010, 574c2526597SStephen Boyd .hid_width = 5, 575c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map, 576c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 577c2526597SStephen Boyd .name = "isense_clk_src", 578c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div, 579c2526597SStephen Boyd .num_parents = 7, 580c2526597SStephen Boyd .ops = &clk_rcg2_ops, 581c2526597SStephen Boyd }, 582c2526597SStephen Boyd }; 583c2526597SStephen Boyd 584c2526597SStephen Boyd static const struct freq_tbl ftbl_rbcpr_clk_src[] = { 585c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 586c2526597SStephen Boyd F(50000000, P_GPLL0, 12, 0, 0), 587c2526597SStephen Boyd { } 588c2526597SStephen Boyd }; 589c2526597SStephen Boyd 590c2526597SStephen Boyd static struct clk_rcg2 rbcpr_clk_src = { 591c2526597SStephen Boyd .cmd_rcgr = 0x4060, 592c2526597SStephen Boyd .hid_width = 5, 593c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 594c2526597SStephen Boyd .freq_tbl = ftbl_rbcpr_clk_src, 595c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 596c2526597SStephen Boyd .name = "rbcpr_clk_src", 597c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 598c2526597SStephen Boyd .num_parents = 4, 599c2526597SStephen Boyd .ops = &clk_rcg2_ops, 600c2526597SStephen Boyd }, 601c2526597SStephen Boyd }; 602c2526597SStephen Boyd 603c2526597SStephen Boyd static const struct freq_tbl ftbl_video_core_clk_src[] = { 604c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 605c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 606c2526597SStephen Boyd F(346666667, P_MMPLL3, 3, 0, 0), 607c2526597SStephen Boyd F(520000000, P_MMPLL3, 2, 0, 0), 608c2526597SStephen Boyd { } 609c2526597SStephen Boyd }; 610c2526597SStephen Boyd 611c2526597SStephen Boyd static struct clk_rcg2 video_core_clk_src = { 612c2526597SStephen Boyd .cmd_rcgr = 0x1000, 613c2526597SStephen Boyd .mnd_width = 8, 614c2526597SStephen Boyd .hid_width = 5, 615c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 616c2526597SStephen Boyd .freq_tbl = ftbl_video_core_clk_src, 617c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 618c2526597SStephen Boyd .name = "video_core_clk_src", 619c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 620c2526597SStephen Boyd .num_parents = 5, 621c2526597SStephen Boyd .ops = &clk_rcg2_ops, 622c2526597SStephen Boyd }, 623c2526597SStephen Boyd }; 624c2526597SStephen Boyd 625c2526597SStephen Boyd static struct clk_rcg2 video_subcore0_clk_src = { 626c2526597SStephen Boyd .cmd_rcgr = 0x1060, 627c2526597SStephen Boyd .mnd_width = 8, 628c2526597SStephen Boyd .hid_width = 5, 629c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 630c2526597SStephen Boyd .freq_tbl = ftbl_video_core_clk_src, 631c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 632c2526597SStephen Boyd .name = "video_subcore0_clk_src", 633c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 634c2526597SStephen Boyd .num_parents = 5, 635c2526597SStephen Boyd .ops = &clk_rcg2_ops, 636c2526597SStephen Boyd }, 637c2526597SStephen Boyd }; 638c2526597SStephen Boyd 639c2526597SStephen Boyd static struct clk_rcg2 video_subcore1_clk_src = { 640c2526597SStephen Boyd .cmd_rcgr = 0x1080, 641c2526597SStephen Boyd .mnd_width = 8, 642c2526597SStephen Boyd .hid_width = 5, 643c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 644c2526597SStephen Boyd .freq_tbl = ftbl_video_core_clk_src, 645c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 646c2526597SStephen Boyd .name = "video_subcore1_clk_src", 647c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 648c2526597SStephen Boyd .num_parents = 5, 649c2526597SStephen Boyd .ops = &clk_rcg2_ops, 650c2526597SStephen Boyd }, 651c2526597SStephen Boyd }; 652c2526597SStephen Boyd 653c2526597SStephen Boyd static struct clk_rcg2 pclk0_clk_src = { 654c2526597SStephen Boyd .cmd_rcgr = 0x2000, 655c2526597SStephen Boyd .mnd_width = 8, 656c2526597SStephen Boyd .hid_width = 5, 657c2526597SStephen Boyd .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 658c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 659c2526597SStephen Boyd .name = "pclk0_clk_src", 660c2526597SStephen Boyd .parent_names = mmss_xo_dsi0pll_dsi1pll, 661c2526597SStephen Boyd .num_parents = 3, 662c2526597SStephen Boyd .ops = &clk_pixel_ops, 663c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 664c2526597SStephen Boyd }, 665c2526597SStephen Boyd }; 666c2526597SStephen Boyd 667c2526597SStephen Boyd static struct clk_rcg2 pclk1_clk_src = { 668c2526597SStephen Boyd .cmd_rcgr = 0x2020, 669c2526597SStephen Boyd .mnd_width = 8, 670c2526597SStephen Boyd .hid_width = 5, 671c2526597SStephen Boyd .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 672c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 673c2526597SStephen Boyd .name = "pclk1_clk_src", 674c2526597SStephen Boyd .parent_names = mmss_xo_dsi0pll_dsi1pll, 675c2526597SStephen Boyd .num_parents = 3, 676c2526597SStephen Boyd .ops = &clk_pixel_ops, 677c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 678c2526597SStephen Boyd }, 679c2526597SStephen Boyd }; 680c2526597SStephen Boyd 681c2526597SStephen Boyd static const struct freq_tbl ftbl_mdp_clk_src[] = { 682c2526597SStephen Boyd F(85714286, P_GPLL0, 7, 0, 0), 683c2526597SStephen Boyd F(100000000, P_GPLL0, 6, 0, 0), 684c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 685c2526597SStephen Boyd F(171428571, P_GPLL0, 3.5, 0, 0), 686c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 687c2526597SStephen Boyd F(275000000, P_MMPLL5, 3, 0, 0), 688c2526597SStephen Boyd F(300000000, P_GPLL0, 2, 0, 0), 689c2526597SStephen Boyd F(330000000, P_MMPLL5, 2.5, 0, 0), 690c2526597SStephen Boyd F(412500000, P_MMPLL5, 2, 0, 0), 691c2526597SStephen Boyd { } 692c2526597SStephen Boyd }; 693c2526597SStephen Boyd 694c2526597SStephen Boyd static struct clk_rcg2 mdp_clk_src = { 695c2526597SStephen Boyd .cmd_rcgr = 0x2040, 696c2526597SStephen Boyd .hid_width = 5, 697c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map, 698c2526597SStephen Boyd .freq_tbl = ftbl_mdp_clk_src, 699c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 700c2526597SStephen Boyd .name = "mdp_clk_src", 701c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, 702c2526597SStephen Boyd .num_parents = 5, 703c2526597SStephen Boyd .ops = &clk_rcg2_ops, 704c2526597SStephen Boyd }, 705c2526597SStephen Boyd }; 706c2526597SStephen Boyd 707c2526597SStephen Boyd static struct freq_tbl extpclk_freq_tbl[] = { 708c2526597SStephen Boyd { .src = P_HDMIPLL }, 709c2526597SStephen Boyd { } 710c2526597SStephen Boyd }; 711c2526597SStephen Boyd 712c2526597SStephen Boyd static struct clk_rcg2 extpclk_clk_src = { 713c2526597SStephen Boyd .cmd_rcgr = 0x2060, 714c2526597SStephen Boyd .hid_width = 5, 715c2526597SStephen Boyd .parent_map = mmss_xo_hdmi_map, 716c2526597SStephen Boyd .freq_tbl = extpclk_freq_tbl, 717c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 718c2526597SStephen Boyd .name = "extpclk_clk_src", 719c2526597SStephen Boyd .parent_names = mmss_xo_hdmi, 720c2526597SStephen Boyd .num_parents = 2, 721c2526597SStephen Boyd .ops = &clk_byte_ops, 722c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 723c2526597SStephen Boyd }, 724c2526597SStephen Boyd }; 725c2526597SStephen Boyd 726c2526597SStephen Boyd static struct freq_tbl ftbl_mdss_vsync_clk[] = { 727c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 728c2526597SStephen Boyd { } 729c2526597SStephen Boyd }; 730c2526597SStephen Boyd 731c2526597SStephen Boyd static struct clk_rcg2 vsync_clk_src = { 732c2526597SStephen Boyd .cmd_rcgr = 0x2080, 733c2526597SStephen Boyd .hid_width = 5, 734c2526597SStephen Boyd .parent_map = mmss_xo_gpll0_gpll0_div_map, 735c2526597SStephen Boyd .freq_tbl = ftbl_mdss_vsync_clk, 736c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 737c2526597SStephen Boyd .name = "vsync_clk_src", 738c2526597SStephen Boyd .parent_names = mmss_xo_gpll0_gpll0_div, 739c2526597SStephen Boyd .num_parents = 3, 740c2526597SStephen Boyd .ops = &clk_rcg2_ops, 741c2526597SStephen Boyd }, 742c2526597SStephen Boyd }; 743c2526597SStephen Boyd 744c2526597SStephen Boyd static struct freq_tbl ftbl_mdss_hdmi_clk[] = { 745c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 746c2526597SStephen Boyd { } 747c2526597SStephen Boyd }; 748c2526597SStephen Boyd 749c2526597SStephen Boyd static struct clk_rcg2 hdmi_clk_src = { 750c2526597SStephen Boyd .cmd_rcgr = 0x2100, 751c2526597SStephen Boyd .hid_width = 5, 752c2526597SStephen Boyd .parent_map = mmss_xo_gpll0_gpll0_div_map, 753c2526597SStephen Boyd .freq_tbl = ftbl_mdss_hdmi_clk, 754c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 755c2526597SStephen Boyd .name = "hdmi_clk_src", 756c2526597SStephen Boyd .parent_names = mmss_xo_gpll0_gpll0_div, 757c2526597SStephen Boyd .num_parents = 3, 758c2526597SStephen Boyd .ops = &clk_rcg2_ops, 759c2526597SStephen Boyd }, 760c2526597SStephen Boyd }; 761c2526597SStephen Boyd 762c2526597SStephen Boyd static struct clk_rcg2 byte0_clk_src = { 763c2526597SStephen Boyd .cmd_rcgr = 0x2120, 764c2526597SStephen Boyd .hid_width = 5, 765c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 766c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 767c2526597SStephen Boyd .name = "byte0_clk_src", 768c2526597SStephen Boyd .parent_names = mmss_xo_dsibyte, 769c2526597SStephen Boyd .num_parents = 3, 770c2526597SStephen Boyd .ops = &clk_byte2_ops, 771c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 772c2526597SStephen Boyd }, 773c2526597SStephen Boyd }; 774c2526597SStephen Boyd 775c2526597SStephen Boyd static struct clk_rcg2 byte1_clk_src = { 776c2526597SStephen Boyd .cmd_rcgr = 0x2140, 777c2526597SStephen Boyd .hid_width = 5, 778c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 779c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 780c2526597SStephen Boyd .name = "byte1_clk_src", 781c2526597SStephen Boyd .parent_names = mmss_xo_dsibyte, 782c2526597SStephen Boyd .num_parents = 3, 783c2526597SStephen Boyd .ops = &clk_byte2_ops, 784c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 785c2526597SStephen Boyd }, 786c2526597SStephen Boyd }; 787c2526597SStephen Boyd 788c2526597SStephen Boyd static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { 789c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 790c2526597SStephen Boyd { } 791c2526597SStephen Boyd }; 792c2526597SStephen Boyd 793c2526597SStephen Boyd static struct clk_rcg2 esc0_clk_src = { 794c2526597SStephen Boyd .cmd_rcgr = 0x2160, 795c2526597SStephen Boyd .hid_width = 5, 796c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 797c2526597SStephen Boyd .freq_tbl = ftbl_mdss_esc0_1_clk, 798c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 799c2526597SStephen Boyd .name = "esc0_clk_src", 800c2526597SStephen Boyd .parent_names = mmss_xo_dsibyte, 801c2526597SStephen Boyd .num_parents = 3, 802c2526597SStephen Boyd .ops = &clk_rcg2_ops, 803c2526597SStephen Boyd }, 804c2526597SStephen Boyd }; 805c2526597SStephen Boyd 806c2526597SStephen Boyd static struct clk_rcg2 esc1_clk_src = { 807c2526597SStephen Boyd .cmd_rcgr = 0x2180, 808c2526597SStephen Boyd .hid_width = 5, 809c2526597SStephen Boyd .parent_map = mmss_xo_dsibyte_map, 810c2526597SStephen Boyd .freq_tbl = ftbl_mdss_esc0_1_clk, 811c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 812c2526597SStephen Boyd .name = "esc1_clk_src", 813c2526597SStephen Boyd .parent_names = mmss_xo_dsibyte, 814c2526597SStephen Boyd .num_parents = 3, 815c2526597SStephen Boyd .ops = &clk_rcg2_ops, 816c2526597SStephen Boyd }, 817c2526597SStephen Boyd }; 818c2526597SStephen Boyd 819c2526597SStephen Boyd static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { 820c2526597SStephen Boyd F(10000, P_XO, 16, 1, 120), 821c2526597SStephen Boyd F(24000, P_XO, 16, 1, 50), 822c2526597SStephen Boyd F(6000000, P_GPLL0_DIV, 10, 1, 5), 823c2526597SStephen Boyd F(12000000, P_GPLL0_DIV, 1, 1, 25), 824c2526597SStephen Boyd F(13000000, P_GPLL0_DIV, 2, 13, 150), 825c2526597SStephen Boyd F(24000000, P_GPLL0_DIV, 1, 2, 25), 826c2526597SStephen Boyd { } 827c2526597SStephen Boyd }; 828c2526597SStephen Boyd 829c2526597SStephen Boyd static struct clk_rcg2 camss_gp0_clk_src = { 830c2526597SStephen Boyd .cmd_rcgr = 0x3420, 831c2526597SStephen Boyd .mnd_width = 8, 832c2526597SStephen Boyd .hid_width = 5, 833c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 834c2526597SStephen Boyd .freq_tbl = ftbl_camss_gp0_clk_src, 835c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 836c2526597SStephen Boyd .name = "camss_gp0_clk_src", 837c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 838c2526597SStephen Boyd .num_parents = 5, 839c2526597SStephen Boyd .ops = &clk_rcg2_ops, 840c2526597SStephen Boyd }, 841c2526597SStephen Boyd }; 842c2526597SStephen Boyd 843c2526597SStephen Boyd static struct clk_rcg2 camss_gp1_clk_src = { 844c2526597SStephen Boyd .cmd_rcgr = 0x3450, 845c2526597SStephen Boyd .mnd_width = 8, 846c2526597SStephen Boyd .hid_width = 5, 847c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 848c2526597SStephen Boyd .freq_tbl = ftbl_camss_gp0_clk_src, 849c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 850c2526597SStephen Boyd .name = "camss_gp1_clk_src", 851c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 852c2526597SStephen Boyd .num_parents = 5, 853c2526597SStephen Boyd .ops = &clk_rcg2_ops, 854c2526597SStephen Boyd }, 855c2526597SStephen Boyd }; 856c2526597SStephen Boyd 857c2526597SStephen Boyd static const struct freq_tbl ftbl_mclk0_clk_src[] = { 858c2526597SStephen Boyd F(4800000, P_XO, 4, 0, 0), 859c2526597SStephen Boyd F(6000000, P_GPLL0_DIV, 10, 1, 5), 860c2526597SStephen Boyd F(8000000, P_GPLL0_DIV, 1, 2, 75), 861c2526597SStephen Boyd F(9600000, P_XO, 2, 0, 0), 862c2526597SStephen Boyd F(16666667, P_GPLL0_DIV, 2, 1, 9), 863c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 864c2526597SStephen Boyd F(24000000, P_GPLL0_DIV, 1, 2, 25), 865c2526597SStephen Boyd F(33333333, P_GPLL0_DIV, 1, 1, 9), 866c2526597SStephen Boyd F(48000000, P_GPLL0, 1, 2, 25), 867c2526597SStephen Boyd F(66666667, P_GPLL0, 1, 1, 9), 868c2526597SStephen Boyd { } 869c2526597SStephen Boyd }; 870c2526597SStephen Boyd 871c2526597SStephen Boyd static struct clk_rcg2 mclk0_clk_src = { 872c2526597SStephen Boyd .cmd_rcgr = 0x3360, 873c2526597SStephen Boyd .mnd_width = 8, 874c2526597SStephen Boyd .hid_width = 5, 875c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 876c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 877c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 878c2526597SStephen Boyd .name = "mclk0_clk_src", 879c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 880c2526597SStephen Boyd .num_parents = 5, 881c2526597SStephen Boyd .ops = &clk_rcg2_ops, 882c2526597SStephen Boyd }, 883c2526597SStephen Boyd }; 884c2526597SStephen Boyd 885c2526597SStephen Boyd static struct clk_rcg2 mclk1_clk_src = { 886c2526597SStephen Boyd .cmd_rcgr = 0x3390, 887c2526597SStephen Boyd .mnd_width = 8, 888c2526597SStephen Boyd .hid_width = 5, 889c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 890c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 891c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 892c2526597SStephen Boyd .name = "mclk1_clk_src", 893c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 894c2526597SStephen Boyd .num_parents = 5, 895c2526597SStephen Boyd .ops = &clk_rcg2_ops, 896c2526597SStephen Boyd }, 897c2526597SStephen Boyd }; 898c2526597SStephen Boyd 899c2526597SStephen Boyd static struct clk_rcg2 mclk2_clk_src = { 900c2526597SStephen Boyd .cmd_rcgr = 0x33c0, 901c2526597SStephen Boyd .mnd_width = 8, 902c2526597SStephen Boyd .hid_width = 5, 903c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 904c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 905c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 906c2526597SStephen Boyd .name = "mclk2_clk_src", 907c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 908c2526597SStephen Boyd .num_parents = 5, 909c2526597SStephen Boyd .ops = &clk_rcg2_ops, 910c2526597SStephen Boyd }, 911c2526597SStephen Boyd }; 912c2526597SStephen Boyd 913c2526597SStephen Boyd static struct clk_rcg2 mclk3_clk_src = { 914c2526597SStephen Boyd .cmd_rcgr = 0x33f0, 915c2526597SStephen Boyd .mnd_width = 8, 916c2526597SStephen Boyd .hid_width = 5, 917c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 918c2526597SStephen Boyd .freq_tbl = ftbl_mclk0_clk_src, 919c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 920c2526597SStephen Boyd .name = "mclk3_clk_src", 921c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 922c2526597SStephen Boyd .num_parents = 5, 923c2526597SStephen Boyd .ops = &clk_rcg2_ops, 924c2526597SStephen Boyd }, 925c2526597SStephen Boyd }; 926c2526597SStephen Boyd 927c2526597SStephen Boyd static const struct freq_tbl ftbl_cci_clk_src[] = { 928c2526597SStephen Boyd F(19200000, P_XO, 1, 0, 0), 929c2526597SStephen Boyd F(37500000, P_GPLL0, 16, 0, 0), 930c2526597SStephen Boyd F(50000000, P_GPLL0, 12, 0, 0), 931c2526597SStephen Boyd F(100000000, P_GPLL0, 6, 0, 0), 932c2526597SStephen Boyd { } 933c2526597SStephen Boyd }; 934c2526597SStephen Boyd 935c2526597SStephen Boyd static struct clk_rcg2 cci_clk_src = { 936c2526597SStephen Boyd .cmd_rcgr = 0x3300, 937c2526597SStephen Boyd .mnd_width = 8, 938c2526597SStephen Boyd .hid_width = 5, 939c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 940c2526597SStephen Boyd .freq_tbl = ftbl_cci_clk_src, 941c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 942c2526597SStephen Boyd .name = "cci_clk_src", 943c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 944c2526597SStephen Boyd .num_parents = 5, 945c2526597SStephen Boyd .ops = &clk_rcg2_ops, 946c2526597SStephen Boyd }, 947c2526597SStephen Boyd }; 948c2526597SStephen Boyd 949c2526597SStephen Boyd static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { 950c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 951c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 952c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 953c2526597SStephen Boyd { } 954c2526597SStephen Boyd }; 955c2526597SStephen Boyd 956c2526597SStephen Boyd static struct clk_rcg2 csi0phytimer_clk_src = { 957c2526597SStephen Boyd .cmd_rcgr = 0x3000, 958c2526597SStephen Boyd .hid_width = 5, 959c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 960c2526597SStephen Boyd .freq_tbl = ftbl_csi0phytimer_clk_src, 961c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 962c2526597SStephen Boyd .name = "csi0phytimer_clk_src", 963c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 964c2526597SStephen Boyd .num_parents = 7, 965c2526597SStephen Boyd .ops = &clk_rcg2_ops, 966c2526597SStephen Boyd }, 967c2526597SStephen Boyd }; 968c2526597SStephen Boyd 969c2526597SStephen Boyd static struct clk_rcg2 csi1phytimer_clk_src = { 970c2526597SStephen Boyd .cmd_rcgr = 0x3030, 971c2526597SStephen Boyd .hid_width = 5, 972c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 973c2526597SStephen Boyd .freq_tbl = ftbl_csi0phytimer_clk_src, 974c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 975c2526597SStephen Boyd .name = "csi1phytimer_clk_src", 976c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 977c2526597SStephen Boyd .num_parents = 7, 978c2526597SStephen Boyd .ops = &clk_rcg2_ops, 979c2526597SStephen Boyd }, 980c2526597SStephen Boyd }; 981c2526597SStephen Boyd 982c2526597SStephen Boyd static struct clk_rcg2 csi2phytimer_clk_src = { 983c2526597SStephen Boyd .cmd_rcgr = 0x3060, 984c2526597SStephen Boyd .hid_width = 5, 985c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 986c2526597SStephen Boyd .freq_tbl = ftbl_csi0phytimer_clk_src, 987c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 988c2526597SStephen Boyd .name = "csi2phytimer_clk_src", 989c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 990c2526597SStephen Boyd .num_parents = 7, 991c2526597SStephen Boyd .ops = &clk_rcg2_ops, 992c2526597SStephen Boyd }, 993c2526597SStephen Boyd }; 994c2526597SStephen Boyd 995c2526597SStephen Boyd static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = { 996c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 997c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 998c2526597SStephen Boyd F(320000000, P_MMPLL4, 3, 0, 0), 999c2526597SStephen Boyd F(384000000, P_MMPLL4, 2.5, 0, 0), 1000c2526597SStephen Boyd { } 1001c2526597SStephen Boyd }; 1002c2526597SStephen Boyd 1003c2526597SStephen Boyd static struct clk_rcg2 csiphy0_3p_clk_src = { 1004c2526597SStephen Boyd .cmd_rcgr = 0x3240, 1005c2526597SStephen Boyd .hid_width = 5, 1006c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1007c2526597SStephen Boyd .freq_tbl = ftbl_csiphy0_3p_clk_src, 1008c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1009c2526597SStephen Boyd .name = "csiphy0_3p_clk_src", 1010c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1011c2526597SStephen Boyd .num_parents = 7, 1012c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1013c2526597SStephen Boyd }, 1014c2526597SStephen Boyd }; 1015c2526597SStephen Boyd 1016c2526597SStephen Boyd static struct clk_rcg2 csiphy1_3p_clk_src = { 1017c2526597SStephen Boyd .cmd_rcgr = 0x3260, 1018c2526597SStephen Boyd .hid_width = 5, 1019c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1020c2526597SStephen Boyd .freq_tbl = ftbl_csiphy0_3p_clk_src, 1021c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1022c2526597SStephen Boyd .name = "csiphy1_3p_clk_src", 1023c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1024c2526597SStephen Boyd .num_parents = 7, 1025c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1026c2526597SStephen Boyd }, 1027c2526597SStephen Boyd }; 1028c2526597SStephen Boyd 1029c2526597SStephen Boyd static struct clk_rcg2 csiphy2_3p_clk_src = { 1030c2526597SStephen Boyd .cmd_rcgr = 0x3280, 1031c2526597SStephen Boyd .hid_width = 5, 1032c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1033c2526597SStephen Boyd .freq_tbl = ftbl_csiphy0_3p_clk_src, 1034c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1035c2526597SStephen Boyd .name = "csiphy2_3p_clk_src", 1036c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1037c2526597SStephen Boyd .num_parents = 7, 1038c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1039c2526597SStephen Boyd }, 1040c2526597SStephen Boyd }; 1041c2526597SStephen Boyd 1042c2526597SStephen Boyd static const struct freq_tbl ftbl_jpeg0_clk_src[] = { 1043c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 1044c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 1045c2526597SStephen Boyd F(228571429, P_MMPLL0, 3.5, 0, 0), 1046c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 1047c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1048c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1049c2526597SStephen Boyd { } 1050c2526597SStephen Boyd }; 1051c2526597SStephen Boyd 1052c2526597SStephen Boyd static struct clk_rcg2 jpeg0_clk_src = { 1053c2526597SStephen Boyd .cmd_rcgr = 0x3500, 1054c2526597SStephen Boyd .hid_width = 5, 1055c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1056c2526597SStephen Boyd .freq_tbl = ftbl_jpeg0_clk_src, 1057c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1058c2526597SStephen Boyd .name = "jpeg0_clk_src", 1059c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1060c2526597SStephen Boyd .num_parents = 7, 1061c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1062c2526597SStephen Boyd }, 1063c2526597SStephen Boyd }; 1064c2526597SStephen Boyd 1065c2526597SStephen Boyd static const struct freq_tbl ftbl_jpeg2_clk_src[] = { 1066c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 1067c2526597SStephen Boyd F(150000000, P_GPLL0, 4, 0, 0), 1068c2526597SStephen Boyd F(228571429, P_MMPLL0, 3.5, 0, 0), 1069c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 1070c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1071c2526597SStephen Boyd { } 1072c2526597SStephen Boyd }; 1073c2526597SStephen Boyd 1074c2526597SStephen Boyd static struct clk_rcg2 jpeg2_clk_src = { 1075c2526597SStephen Boyd .cmd_rcgr = 0x3540, 1076c2526597SStephen Boyd .hid_width = 5, 1077c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1078c2526597SStephen Boyd .freq_tbl = ftbl_jpeg2_clk_src, 1079c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1080c2526597SStephen Boyd .name = "jpeg2_clk_src", 1081c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1082c2526597SStephen Boyd .num_parents = 7, 1083c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1084c2526597SStephen Boyd }, 1085c2526597SStephen Boyd }; 1086c2526597SStephen Boyd 1087c2526597SStephen Boyd static struct clk_rcg2 jpeg_dma_clk_src = { 1088c2526597SStephen Boyd .cmd_rcgr = 0x3560, 1089c2526597SStephen Boyd .hid_width = 5, 1090c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1091c2526597SStephen Boyd .freq_tbl = ftbl_jpeg0_clk_src, 1092c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1093c2526597SStephen Boyd .name = "jpeg_dma_clk_src", 1094c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1095c2526597SStephen Boyd .num_parents = 7, 1096c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1097c2526597SStephen Boyd }, 1098c2526597SStephen Boyd }; 1099c2526597SStephen Boyd 1100c2526597SStephen Boyd static const struct freq_tbl ftbl_vfe0_clk_src[] = { 1101c2526597SStephen Boyd F(75000000, P_GPLL0_DIV, 4, 0, 0), 1102c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1103c2526597SStephen Boyd F(300000000, P_GPLL0, 2, 0, 0), 1104c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1105c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1106c2526597SStephen Boyd F(600000000, P_GPLL0, 1, 0, 0), 1107c2526597SStephen Boyd { } 1108c2526597SStephen Boyd }; 1109c2526597SStephen Boyd 1110c2526597SStephen Boyd static struct clk_rcg2 vfe0_clk_src = { 1111c2526597SStephen Boyd .cmd_rcgr = 0x3600, 1112c2526597SStephen Boyd .hid_width = 5, 1113c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1114c2526597SStephen Boyd .freq_tbl = ftbl_vfe0_clk_src, 1115c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1116c2526597SStephen Boyd .name = "vfe0_clk_src", 1117c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1118c2526597SStephen Boyd .num_parents = 7, 1119c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1120c2526597SStephen Boyd }, 1121c2526597SStephen Boyd }; 1122c2526597SStephen Boyd 1123c2526597SStephen Boyd static struct clk_rcg2 vfe1_clk_src = { 1124c2526597SStephen Boyd .cmd_rcgr = 0x3620, 1125c2526597SStephen Boyd .hid_width = 5, 1126c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1127c2526597SStephen Boyd .freq_tbl = ftbl_vfe0_clk_src, 1128c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1129c2526597SStephen Boyd .name = "vfe1_clk_src", 1130c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1131c2526597SStephen Boyd .num_parents = 7, 1132c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1133c2526597SStephen Boyd }, 1134c2526597SStephen Boyd }; 1135c2526597SStephen Boyd 1136c2526597SStephen Boyd static const struct freq_tbl ftbl_cpp_clk_src[] = { 1137c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1138c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1139c2526597SStephen Boyd F(320000000, P_MMPLL0, 2.5, 0, 0), 1140c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1141c2526597SStephen Boyd F(640000000, P_MMPLL4, 1.5, 0, 0), 1142c2526597SStephen Boyd { } 1143c2526597SStephen Boyd }; 1144c2526597SStephen Boyd 1145c2526597SStephen Boyd static struct clk_rcg2 cpp_clk_src = { 1146c2526597SStephen Boyd .cmd_rcgr = 0x3640, 1147c2526597SStephen Boyd .hid_width = 5, 1148c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1149c2526597SStephen Boyd .freq_tbl = ftbl_cpp_clk_src, 1150c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1151c2526597SStephen Boyd .name = "cpp_clk_src", 1152c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1153c2526597SStephen Boyd .num_parents = 7, 1154c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1155c2526597SStephen Boyd }, 1156c2526597SStephen Boyd }; 1157c2526597SStephen Boyd 1158c2526597SStephen Boyd static const struct freq_tbl ftbl_csi0_clk_src[] = { 1159c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1160c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1161c2526597SStephen Boyd F(266666667, P_MMPLL0, 3, 0, 0), 1162c2526597SStephen Boyd F(480000000, P_MMPLL4, 2, 0, 0), 1163c2526597SStephen Boyd F(600000000, P_GPLL0, 1, 0, 0), 1164c2526597SStephen Boyd { } 1165c2526597SStephen Boyd }; 1166c2526597SStephen Boyd 1167c2526597SStephen Boyd static struct clk_rcg2 csi0_clk_src = { 1168c2526597SStephen Boyd .cmd_rcgr = 0x3090, 1169c2526597SStephen Boyd .hid_width = 5, 1170c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1171c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1172c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1173c2526597SStephen Boyd .name = "csi0_clk_src", 1174c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1175c2526597SStephen Boyd .num_parents = 7, 1176c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1177c2526597SStephen Boyd }, 1178c2526597SStephen Boyd }; 1179c2526597SStephen Boyd 1180c2526597SStephen Boyd static struct clk_rcg2 csi1_clk_src = { 1181c2526597SStephen Boyd .cmd_rcgr = 0x3100, 1182c2526597SStephen Boyd .hid_width = 5, 1183c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1184c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1185c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1186c2526597SStephen Boyd .name = "csi1_clk_src", 1187c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1188c2526597SStephen Boyd .num_parents = 7, 1189c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1190c2526597SStephen Boyd }, 1191c2526597SStephen Boyd }; 1192c2526597SStephen Boyd 1193c2526597SStephen Boyd static struct clk_rcg2 csi2_clk_src = { 1194c2526597SStephen Boyd .cmd_rcgr = 0x3160, 1195c2526597SStephen Boyd .hid_width = 5, 1196c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1197c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1198c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1199c2526597SStephen Boyd .name = "csi2_clk_src", 1200c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1201c2526597SStephen Boyd .num_parents = 7, 1202c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1203c2526597SStephen Boyd }, 1204c2526597SStephen Boyd }; 1205c2526597SStephen Boyd 1206c2526597SStephen Boyd static struct clk_rcg2 csi3_clk_src = { 1207c2526597SStephen Boyd .cmd_rcgr = 0x31c0, 1208c2526597SStephen Boyd .hid_width = 5, 1209c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1210c2526597SStephen Boyd .freq_tbl = ftbl_csi0_clk_src, 1211c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1212c2526597SStephen Boyd .name = "csi3_clk_src", 1213c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1214c2526597SStephen Boyd .num_parents = 7, 1215c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1216c2526597SStephen Boyd }, 1217c2526597SStephen Boyd }; 1218c2526597SStephen Boyd 1219c2526597SStephen Boyd static const struct freq_tbl ftbl_fd_core_clk_src[] = { 1220c2526597SStephen Boyd F(100000000, P_GPLL0_DIV, 3, 0, 0), 1221c2526597SStephen Boyd F(200000000, P_GPLL0, 3, 0, 0), 1222c2526597SStephen Boyd F(400000000, P_MMPLL0, 2, 0, 0), 1223c2526597SStephen Boyd { } 1224c2526597SStephen Boyd }; 1225c2526597SStephen Boyd 1226c2526597SStephen Boyd static struct clk_rcg2 fd_core_clk_src = { 1227c2526597SStephen Boyd .cmd_rcgr = 0x3b00, 1228c2526597SStephen Boyd .hid_width = 5, 1229c2526597SStephen Boyd .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 1230c2526597SStephen Boyd .freq_tbl = ftbl_fd_core_clk_src, 1231c2526597SStephen Boyd .clkr.hw.init = &(struct clk_init_data){ 1232c2526597SStephen Boyd .name = "fd_core_clk_src", 1233c2526597SStephen Boyd .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 1234c2526597SStephen Boyd .num_parents = 5, 1235c2526597SStephen Boyd .ops = &clk_rcg2_ops, 1236c2526597SStephen Boyd }, 1237c2526597SStephen Boyd }; 1238c2526597SStephen Boyd 1239c2526597SStephen Boyd static struct clk_branch mmss_mmagic_ahb_clk = { 1240c2526597SStephen Boyd .halt_reg = 0x5024, 1241c2526597SStephen Boyd .clkr = { 1242c2526597SStephen Boyd .enable_reg = 0x5024, 1243c2526597SStephen Boyd .enable_mask = BIT(0), 1244c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1245c2526597SStephen Boyd .name = "mmss_mmagic_ahb_clk", 1246c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1247c2526597SStephen Boyd .num_parents = 1, 1248c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1249c2526597SStephen Boyd .ops = &clk_branch2_ops, 1250c2526597SStephen Boyd }, 1251c2526597SStephen Boyd }, 1252c2526597SStephen Boyd }; 1253c2526597SStephen Boyd 1254c2526597SStephen Boyd static struct clk_branch mmss_mmagic_cfg_ahb_clk = { 1255c2526597SStephen Boyd .halt_reg = 0x5054, 1256c2526597SStephen Boyd .clkr = { 1257c2526597SStephen Boyd .enable_reg = 0x5054, 1258c2526597SStephen Boyd .enable_mask = BIT(0), 1259c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1260c2526597SStephen Boyd .name = "mmss_mmagic_cfg_ahb_clk", 1261c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1262c2526597SStephen Boyd .num_parents = 1, 1263c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1264c2526597SStephen Boyd .ops = &clk_branch2_ops, 1265c2526597SStephen Boyd }, 1266c2526597SStephen Boyd }, 1267c2526597SStephen Boyd }; 1268c2526597SStephen Boyd 1269c2526597SStephen Boyd static struct clk_branch mmss_misc_ahb_clk = { 1270c2526597SStephen Boyd .halt_reg = 0x5018, 1271c2526597SStephen Boyd .clkr = { 1272c2526597SStephen Boyd .enable_reg = 0x5018, 1273c2526597SStephen Boyd .enable_mask = BIT(0), 1274c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1275c2526597SStephen Boyd .name = "mmss_misc_ahb_clk", 1276c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1277c2526597SStephen Boyd .num_parents = 1, 1278c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1279c2526597SStephen Boyd .ops = &clk_branch2_ops, 1280c2526597SStephen Boyd }, 1281c2526597SStephen Boyd }, 1282c2526597SStephen Boyd }; 1283c2526597SStephen Boyd 1284c2526597SStephen Boyd static struct clk_branch mmss_misc_cxo_clk = { 1285c2526597SStephen Boyd .halt_reg = 0x5014, 1286c2526597SStephen Boyd .clkr = { 1287c2526597SStephen Boyd .enable_reg = 0x5014, 1288c2526597SStephen Boyd .enable_mask = BIT(0), 1289c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1290c2526597SStephen Boyd .name = "mmss_misc_cxo_clk", 1291c2526597SStephen Boyd .parent_names = (const char *[]){ "xo" }, 1292c2526597SStephen Boyd .num_parents = 1, 1293c2526597SStephen Boyd .ops = &clk_branch2_ops, 1294c2526597SStephen Boyd }, 1295c2526597SStephen Boyd }, 1296c2526597SStephen Boyd }; 1297c2526597SStephen Boyd 1298c2526597SStephen Boyd static struct clk_branch mmss_mmagic_maxi_clk = { 1299c2526597SStephen Boyd .halt_reg = 0x5074, 1300c2526597SStephen Boyd .clkr = { 1301c2526597SStephen Boyd .enable_reg = 0x5074, 1302c2526597SStephen Boyd .enable_mask = BIT(0), 1303c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1304c2526597SStephen Boyd .name = "mmss_mmagic_maxi_clk", 1305c2526597SStephen Boyd .parent_names = (const char *[]){ "maxi_clk_src" }, 1306c2526597SStephen Boyd .num_parents = 1, 1307c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1308c2526597SStephen Boyd .ops = &clk_branch2_ops, 1309c2526597SStephen Boyd }, 1310c2526597SStephen Boyd }, 1311c2526597SStephen Boyd }; 1312c2526597SStephen Boyd 1313c2526597SStephen Boyd static struct clk_branch mmagic_camss_axi_clk = { 1314c2526597SStephen Boyd .halt_reg = 0x3c44, 1315c2526597SStephen Boyd .clkr = { 1316c2526597SStephen Boyd .enable_reg = 0x3c44, 1317c2526597SStephen Boyd .enable_mask = BIT(0), 1318c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1319c2526597SStephen Boyd .name = "mmagic_camss_axi_clk", 1320c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1321c2526597SStephen Boyd .num_parents = 1, 1322c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1323c2526597SStephen Boyd .ops = &clk_branch2_ops, 1324c2526597SStephen Boyd }, 1325c2526597SStephen Boyd }, 1326c2526597SStephen Boyd }; 1327c2526597SStephen Boyd 1328c2526597SStephen Boyd static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = { 1329c2526597SStephen Boyd .halt_reg = 0x3c48, 1330c2526597SStephen Boyd .clkr = { 1331c2526597SStephen Boyd .enable_reg = 0x3c48, 1332c2526597SStephen Boyd .enable_mask = BIT(0), 1333c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1334c2526597SStephen Boyd .name = "mmagic_camss_noc_cfg_ahb_clk", 1335c2526597SStephen Boyd .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1336c2526597SStephen Boyd .num_parents = 1, 1337c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1338c2526597SStephen Boyd .ops = &clk_branch2_ops, 1339c2526597SStephen Boyd }, 1340c2526597SStephen Boyd }, 1341c2526597SStephen Boyd }; 1342c2526597SStephen Boyd 1343c2526597SStephen Boyd static struct clk_branch smmu_vfe_ahb_clk = { 1344c2526597SStephen Boyd .halt_reg = 0x3c04, 1345c2526597SStephen Boyd .clkr = { 1346c2526597SStephen Boyd .enable_reg = 0x3c04, 1347c2526597SStephen Boyd .enable_mask = BIT(0), 1348c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1349c2526597SStephen Boyd .name = "smmu_vfe_ahb_clk", 1350c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1351c2526597SStephen Boyd .num_parents = 1, 1352c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1353c2526597SStephen Boyd .ops = &clk_branch2_ops, 1354c2526597SStephen Boyd }, 1355c2526597SStephen Boyd }, 1356c2526597SStephen Boyd }; 1357c2526597SStephen Boyd 1358c2526597SStephen Boyd static struct clk_branch smmu_vfe_axi_clk = { 1359c2526597SStephen Boyd .halt_reg = 0x3c08, 1360c2526597SStephen Boyd .clkr = { 1361c2526597SStephen Boyd .enable_reg = 0x3c08, 1362c2526597SStephen Boyd .enable_mask = BIT(0), 1363c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1364c2526597SStephen Boyd .name = "smmu_vfe_axi_clk", 1365c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1366c2526597SStephen Boyd .num_parents = 1, 1367c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1368c2526597SStephen Boyd .ops = &clk_branch2_ops, 1369c2526597SStephen Boyd }, 1370c2526597SStephen Boyd }, 1371c2526597SStephen Boyd }; 1372c2526597SStephen Boyd 1373c2526597SStephen Boyd static struct clk_branch smmu_cpp_ahb_clk = { 1374c2526597SStephen Boyd .halt_reg = 0x3c14, 1375c2526597SStephen Boyd .clkr = { 1376c2526597SStephen Boyd .enable_reg = 0x3c14, 1377c2526597SStephen Boyd .enable_mask = BIT(0), 1378c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1379c2526597SStephen Boyd .name = "smmu_cpp_ahb_clk", 1380c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1381c2526597SStephen Boyd .num_parents = 1, 1382c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1383c2526597SStephen Boyd .ops = &clk_branch2_ops, 1384c2526597SStephen Boyd }, 1385c2526597SStephen Boyd }, 1386c2526597SStephen Boyd }; 1387c2526597SStephen Boyd 1388c2526597SStephen Boyd static struct clk_branch smmu_cpp_axi_clk = { 1389c2526597SStephen Boyd .halt_reg = 0x3c18, 1390c2526597SStephen Boyd .clkr = { 1391c2526597SStephen Boyd .enable_reg = 0x3c18, 1392c2526597SStephen Boyd .enable_mask = BIT(0), 1393c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1394c2526597SStephen Boyd .name = "smmu_cpp_axi_clk", 1395c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1396c2526597SStephen Boyd .num_parents = 1, 1397c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1398c2526597SStephen Boyd .ops = &clk_branch2_ops, 1399c2526597SStephen Boyd }, 1400c2526597SStephen Boyd }, 1401c2526597SStephen Boyd }; 1402c2526597SStephen Boyd 1403c2526597SStephen Boyd static struct clk_branch smmu_jpeg_ahb_clk = { 1404c2526597SStephen Boyd .halt_reg = 0x3c24, 1405c2526597SStephen Boyd .clkr = { 1406c2526597SStephen Boyd .enable_reg = 0x3c24, 1407c2526597SStephen Boyd .enable_mask = BIT(0), 1408c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1409c2526597SStephen Boyd .name = "smmu_jpeg_ahb_clk", 1410c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1411c2526597SStephen Boyd .num_parents = 1, 1412c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1413c2526597SStephen Boyd .ops = &clk_branch2_ops, 1414c2526597SStephen Boyd }, 1415c2526597SStephen Boyd }, 1416c2526597SStephen Boyd }; 1417c2526597SStephen Boyd 1418c2526597SStephen Boyd static struct clk_branch smmu_jpeg_axi_clk = { 1419c2526597SStephen Boyd .halt_reg = 0x3c28, 1420c2526597SStephen Boyd .clkr = { 1421c2526597SStephen Boyd .enable_reg = 0x3c28, 1422c2526597SStephen Boyd .enable_mask = BIT(0), 1423c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1424c2526597SStephen Boyd .name = "smmu_jpeg_axi_clk", 1425c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1426c2526597SStephen Boyd .num_parents = 1, 1427c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1428c2526597SStephen Boyd .ops = &clk_branch2_ops, 1429c2526597SStephen Boyd }, 1430c2526597SStephen Boyd }, 1431c2526597SStephen Boyd }; 1432c2526597SStephen Boyd 1433c2526597SStephen Boyd static struct clk_branch mmagic_mdss_axi_clk = { 1434c2526597SStephen Boyd .halt_reg = 0x2474, 1435c2526597SStephen Boyd .clkr = { 1436c2526597SStephen Boyd .enable_reg = 0x2474, 1437c2526597SStephen Boyd .enable_mask = BIT(0), 1438c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1439c2526597SStephen Boyd .name = "mmagic_mdss_axi_clk", 1440c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1441c2526597SStephen Boyd .num_parents = 1, 1442c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1443c2526597SStephen Boyd .ops = &clk_branch2_ops, 1444c2526597SStephen Boyd }, 1445c2526597SStephen Boyd }, 1446c2526597SStephen Boyd }; 1447c2526597SStephen Boyd 1448c2526597SStephen Boyd static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = { 1449c2526597SStephen Boyd .halt_reg = 0x2478, 1450c2526597SStephen Boyd .clkr = { 1451c2526597SStephen Boyd .enable_reg = 0x2478, 1452c2526597SStephen Boyd .enable_mask = BIT(0), 1453c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1454c2526597SStephen Boyd .name = "mmagic_mdss_noc_cfg_ahb_clk", 1455c2526597SStephen Boyd .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1456c2526597SStephen Boyd .num_parents = 1, 1457c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1458c2526597SStephen Boyd .ops = &clk_branch2_ops, 1459c2526597SStephen Boyd }, 1460c2526597SStephen Boyd }, 1461c2526597SStephen Boyd }; 1462c2526597SStephen Boyd 1463c2526597SStephen Boyd static struct clk_branch smmu_rot_ahb_clk = { 1464c2526597SStephen Boyd .halt_reg = 0x2444, 1465c2526597SStephen Boyd .clkr = { 1466c2526597SStephen Boyd .enable_reg = 0x2444, 1467c2526597SStephen Boyd .enable_mask = BIT(0), 1468c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1469c2526597SStephen Boyd .name = "smmu_rot_ahb_clk", 1470c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1471c2526597SStephen Boyd .num_parents = 1, 1472c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1473c2526597SStephen Boyd .ops = &clk_branch2_ops, 1474c2526597SStephen Boyd }, 1475c2526597SStephen Boyd }, 1476c2526597SStephen Boyd }; 1477c2526597SStephen Boyd 1478c2526597SStephen Boyd static struct clk_branch smmu_rot_axi_clk = { 1479c2526597SStephen Boyd .halt_reg = 0x2448, 1480c2526597SStephen Boyd .clkr = { 1481c2526597SStephen Boyd .enable_reg = 0x2448, 1482c2526597SStephen Boyd .enable_mask = BIT(0), 1483c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1484c2526597SStephen Boyd .name = "smmu_rot_axi_clk", 1485c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1486c2526597SStephen Boyd .num_parents = 1, 1487c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1488c2526597SStephen Boyd .ops = &clk_branch2_ops, 1489c2526597SStephen Boyd }, 1490c2526597SStephen Boyd }, 1491c2526597SStephen Boyd }; 1492c2526597SStephen Boyd 1493c2526597SStephen Boyd static struct clk_branch smmu_mdp_ahb_clk = { 1494c2526597SStephen Boyd .halt_reg = 0x2454, 1495c2526597SStephen Boyd .clkr = { 1496c2526597SStephen Boyd .enable_reg = 0x2454, 1497c2526597SStephen Boyd .enable_mask = BIT(0), 1498c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1499c2526597SStephen Boyd .name = "smmu_mdp_ahb_clk", 1500c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1501c2526597SStephen Boyd .num_parents = 1, 1502c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1503c2526597SStephen Boyd .ops = &clk_branch2_ops, 1504c2526597SStephen Boyd }, 1505c2526597SStephen Boyd }, 1506c2526597SStephen Boyd }; 1507c2526597SStephen Boyd 1508c2526597SStephen Boyd static struct clk_branch smmu_mdp_axi_clk = { 1509c2526597SStephen Boyd .halt_reg = 0x2458, 1510c2526597SStephen Boyd .clkr = { 1511c2526597SStephen Boyd .enable_reg = 0x2458, 1512c2526597SStephen Boyd .enable_mask = BIT(0), 1513c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1514c2526597SStephen Boyd .name = "smmu_mdp_axi_clk", 1515c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1516c2526597SStephen Boyd .num_parents = 1, 1517c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1518c2526597SStephen Boyd .ops = &clk_branch2_ops, 1519c2526597SStephen Boyd }, 1520c2526597SStephen Boyd }, 1521c2526597SStephen Boyd }; 1522c2526597SStephen Boyd 1523c2526597SStephen Boyd static struct clk_branch mmagic_video_axi_clk = { 1524c2526597SStephen Boyd .halt_reg = 0x1194, 1525c2526597SStephen Boyd .clkr = { 1526c2526597SStephen Boyd .enable_reg = 0x1194, 1527c2526597SStephen Boyd .enable_mask = BIT(0), 1528c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1529c2526597SStephen Boyd .name = "mmagic_video_axi_clk", 1530c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1531c2526597SStephen Boyd .num_parents = 1, 1532c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1533c2526597SStephen Boyd .ops = &clk_branch2_ops, 1534c2526597SStephen Boyd }, 1535c2526597SStephen Boyd }, 1536c2526597SStephen Boyd }; 1537c2526597SStephen Boyd 1538c2526597SStephen Boyd static struct clk_branch mmagic_video_noc_cfg_ahb_clk = { 1539c2526597SStephen Boyd .halt_reg = 0x1198, 1540c2526597SStephen Boyd .clkr = { 1541c2526597SStephen Boyd .enable_reg = 0x1198, 1542c2526597SStephen Boyd .enable_mask = BIT(0), 1543c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1544c2526597SStephen Boyd .name = "mmagic_video_noc_cfg_ahb_clk", 1545c2526597SStephen Boyd .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1546c2526597SStephen Boyd .num_parents = 1, 1547c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1548c2526597SStephen Boyd .ops = &clk_branch2_ops, 1549c2526597SStephen Boyd }, 1550c2526597SStephen Boyd }, 1551c2526597SStephen Boyd }; 1552c2526597SStephen Boyd 1553c2526597SStephen Boyd static struct clk_branch smmu_video_ahb_clk = { 1554c2526597SStephen Boyd .halt_reg = 0x1174, 1555c2526597SStephen Boyd .clkr = { 1556c2526597SStephen Boyd .enable_reg = 0x1174, 1557c2526597SStephen Boyd .enable_mask = BIT(0), 1558c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1559c2526597SStephen Boyd .name = "smmu_video_ahb_clk", 1560c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1561c2526597SStephen Boyd .num_parents = 1, 1562c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1563c2526597SStephen Boyd .ops = &clk_branch2_ops, 1564c2526597SStephen Boyd }, 1565c2526597SStephen Boyd }, 1566c2526597SStephen Boyd }; 1567c2526597SStephen Boyd 1568c2526597SStephen Boyd static struct clk_branch smmu_video_axi_clk = { 1569c2526597SStephen Boyd .halt_reg = 0x1178, 1570c2526597SStephen Boyd .clkr = { 1571c2526597SStephen Boyd .enable_reg = 0x1178, 1572c2526597SStephen Boyd .enable_mask = BIT(0), 1573c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1574c2526597SStephen Boyd .name = "smmu_video_axi_clk", 1575c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1576c2526597SStephen Boyd .num_parents = 1, 1577c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1578c2526597SStephen Boyd .ops = &clk_branch2_ops, 1579c2526597SStephen Boyd }, 1580c2526597SStephen Boyd }, 1581c2526597SStephen Boyd }; 1582c2526597SStephen Boyd 1583c2526597SStephen Boyd static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { 1584c2526597SStephen Boyd .halt_reg = 0x5298, 1585c2526597SStephen Boyd .clkr = { 1586c2526597SStephen Boyd .enable_reg = 0x5298, 1587c2526597SStephen Boyd .enable_mask = BIT(0), 1588c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1589c2526597SStephen Boyd .name = "mmagic_bimc_noc_cfg_ahb_clk", 1590c2526597SStephen Boyd .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1591c2526597SStephen Boyd .num_parents = 1, 1592c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1593c2526597SStephen Boyd .ops = &clk_branch2_ops, 1594c2526597SStephen Boyd }, 1595c2526597SStephen Boyd }, 1596c2526597SStephen Boyd }; 1597c2526597SStephen Boyd 1598c2526597SStephen Boyd static struct clk_branch gpu_gx_gfx3d_clk = { 1599c2526597SStephen Boyd .halt_reg = 0x4028, 1600c2526597SStephen Boyd .clkr = { 1601c2526597SStephen Boyd .enable_reg = 0x4028, 1602c2526597SStephen Boyd .enable_mask = BIT(0), 1603c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1604c2526597SStephen Boyd .name = "gpu_gx_gfx3d_clk", 1605c2526597SStephen Boyd .parent_names = (const char *[]){ "gfx3d_clk_src" }, 1606c2526597SStephen Boyd .num_parents = 1, 1607c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1608c2526597SStephen Boyd .ops = &clk_branch2_ops, 1609c2526597SStephen Boyd }, 1610c2526597SStephen Boyd }, 1611c2526597SStephen Boyd }; 1612c2526597SStephen Boyd 1613c2526597SStephen Boyd static struct clk_branch gpu_gx_rbbmtimer_clk = { 1614c2526597SStephen Boyd .halt_reg = 0x40b0, 1615c2526597SStephen Boyd .clkr = { 1616c2526597SStephen Boyd .enable_reg = 0x40b0, 1617c2526597SStephen Boyd .enable_mask = BIT(0), 1618c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1619c2526597SStephen Boyd .name = "gpu_gx_rbbmtimer_clk", 1620c2526597SStephen Boyd .parent_names = (const char *[]){ "rbbmtimer_clk_src" }, 1621c2526597SStephen Boyd .num_parents = 1, 1622c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1623c2526597SStephen Boyd .ops = &clk_branch2_ops, 1624c2526597SStephen Boyd }, 1625c2526597SStephen Boyd }, 1626c2526597SStephen Boyd }; 1627c2526597SStephen Boyd 1628c2526597SStephen Boyd static struct clk_branch gpu_ahb_clk = { 1629c2526597SStephen Boyd .halt_reg = 0x403c, 1630c2526597SStephen Boyd .clkr = { 1631c2526597SStephen Boyd .enable_reg = 0x403c, 1632c2526597SStephen Boyd .enable_mask = BIT(0), 1633c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1634c2526597SStephen Boyd .name = "gpu_ahb_clk", 1635c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1636c2526597SStephen Boyd .num_parents = 1, 1637c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1638c2526597SStephen Boyd .ops = &clk_branch2_ops, 1639c2526597SStephen Boyd }, 1640c2526597SStephen Boyd }, 1641c2526597SStephen Boyd }; 1642c2526597SStephen Boyd 1643c2526597SStephen Boyd static struct clk_branch gpu_aon_isense_clk = { 1644c2526597SStephen Boyd .halt_reg = 0x4044, 1645c2526597SStephen Boyd .clkr = { 1646c2526597SStephen Boyd .enable_reg = 0x4044, 1647c2526597SStephen Boyd .enable_mask = BIT(0), 1648c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1649c2526597SStephen Boyd .name = "gpu_aon_isense_clk", 1650c2526597SStephen Boyd .parent_names = (const char *[]){ "isense_clk_src" }, 1651c2526597SStephen Boyd .num_parents = 1, 1652c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1653c2526597SStephen Boyd .ops = &clk_branch2_ops, 1654c2526597SStephen Boyd }, 1655c2526597SStephen Boyd }, 1656c2526597SStephen Boyd }; 1657c2526597SStephen Boyd 1658c2526597SStephen Boyd static struct clk_branch vmem_maxi_clk = { 1659c2526597SStephen Boyd .halt_reg = 0x1204, 1660c2526597SStephen Boyd .clkr = { 1661c2526597SStephen Boyd .enable_reg = 0x1204, 1662c2526597SStephen Boyd .enable_mask = BIT(0), 1663c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1664c2526597SStephen Boyd .name = "vmem_maxi_clk", 1665c2526597SStephen Boyd .parent_names = (const char *[]){ "maxi_clk_src" }, 1666c2526597SStephen Boyd .num_parents = 1, 1667c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1668c2526597SStephen Boyd .ops = &clk_branch2_ops, 1669c2526597SStephen Boyd }, 1670c2526597SStephen Boyd }, 1671c2526597SStephen Boyd }; 1672c2526597SStephen Boyd 1673c2526597SStephen Boyd static struct clk_branch vmem_ahb_clk = { 1674c2526597SStephen Boyd .halt_reg = 0x1208, 1675c2526597SStephen Boyd .clkr = { 1676c2526597SStephen Boyd .enable_reg = 0x1208, 1677c2526597SStephen Boyd .enable_mask = BIT(0), 1678c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1679c2526597SStephen Boyd .name = "vmem_ahb_clk", 1680c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1681c2526597SStephen Boyd .num_parents = 1, 1682c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1683c2526597SStephen Boyd .ops = &clk_branch2_ops, 1684c2526597SStephen Boyd }, 1685c2526597SStephen Boyd }, 1686c2526597SStephen Boyd }; 1687c2526597SStephen Boyd 1688c2526597SStephen Boyd static struct clk_branch mmss_rbcpr_clk = { 1689c2526597SStephen Boyd .halt_reg = 0x4084, 1690c2526597SStephen Boyd .clkr = { 1691c2526597SStephen Boyd .enable_reg = 0x4084, 1692c2526597SStephen Boyd .enable_mask = BIT(0), 1693c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1694c2526597SStephen Boyd .name = "mmss_rbcpr_clk", 1695c2526597SStephen Boyd .parent_names = (const char *[]){ "rbcpr_clk_src" }, 1696c2526597SStephen Boyd .num_parents = 1, 1697c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1698c2526597SStephen Boyd .ops = &clk_branch2_ops, 1699c2526597SStephen Boyd }, 1700c2526597SStephen Boyd }, 1701c2526597SStephen Boyd }; 1702c2526597SStephen Boyd 1703c2526597SStephen Boyd static struct clk_branch mmss_rbcpr_ahb_clk = { 1704c2526597SStephen Boyd .halt_reg = 0x4088, 1705c2526597SStephen Boyd .clkr = { 1706c2526597SStephen Boyd .enable_reg = 0x4088, 1707c2526597SStephen Boyd .enable_mask = BIT(0), 1708c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1709c2526597SStephen Boyd .name = "mmss_rbcpr_ahb_clk", 1710c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1711c2526597SStephen Boyd .num_parents = 1, 1712c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1713c2526597SStephen Boyd .ops = &clk_branch2_ops, 1714c2526597SStephen Boyd }, 1715c2526597SStephen Boyd }, 1716c2526597SStephen Boyd }; 1717c2526597SStephen Boyd 1718c2526597SStephen Boyd static struct clk_branch video_core_clk = { 1719c2526597SStephen Boyd .halt_reg = 0x1028, 1720c2526597SStephen Boyd .clkr = { 1721c2526597SStephen Boyd .enable_reg = 0x1028, 1722c2526597SStephen Boyd .enable_mask = BIT(0), 1723c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1724c2526597SStephen Boyd .name = "video_core_clk", 1725c2526597SStephen Boyd .parent_names = (const char *[]){ "video_core_clk_src" }, 1726c2526597SStephen Boyd .num_parents = 1, 1727c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1728c2526597SStephen Boyd .ops = &clk_branch2_ops, 1729c2526597SStephen Boyd }, 1730c2526597SStephen Boyd }, 1731c2526597SStephen Boyd }; 1732c2526597SStephen Boyd 1733c2526597SStephen Boyd static struct clk_branch video_axi_clk = { 1734c2526597SStephen Boyd .halt_reg = 0x1034, 1735c2526597SStephen Boyd .clkr = { 1736c2526597SStephen Boyd .enable_reg = 0x1034, 1737c2526597SStephen Boyd .enable_mask = BIT(0), 1738c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1739c2526597SStephen Boyd .name = "video_axi_clk", 1740c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1741c2526597SStephen Boyd .num_parents = 1, 1742c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1743c2526597SStephen Boyd .ops = &clk_branch2_ops, 1744c2526597SStephen Boyd }, 1745c2526597SStephen Boyd }, 1746c2526597SStephen Boyd }; 1747c2526597SStephen Boyd 1748c2526597SStephen Boyd static struct clk_branch video_maxi_clk = { 1749c2526597SStephen Boyd .halt_reg = 0x1038, 1750c2526597SStephen Boyd .clkr = { 1751c2526597SStephen Boyd .enable_reg = 0x1038, 1752c2526597SStephen Boyd .enable_mask = BIT(0), 1753c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1754c2526597SStephen Boyd .name = "video_maxi_clk", 1755c2526597SStephen Boyd .parent_names = (const char *[]){ "maxi_clk_src" }, 1756c2526597SStephen Boyd .num_parents = 1, 1757c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1758c2526597SStephen Boyd .ops = &clk_branch2_ops, 1759c2526597SStephen Boyd }, 1760c2526597SStephen Boyd }, 1761c2526597SStephen Boyd }; 1762c2526597SStephen Boyd 1763c2526597SStephen Boyd static struct clk_branch video_ahb_clk = { 1764c2526597SStephen Boyd .halt_reg = 0x1030, 1765c2526597SStephen Boyd .clkr = { 1766c2526597SStephen Boyd .enable_reg = 0x1030, 1767c2526597SStephen Boyd .enable_mask = BIT(0), 1768c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1769c2526597SStephen Boyd .name = "video_ahb_clk", 1770c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1771c2526597SStephen Boyd .num_parents = 1, 1772c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1773c2526597SStephen Boyd .ops = &clk_branch2_ops, 1774c2526597SStephen Boyd }, 1775c2526597SStephen Boyd }, 1776c2526597SStephen Boyd }; 1777c2526597SStephen Boyd 1778c2526597SStephen Boyd static struct clk_branch video_subcore0_clk = { 1779c2526597SStephen Boyd .halt_reg = 0x1048, 1780c2526597SStephen Boyd .clkr = { 1781c2526597SStephen Boyd .enable_reg = 0x1048, 1782c2526597SStephen Boyd .enable_mask = BIT(0), 1783c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1784c2526597SStephen Boyd .name = "video_subcore0_clk", 1785c2526597SStephen Boyd .parent_names = (const char *[]){ "video_subcore0_clk_src" }, 1786c2526597SStephen Boyd .num_parents = 1, 1787c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1788c2526597SStephen Boyd .ops = &clk_branch2_ops, 1789c2526597SStephen Boyd }, 1790c2526597SStephen Boyd }, 1791c2526597SStephen Boyd }; 1792c2526597SStephen Boyd 1793c2526597SStephen Boyd static struct clk_branch video_subcore1_clk = { 1794c2526597SStephen Boyd .halt_reg = 0x104c, 1795c2526597SStephen Boyd .clkr = { 1796c2526597SStephen Boyd .enable_reg = 0x104c, 1797c2526597SStephen Boyd .enable_mask = BIT(0), 1798c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1799c2526597SStephen Boyd .name = "video_subcore1_clk", 1800c2526597SStephen Boyd .parent_names = (const char *[]){ "video_subcore1_clk_src" }, 1801c2526597SStephen Boyd .num_parents = 1, 1802c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1803c2526597SStephen Boyd .ops = &clk_branch2_ops, 1804c2526597SStephen Boyd }, 1805c2526597SStephen Boyd }, 1806c2526597SStephen Boyd }; 1807c2526597SStephen Boyd 1808c2526597SStephen Boyd static struct clk_branch mdss_ahb_clk = { 1809c2526597SStephen Boyd .halt_reg = 0x2308, 1810c2526597SStephen Boyd .clkr = { 1811c2526597SStephen Boyd .enable_reg = 0x2308, 1812c2526597SStephen Boyd .enable_mask = BIT(0), 1813c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1814c2526597SStephen Boyd .name = "mdss_ahb_clk", 1815c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1816c2526597SStephen Boyd .num_parents = 1, 1817c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1818c2526597SStephen Boyd .ops = &clk_branch2_ops, 1819c2526597SStephen Boyd }, 1820c2526597SStephen Boyd }, 1821c2526597SStephen Boyd }; 1822c2526597SStephen Boyd 1823c2526597SStephen Boyd static struct clk_branch mdss_hdmi_ahb_clk = { 1824c2526597SStephen Boyd .halt_reg = 0x230c, 1825c2526597SStephen Boyd .clkr = { 1826c2526597SStephen Boyd .enable_reg = 0x230c, 1827c2526597SStephen Boyd .enable_mask = BIT(0), 1828c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1829c2526597SStephen Boyd .name = "mdss_hdmi_ahb_clk", 1830c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 1831c2526597SStephen Boyd .num_parents = 1, 1832c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1833c2526597SStephen Boyd .ops = &clk_branch2_ops, 1834c2526597SStephen Boyd }, 1835c2526597SStephen Boyd }, 1836c2526597SStephen Boyd }; 1837c2526597SStephen Boyd 1838c2526597SStephen Boyd static struct clk_branch mdss_axi_clk = { 1839c2526597SStephen Boyd .halt_reg = 0x2310, 1840c2526597SStephen Boyd .clkr = { 1841c2526597SStephen Boyd .enable_reg = 0x2310, 1842c2526597SStephen Boyd .enable_mask = BIT(0), 1843c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1844c2526597SStephen Boyd .name = "mdss_axi_clk", 1845c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 1846c2526597SStephen Boyd .num_parents = 1, 1847c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1848c2526597SStephen Boyd .ops = &clk_branch2_ops, 1849c2526597SStephen Boyd }, 1850c2526597SStephen Boyd }, 1851c2526597SStephen Boyd }; 1852c2526597SStephen Boyd 1853c2526597SStephen Boyd static struct clk_branch mdss_pclk0_clk = { 1854c2526597SStephen Boyd .halt_reg = 0x2314, 1855c2526597SStephen Boyd .clkr = { 1856c2526597SStephen Boyd .enable_reg = 0x2314, 1857c2526597SStephen Boyd .enable_mask = BIT(0), 1858c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1859c2526597SStephen Boyd .name = "mdss_pclk0_clk", 1860c2526597SStephen Boyd .parent_names = (const char *[]){ "pclk0_clk_src" }, 1861c2526597SStephen Boyd .num_parents = 1, 1862c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1863c2526597SStephen Boyd .ops = &clk_branch2_ops, 1864c2526597SStephen Boyd }, 1865c2526597SStephen Boyd }, 1866c2526597SStephen Boyd }; 1867c2526597SStephen Boyd 1868c2526597SStephen Boyd static struct clk_branch mdss_pclk1_clk = { 1869c2526597SStephen Boyd .halt_reg = 0x2318, 1870c2526597SStephen Boyd .clkr = { 1871c2526597SStephen Boyd .enable_reg = 0x2318, 1872c2526597SStephen Boyd .enable_mask = BIT(0), 1873c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1874c2526597SStephen Boyd .name = "mdss_pclk1_clk", 1875c2526597SStephen Boyd .parent_names = (const char *[]){ "pclk1_clk_src" }, 1876c2526597SStephen Boyd .num_parents = 1, 1877c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1878c2526597SStephen Boyd .ops = &clk_branch2_ops, 1879c2526597SStephen Boyd }, 1880c2526597SStephen Boyd }, 1881c2526597SStephen Boyd }; 1882c2526597SStephen Boyd 1883c2526597SStephen Boyd static struct clk_branch mdss_mdp_clk = { 1884c2526597SStephen Boyd .halt_reg = 0x231c, 1885c2526597SStephen Boyd .clkr = { 1886c2526597SStephen Boyd .enable_reg = 0x231c, 1887c2526597SStephen Boyd .enable_mask = BIT(0), 1888c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1889c2526597SStephen Boyd .name = "mdss_mdp_clk", 1890c2526597SStephen Boyd .parent_names = (const char *[]){ "mdp_clk_src" }, 1891c2526597SStephen Boyd .num_parents = 1, 1892c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1893c2526597SStephen Boyd .ops = &clk_branch2_ops, 1894c2526597SStephen Boyd }, 1895c2526597SStephen Boyd }, 1896c2526597SStephen Boyd }; 1897c2526597SStephen Boyd 1898c2526597SStephen Boyd static struct clk_branch mdss_extpclk_clk = { 1899c2526597SStephen Boyd .halt_reg = 0x2324, 1900c2526597SStephen Boyd .clkr = { 1901c2526597SStephen Boyd .enable_reg = 0x2324, 1902c2526597SStephen Boyd .enable_mask = BIT(0), 1903c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1904c2526597SStephen Boyd .name = "mdss_extpclk_clk", 1905c2526597SStephen Boyd .parent_names = (const char *[]){ "extpclk_clk_src" }, 1906c2526597SStephen Boyd .num_parents = 1, 1907c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1908c2526597SStephen Boyd .ops = &clk_branch2_ops, 1909c2526597SStephen Boyd }, 1910c2526597SStephen Boyd }, 1911c2526597SStephen Boyd }; 1912c2526597SStephen Boyd 1913c2526597SStephen Boyd static struct clk_branch mdss_vsync_clk = { 1914c2526597SStephen Boyd .halt_reg = 0x2328, 1915c2526597SStephen Boyd .clkr = { 1916c2526597SStephen Boyd .enable_reg = 0x2328, 1917c2526597SStephen Boyd .enable_mask = BIT(0), 1918c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1919c2526597SStephen Boyd .name = "mdss_vsync_clk", 1920c2526597SStephen Boyd .parent_names = (const char *[]){ "vsync_clk_src" }, 1921c2526597SStephen Boyd .num_parents = 1, 1922c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1923c2526597SStephen Boyd .ops = &clk_branch2_ops, 1924c2526597SStephen Boyd }, 1925c2526597SStephen Boyd }, 1926c2526597SStephen Boyd }; 1927c2526597SStephen Boyd 1928c2526597SStephen Boyd static struct clk_branch mdss_hdmi_clk = { 1929c2526597SStephen Boyd .halt_reg = 0x2338, 1930c2526597SStephen Boyd .clkr = { 1931c2526597SStephen Boyd .enable_reg = 0x2338, 1932c2526597SStephen Boyd .enable_mask = BIT(0), 1933c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1934c2526597SStephen Boyd .name = "mdss_hdmi_clk", 1935c2526597SStephen Boyd .parent_names = (const char *[]){ "hdmi_clk_src" }, 1936c2526597SStephen Boyd .num_parents = 1, 1937c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1938c2526597SStephen Boyd .ops = &clk_branch2_ops, 1939c2526597SStephen Boyd }, 1940c2526597SStephen Boyd }, 1941c2526597SStephen Boyd }; 1942c2526597SStephen Boyd 1943c2526597SStephen Boyd static struct clk_branch mdss_byte0_clk = { 1944c2526597SStephen Boyd .halt_reg = 0x233c, 1945c2526597SStephen Boyd .clkr = { 1946c2526597SStephen Boyd .enable_reg = 0x233c, 1947c2526597SStephen Boyd .enable_mask = BIT(0), 1948c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1949c2526597SStephen Boyd .name = "mdss_byte0_clk", 1950c2526597SStephen Boyd .parent_names = (const char *[]){ "byte0_clk_src" }, 1951c2526597SStephen Boyd .num_parents = 1, 1952c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1953c2526597SStephen Boyd .ops = &clk_branch2_ops, 1954c2526597SStephen Boyd }, 1955c2526597SStephen Boyd }, 1956c2526597SStephen Boyd }; 1957c2526597SStephen Boyd 1958c2526597SStephen Boyd static struct clk_branch mdss_byte1_clk = { 1959c2526597SStephen Boyd .halt_reg = 0x2340, 1960c2526597SStephen Boyd .clkr = { 1961c2526597SStephen Boyd .enable_reg = 0x2340, 1962c2526597SStephen Boyd .enable_mask = BIT(0), 1963c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1964c2526597SStephen Boyd .name = "mdss_byte1_clk", 1965c2526597SStephen Boyd .parent_names = (const char *[]){ "byte1_clk_src" }, 1966c2526597SStephen Boyd .num_parents = 1, 1967c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1968c2526597SStephen Boyd .ops = &clk_branch2_ops, 1969c2526597SStephen Boyd }, 1970c2526597SStephen Boyd }, 1971c2526597SStephen Boyd }; 1972c2526597SStephen Boyd 1973c2526597SStephen Boyd static struct clk_branch mdss_esc0_clk = { 1974c2526597SStephen Boyd .halt_reg = 0x2344, 1975c2526597SStephen Boyd .clkr = { 1976c2526597SStephen Boyd .enable_reg = 0x2344, 1977c2526597SStephen Boyd .enable_mask = BIT(0), 1978c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1979c2526597SStephen Boyd .name = "mdss_esc0_clk", 1980c2526597SStephen Boyd .parent_names = (const char *[]){ "esc0_clk_src" }, 1981c2526597SStephen Boyd .num_parents = 1, 1982c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1983c2526597SStephen Boyd .ops = &clk_branch2_ops, 1984c2526597SStephen Boyd }, 1985c2526597SStephen Boyd }, 1986c2526597SStephen Boyd }; 1987c2526597SStephen Boyd 1988c2526597SStephen Boyd static struct clk_branch mdss_esc1_clk = { 1989c2526597SStephen Boyd .halt_reg = 0x2348, 1990c2526597SStephen Boyd .clkr = { 1991c2526597SStephen Boyd .enable_reg = 0x2348, 1992c2526597SStephen Boyd .enable_mask = BIT(0), 1993c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 1994c2526597SStephen Boyd .name = "mdss_esc1_clk", 1995c2526597SStephen Boyd .parent_names = (const char *[]){ "esc1_clk_src" }, 1996c2526597SStephen Boyd .num_parents = 1, 1997c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 1998c2526597SStephen Boyd .ops = &clk_branch2_ops, 1999c2526597SStephen Boyd }, 2000c2526597SStephen Boyd }, 2001c2526597SStephen Boyd }; 2002c2526597SStephen Boyd 2003c2526597SStephen Boyd static struct clk_branch camss_top_ahb_clk = { 2004c2526597SStephen Boyd .halt_reg = 0x3484, 2005c2526597SStephen Boyd .clkr = { 2006c2526597SStephen Boyd .enable_reg = 0x3484, 2007c2526597SStephen Boyd .enable_mask = BIT(0), 2008c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2009c2526597SStephen Boyd .name = "camss_top_ahb_clk", 2010c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2011c2526597SStephen Boyd .num_parents = 1, 2012c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2013c2526597SStephen Boyd .ops = &clk_branch2_ops, 2014c2526597SStephen Boyd }, 2015c2526597SStephen Boyd }, 2016c2526597SStephen Boyd }; 2017c2526597SStephen Boyd 2018c2526597SStephen Boyd static struct clk_branch camss_ahb_clk = { 2019c2526597SStephen Boyd .halt_reg = 0x348c, 2020c2526597SStephen Boyd .clkr = { 2021c2526597SStephen Boyd .enable_reg = 0x348c, 2022c2526597SStephen Boyd .enable_mask = BIT(0), 2023c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2024c2526597SStephen Boyd .name = "camss_ahb_clk", 2025c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2026c2526597SStephen Boyd .num_parents = 1, 2027c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2028c2526597SStephen Boyd .ops = &clk_branch2_ops, 2029c2526597SStephen Boyd }, 2030c2526597SStephen Boyd }, 2031c2526597SStephen Boyd }; 2032c2526597SStephen Boyd 2033c2526597SStephen Boyd static struct clk_branch camss_micro_ahb_clk = { 2034c2526597SStephen Boyd .halt_reg = 0x3494, 2035c2526597SStephen Boyd .clkr = { 2036c2526597SStephen Boyd .enable_reg = 0x3494, 2037c2526597SStephen Boyd .enable_mask = BIT(0), 2038c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2039c2526597SStephen Boyd .name = "camss_micro_ahb_clk", 2040c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2041c2526597SStephen Boyd .num_parents = 1, 2042c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2043c2526597SStephen Boyd .ops = &clk_branch2_ops, 2044c2526597SStephen Boyd }, 2045c2526597SStephen Boyd }, 2046c2526597SStephen Boyd }; 2047c2526597SStephen Boyd 2048c2526597SStephen Boyd static struct clk_branch camss_gp0_clk = { 2049c2526597SStephen Boyd .halt_reg = 0x3444, 2050c2526597SStephen Boyd .clkr = { 2051c2526597SStephen Boyd .enable_reg = 0x3444, 2052c2526597SStephen Boyd .enable_mask = BIT(0), 2053c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2054c2526597SStephen Boyd .name = "camss_gp0_clk", 2055c2526597SStephen Boyd .parent_names = (const char *[]){ "camss_gp0_clk_src" }, 2056c2526597SStephen Boyd .num_parents = 1, 2057c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2058c2526597SStephen Boyd .ops = &clk_branch2_ops, 2059c2526597SStephen Boyd }, 2060c2526597SStephen Boyd }, 2061c2526597SStephen Boyd }; 2062c2526597SStephen Boyd 2063c2526597SStephen Boyd static struct clk_branch camss_gp1_clk = { 2064c2526597SStephen Boyd .halt_reg = 0x3474, 2065c2526597SStephen Boyd .clkr = { 2066c2526597SStephen Boyd .enable_reg = 0x3474, 2067c2526597SStephen Boyd .enable_mask = BIT(0), 2068c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2069c2526597SStephen Boyd .name = "camss_gp1_clk", 2070c2526597SStephen Boyd .parent_names = (const char *[]){ "camss_gp1_clk_src" }, 2071c2526597SStephen Boyd .num_parents = 1, 2072c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2073c2526597SStephen Boyd .ops = &clk_branch2_ops, 2074c2526597SStephen Boyd }, 2075c2526597SStephen Boyd }, 2076c2526597SStephen Boyd }; 2077c2526597SStephen Boyd 2078c2526597SStephen Boyd static struct clk_branch camss_mclk0_clk = { 2079c2526597SStephen Boyd .halt_reg = 0x3384, 2080c2526597SStephen Boyd .clkr = { 2081c2526597SStephen Boyd .enable_reg = 0x3384, 2082c2526597SStephen Boyd .enable_mask = BIT(0), 2083c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2084c2526597SStephen Boyd .name = "camss_mclk0_clk", 2085c2526597SStephen Boyd .parent_names = (const char *[]){ "mclk0_clk_src" }, 2086c2526597SStephen Boyd .num_parents = 1, 2087c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2088c2526597SStephen Boyd .ops = &clk_branch2_ops, 2089c2526597SStephen Boyd }, 2090c2526597SStephen Boyd }, 2091c2526597SStephen Boyd }; 2092c2526597SStephen Boyd 2093c2526597SStephen Boyd static struct clk_branch camss_mclk1_clk = { 2094c2526597SStephen Boyd .halt_reg = 0x33b4, 2095c2526597SStephen Boyd .clkr = { 2096c2526597SStephen Boyd .enable_reg = 0x33b4, 2097c2526597SStephen Boyd .enable_mask = BIT(0), 2098c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2099c2526597SStephen Boyd .name = "camss_mclk1_clk", 2100c2526597SStephen Boyd .parent_names = (const char *[]){ "mclk1_clk_src" }, 2101c2526597SStephen Boyd .num_parents = 1, 2102c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2103c2526597SStephen Boyd .ops = &clk_branch2_ops, 2104c2526597SStephen Boyd }, 2105c2526597SStephen Boyd }, 2106c2526597SStephen Boyd }; 2107c2526597SStephen Boyd 2108c2526597SStephen Boyd static struct clk_branch camss_mclk2_clk = { 2109c2526597SStephen Boyd .halt_reg = 0x33e4, 2110c2526597SStephen Boyd .clkr = { 2111c2526597SStephen Boyd .enable_reg = 0x33e4, 2112c2526597SStephen Boyd .enable_mask = BIT(0), 2113c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2114c2526597SStephen Boyd .name = "camss_mclk2_clk", 2115c2526597SStephen Boyd .parent_names = (const char *[]){ "mclk2_clk_src" }, 2116c2526597SStephen Boyd .num_parents = 1, 2117c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2118c2526597SStephen Boyd .ops = &clk_branch2_ops, 2119c2526597SStephen Boyd }, 2120c2526597SStephen Boyd }, 2121c2526597SStephen Boyd }; 2122c2526597SStephen Boyd 2123c2526597SStephen Boyd static struct clk_branch camss_mclk3_clk = { 2124c2526597SStephen Boyd .halt_reg = 0x3414, 2125c2526597SStephen Boyd .clkr = { 2126c2526597SStephen Boyd .enable_reg = 0x3414, 2127c2526597SStephen Boyd .enable_mask = BIT(0), 2128c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2129c2526597SStephen Boyd .name = "camss_mclk3_clk", 2130c2526597SStephen Boyd .parent_names = (const char *[]){ "mclk3_clk_src" }, 2131c2526597SStephen Boyd .num_parents = 1, 2132c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2133c2526597SStephen Boyd .ops = &clk_branch2_ops, 2134c2526597SStephen Boyd }, 2135c2526597SStephen Boyd }, 2136c2526597SStephen Boyd }; 2137c2526597SStephen Boyd 2138c2526597SStephen Boyd static struct clk_branch camss_cci_clk = { 2139c2526597SStephen Boyd .halt_reg = 0x3344, 2140c2526597SStephen Boyd .clkr = { 2141c2526597SStephen Boyd .enable_reg = 0x3344, 2142c2526597SStephen Boyd .enable_mask = BIT(0), 2143c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2144c2526597SStephen Boyd .name = "camss_cci_clk", 2145c2526597SStephen Boyd .parent_names = (const char *[]){ "cci_clk_src" }, 2146c2526597SStephen Boyd .num_parents = 1, 2147c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2148c2526597SStephen Boyd .ops = &clk_branch2_ops, 2149c2526597SStephen Boyd }, 2150c2526597SStephen Boyd }, 2151c2526597SStephen Boyd }; 2152c2526597SStephen Boyd 2153c2526597SStephen Boyd static struct clk_branch camss_cci_ahb_clk = { 2154c2526597SStephen Boyd .halt_reg = 0x3348, 2155c2526597SStephen Boyd .clkr = { 2156c2526597SStephen Boyd .enable_reg = 0x3348, 2157c2526597SStephen Boyd .enable_mask = BIT(0), 2158c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2159c2526597SStephen Boyd .name = "camss_cci_ahb_clk", 2160c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2161c2526597SStephen Boyd .num_parents = 1, 2162c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2163c2526597SStephen Boyd .ops = &clk_branch2_ops, 2164c2526597SStephen Boyd }, 2165c2526597SStephen Boyd }, 2166c2526597SStephen Boyd }; 2167c2526597SStephen Boyd 2168c2526597SStephen Boyd static struct clk_branch camss_csi0phytimer_clk = { 2169c2526597SStephen Boyd .halt_reg = 0x3024, 2170c2526597SStephen Boyd .clkr = { 2171c2526597SStephen Boyd .enable_reg = 0x3024, 2172c2526597SStephen Boyd .enable_mask = BIT(0), 2173c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2174c2526597SStephen Boyd .name = "camss_csi0phytimer_clk", 2175c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0phytimer_clk_src" }, 2176c2526597SStephen Boyd .num_parents = 1, 2177c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2178c2526597SStephen Boyd .ops = &clk_branch2_ops, 2179c2526597SStephen Boyd }, 2180c2526597SStephen Boyd }, 2181c2526597SStephen Boyd }; 2182c2526597SStephen Boyd 2183c2526597SStephen Boyd static struct clk_branch camss_csi1phytimer_clk = { 2184c2526597SStephen Boyd .halt_reg = 0x3054, 2185c2526597SStephen Boyd .clkr = { 2186c2526597SStephen Boyd .enable_reg = 0x3054, 2187c2526597SStephen Boyd .enable_mask = BIT(0), 2188c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2189c2526597SStephen Boyd .name = "camss_csi1phytimer_clk", 2190c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1phytimer_clk_src" }, 2191c2526597SStephen Boyd .num_parents = 1, 2192c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2193c2526597SStephen Boyd .ops = &clk_branch2_ops, 2194c2526597SStephen Boyd }, 2195c2526597SStephen Boyd }, 2196c2526597SStephen Boyd }; 2197c2526597SStephen Boyd 2198c2526597SStephen Boyd static struct clk_branch camss_csi2phytimer_clk = { 2199c2526597SStephen Boyd .halt_reg = 0x3084, 2200c2526597SStephen Boyd .clkr = { 2201c2526597SStephen Boyd .enable_reg = 0x3084, 2202c2526597SStephen Boyd .enable_mask = BIT(0), 2203c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2204c2526597SStephen Boyd .name = "camss_csi2phytimer_clk", 2205c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2phytimer_clk_src" }, 2206c2526597SStephen Boyd .num_parents = 1, 2207c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2208c2526597SStephen Boyd .ops = &clk_branch2_ops, 2209c2526597SStephen Boyd }, 2210c2526597SStephen Boyd }, 2211c2526597SStephen Boyd }; 2212c2526597SStephen Boyd 2213c2526597SStephen Boyd static struct clk_branch camss_csiphy0_3p_clk = { 2214c2526597SStephen Boyd .halt_reg = 0x3234, 2215c2526597SStephen Boyd .clkr = { 2216c2526597SStephen Boyd .enable_reg = 0x3234, 2217c2526597SStephen Boyd .enable_mask = BIT(0), 2218c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2219c2526597SStephen Boyd .name = "camss_csiphy0_3p_clk", 2220c2526597SStephen Boyd .parent_names = (const char *[]){ "csiphy0_3p_clk_src" }, 2221c2526597SStephen Boyd .num_parents = 1, 2222c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2223c2526597SStephen Boyd .ops = &clk_branch2_ops, 2224c2526597SStephen Boyd }, 2225c2526597SStephen Boyd }, 2226c2526597SStephen Boyd }; 2227c2526597SStephen Boyd 2228c2526597SStephen Boyd static struct clk_branch camss_csiphy1_3p_clk = { 2229c2526597SStephen Boyd .halt_reg = 0x3254, 2230c2526597SStephen Boyd .clkr = { 2231c2526597SStephen Boyd .enable_reg = 0x3254, 2232c2526597SStephen Boyd .enable_mask = BIT(0), 2233c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2234c2526597SStephen Boyd .name = "camss_csiphy1_3p_clk", 2235c2526597SStephen Boyd .parent_names = (const char *[]){ "csiphy1_3p_clk_src" }, 2236c2526597SStephen Boyd .num_parents = 1, 2237c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2238c2526597SStephen Boyd .ops = &clk_branch2_ops, 2239c2526597SStephen Boyd }, 2240c2526597SStephen Boyd }, 2241c2526597SStephen Boyd }; 2242c2526597SStephen Boyd 2243c2526597SStephen Boyd static struct clk_branch camss_csiphy2_3p_clk = { 2244c2526597SStephen Boyd .halt_reg = 0x3274, 2245c2526597SStephen Boyd .clkr = { 2246c2526597SStephen Boyd .enable_reg = 0x3274, 2247c2526597SStephen Boyd .enable_mask = BIT(0), 2248c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2249c2526597SStephen Boyd .name = "camss_csiphy2_3p_clk", 2250c2526597SStephen Boyd .parent_names = (const char *[]){ "csiphy2_3p_clk_src" }, 2251c2526597SStephen Boyd .num_parents = 1, 2252c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2253c2526597SStephen Boyd .ops = &clk_branch2_ops, 2254c2526597SStephen Boyd }, 2255c2526597SStephen Boyd }, 2256c2526597SStephen Boyd }; 2257c2526597SStephen Boyd 2258c2526597SStephen Boyd static struct clk_branch camss_jpeg0_clk = { 2259c2526597SStephen Boyd .halt_reg = 0x35a8, 2260c2526597SStephen Boyd .clkr = { 2261c2526597SStephen Boyd .enable_reg = 0x35a8, 2262c2526597SStephen Boyd .enable_mask = BIT(0), 2263c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2264c2526597SStephen Boyd .name = "camss_jpeg0_clk", 2265c2526597SStephen Boyd .parent_names = (const char *[]){ "jpeg0_clk_src" }, 2266c2526597SStephen Boyd .num_parents = 1, 2267c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2268c2526597SStephen Boyd .ops = &clk_branch2_ops, 2269c2526597SStephen Boyd }, 2270c2526597SStephen Boyd }, 2271c2526597SStephen Boyd }; 2272c2526597SStephen Boyd 2273c2526597SStephen Boyd static struct clk_branch camss_jpeg2_clk = { 2274c2526597SStephen Boyd .halt_reg = 0x35b0, 2275c2526597SStephen Boyd .clkr = { 2276c2526597SStephen Boyd .enable_reg = 0x35b0, 2277c2526597SStephen Boyd .enable_mask = BIT(0), 2278c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2279c2526597SStephen Boyd .name = "camss_jpeg2_clk", 2280c2526597SStephen Boyd .parent_names = (const char *[]){ "jpeg2_clk_src" }, 2281c2526597SStephen Boyd .num_parents = 1, 2282c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2283c2526597SStephen Boyd .ops = &clk_branch2_ops, 2284c2526597SStephen Boyd }, 2285c2526597SStephen Boyd }, 2286c2526597SStephen Boyd }; 2287c2526597SStephen Boyd 2288c2526597SStephen Boyd static struct clk_branch camss_jpeg_dma_clk = { 2289c2526597SStephen Boyd .halt_reg = 0x35c0, 2290c2526597SStephen Boyd .clkr = { 2291c2526597SStephen Boyd .enable_reg = 0x35c0, 2292c2526597SStephen Boyd .enable_mask = BIT(0), 2293c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2294c2526597SStephen Boyd .name = "camss_jpeg_dma_clk", 2295c2526597SStephen Boyd .parent_names = (const char *[]){ "jpeg_dma_clk_src" }, 2296c2526597SStephen Boyd .num_parents = 1, 2297c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2298c2526597SStephen Boyd .ops = &clk_branch2_ops, 2299c2526597SStephen Boyd }, 2300c2526597SStephen Boyd }, 2301c2526597SStephen Boyd }; 2302c2526597SStephen Boyd 2303c2526597SStephen Boyd static struct clk_branch camss_jpeg_ahb_clk = { 2304c2526597SStephen Boyd .halt_reg = 0x35b4, 2305c2526597SStephen Boyd .clkr = { 2306c2526597SStephen Boyd .enable_reg = 0x35b4, 2307c2526597SStephen Boyd .enable_mask = BIT(0), 2308c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2309c2526597SStephen Boyd .name = "camss_jpeg_ahb_clk", 2310c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2311c2526597SStephen Boyd .num_parents = 1, 2312c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2313c2526597SStephen Boyd .ops = &clk_branch2_ops, 2314c2526597SStephen Boyd }, 2315c2526597SStephen Boyd }, 2316c2526597SStephen Boyd }; 2317c2526597SStephen Boyd 2318c2526597SStephen Boyd static struct clk_branch camss_jpeg_axi_clk = { 2319c2526597SStephen Boyd .halt_reg = 0x35b8, 2320c2526597SStephen Boyd .clkr = { 2321c2526597SStephen Boyd .enable_reg = 0x35b8, 2322c2526597SStephen Boyd .enable_mask = BIT(0), 2323c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2324c2526597SStephen Boyd .name = "camss_jpeg_axi_clk", 2325c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 2326c2526597SStephen Boyd .num_parents = 1, 2327c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2328c2526597SStephen Boyd .ops = &clk_branch2_ops, 2329c2526597SStephen Boyd }, 2330c2526597SStephen Boyd }, 2331c2526597SStephen Boyd }; 2332c2526597SStephen Boyd 2333c2526597SStephen Boyd static struct clk_branch camss_vfe_ahb_clk = { 2334c2526597SStephen Boyd .halt_reg = 0x36b8, 2335c2526597SStephen Boyd .clkr = { 2336c2526597SStephen Boyd .enable_reg = 0x36b8, 2337c2526597SStephen Boyd .enable_mask = BIT(0), 2338c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2339c2526597SStephen Boyd .name = "camss_vfe_ahb_clk", 2340c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2341c2526597SStephen Boyd .num_parents = 1, 2342c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2343c2526597SStephen Boyd .ops = &clk_branch2_ops, 2344c2526597SStephen Boyd }, 2345c2526597SStephen Boyd }, 2346c2526597SStephen Boyd }; 2347c2526597SStephen Boyd 2348c2526597SStephen Boyd static struct clk_branch camss_vfe_axi_clk = { 2349c2526597SStephen Boyd .halt_reg = 0x36bc, 2350c2526597SStephen Boyd .clkr = { 2351c2526597SStephen Boyd .enable_reg = 0x36bc, 2352c2526597SStephen Boyd .enable_mask = BIT(0), 2353c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2354c2526597SStephen Boyd .name = "camss_vfe_axi_clk", 2355c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 2356c2526597SStephen Boyd .num_parents = 1, 2357c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2358c2526597SStephen Boyd .ops = &clk_branch2_ops, 2359c2526597SStephen Boyd }, 2360c2526597SStephen Boyd }, 2361c2526597SStephen Boyd }; 2362c2526597SStephen Boyd 2363c2526597SStephen Boyd static struct clk_branch camss_vfe0_clk = { 2364c2526597SStephen Boyd .halt_reg = 0x36a8, 2365c2526597SStephen Boyd .clkr = { 2366c2526597SStephen Boyd .enable_reg = 0x36a8, 2367c2526597SStephen Boyd .enable_mask = BIT(0), 2368c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2369c2526597SStephen Boyd .name = "camss_vfe0_clk", 2370c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe0_clk_src" }, 2371c2526597SStephen Boyd .num_parents = 1, 2372c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2373c2526597SStephen Boyd .ops = &clk_branch2_ops, 2374c2526597SStephen Boyd }, 2375c2526597SStephen Boyd }, 2376c2526597SStephen Boyd }; 2377c2526597SStephen Boyd 2378c2526597SStephen Boyd static struct clk_branch camss_vfe0_stream_clk = { 2379c2526597SStephen Boyd .halt_reg = 0x3720, 2380c2526597SStephen Boyd .clkr = { 2381c2526597SStephen Boyd .enable_reg = 0x3720, 2382c2526597SStephen Boyd .enable_mask = BIT(0), 2383c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2384c2526597SStephen Boyd .name = "camss_vfe0_stream_clk", 2385c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe0_clk_src" }, 2386c2526597SStephen Boyd .num_parents = 1, 2387c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2388c2526597SStephen Boyd .ops = &clk_branch2_ops, 2389c2526597SStephen Boyd }, 2390c2526597SStephen Boyd }, 2391c2526597SStephen Boyd }; 2392c2526597SStephen Boyd 2393c2526597SStephen Boyd static struct clk_branch camss_vfe0_ahb_clk = { 2394c2526597SStephen Boyd .halt_reg = 0x3668, 2395c2526597SStephen Boyd .clkr = { 2396c2526597SStephen Boyd .enable_reg = 0x3668, 2397c2526597SStephen Boyd .enable_mask = BIT(0), 2398c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2399c2526597SStephen Boyd .name = "camss_vfe0_ahb_clk", 2400c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2401c2526597SStephen Boyd .num_parents = 1, 2402c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2403c2526597SStephen Boyd .ops = &clk_branch2_ops, 2404c2526597SStephen Boyd }, 2405c2526597SStephen Boyd }, 2406c2526597SStephen Boyd }; 2407c2526597SStephen Boyd 2408c2526597SStephen Boyd static struct clk_branch camss_vfe1_clk = { 2409c2526597SStephen Boyd .halt_reg = 0x36ac, 2410c2526597SStephen Boyd .clkr = { 2411c2526597SStephen Boyd .enable_reg = 0x36ac, 2412c2526597SStephen Boyd .enable_mask = BIT(0), 2413c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2414c2526597SStephen Boyd .name = "camss_vfe1_clk", 2415c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe1_clk_src" }, 2416c2526597SStephen Boyd .num_parents = 1, 2417c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2418c2526597SStephen Boyd .ops = &clk_branch2_ops, 2419c2526597SStephen Boyd }, 2420c2526597SStephen Boyd }, 2421c2526597SStephen Boyd }; 2422c2526597SStephen Boyd 2423c2526597SStephen Boyd static struct clk_branch camss_vfe1_stream_clk = { 2424c2526597SStephen Boyd .halt_reg = 0x3724, 2425c2526597SStephen Boyd .clkr = { 2426c2526597SStephen Boyd .enable_reg = 0x3724, 2427c2526597SStephen Boyd .enable_mask = BIT(0), 2428c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2429c2526597SStephen Boyd .name = "camss_vfe1_stream_clk", 2430c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe1_clk_src" }, 2431c2526597SStephen Boyd .num_parents = 1, 2432c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2433c2526597SStephen Boyd .ops = &clk_branch2_ops, 2434c2526597SStephen Boyd }, 2435c2526597SStephen Boyd }, 2436c2526597SStephen Boyd }; 2437c2526597SStephen Boyd 2438c2526597SStephen Boyd static struct clk_branch camss_vfe1_ahb_clk = { 2439c2526597SStephen Boyd .halt_reg = 0x3678, 2440c2526597SStephen Boyd .clkr = { 2441c2526597SStephen Boyd .enable_reg = 0x3678, 2442c2526597SStephen Boyd .enable_mask = BIT(0), 2443c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2444c2526597SStephen Boyd .name = "camss_vfe1_ahb_clk", 2445c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2446c2526597SStephen Boyd .num_parents = 1, 2447c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2448c2526597SStephen Boyd .ops = &clk_branch2_ops, 2449c2526597SStephen Boyd }, 2450c2526597SStephen Boyd }, 2451c2526597SStephen Boyd }; 2452c2526597SStephen Boyd 2453c2526597SStephen Boyd static struct clk_branch camss_csi_vfe0_clk = { 2454c2526597SStephen Boyd .halt_reg = 0x3704, 2455c2526597SStephen Boyd .clkr = { 2456c2526597SStephen Boyd .enable_reg = 0x3704, 2457c2526597SStephen Boyd .enable_mask = BIT(0), 2458c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2459c2526597SStephen Boyd .name = "camss_csi_vfe0_clk", 2460c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe0_clk_src" }, 2461c2526597SStephen Boyd .num_parents = 1, 2462c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2463c2526597SStephen Boyd .ops = &clk_branch2_ops, 2464c2526597SStephen Boyd }, 2465c2526597SStephen Boyd }, 2466c2526597SStephen Boyd }; 2467c2526597SStephen Boyd 2468c2526597SStephen Boyd static struct clk_branch camss_csi_vfe1_clk = { 2469c2526597SStephen Boyd .halt_reg = 0x3714, 2470c2526597SStephen Boyd .clkr = { 2471c2526597SStephen Boyd .enable_reg = 0x3714, 2472c2526597SStephen Boyd .enable_mask = BIT(0), 2473c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2474c2526597SStephen Boyd .name = "camss_csi_vfe1_clk", 2475c2526597SStephen Boyd .parent_names = (const char *[]){ "vfe1_clk_src" }, 2476c2526597SStephen Boyd .num_parents = 1, 2477c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2478c2526597SStephen Boyd .ops = &clk_branch2_ops, 2479c2526597SStephen Boyd }, 2480c2526597SStephen Boyd }, 2481c2526597SStephen Boyd }; 2482c2526597SStephen Boyd 2483c2526597SStephen Boyd static struct clk_branch camss_cpp_vbif_ahb_clk = { 2484c2526597SStephen Boyd .halt_reg = 0x36c8, 2485c2526597SStephen Boyd .clkr = { 2486c2526597SStephen Boyd .enable_reg = 0x36c8, 2487c2526597SStephen Boyd .enable_mask = BIT(0), 2488c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2489c2526597SStephen Boyd .name = "camss_cpp_vbif_ahb_clk", 2490c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2491c2526597SStephen Boyd .num_parents = 1, 2492c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2493c2526597SStephen Boyd .ops = &clk_branch2_ops, 2494c2526597SStephen Boyd }, 2495c2526597SStephen Boyd }, 2496c2526597SStephen Boyd }; 2497c2526597SStephen Boyd 2498c2526597SStephen Boyd static struct clk_branch camss_cpp_axi_clk = { 2499c2526597SStephen Boyd .halt_reg = 0x36c4, 2500c2526597SStephen Boyd .clkr = { 2501c2526597SStephen Boyd .enable_reg = 0x36c4, 2502c2526597SStephen Boyd .enable_mask = BIT(0), 2503c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2504c2526597SStephen Boyd .name = "camss_cpp_axi_clk", 2505c2526597SStephen Boyd .parent_names = (const char *[]){ "axi_clk_src" }, 2506c2526597SStephen Boyd .num_parents = 1, 2507c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2508c2526597SStephen Boyd .ops = &clk_branch2_ops, 2509c2526597SStephen Boyd }, 2510c2526597SStephen Boyd }, 2511c2526597SStephen Boyd }; 2512c2526597SStephen Boyd 2513c2526597SStephen Boyd static struct clk_branch camss_cpp_clk = { 2514c2526597SStephen Boyd .halt_reg = 0x36b0, 2515c2526597SStephen Boyd .clkr = { 2516c2526597SStephen Boyd .enable_reg = 0x36b0, 2517c2526597SStephen Boyd .enable_mask = BIT(0), 2518c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2519c2526597SStephen Boyd .name = "camss_cpp_clk", 2520c2526597SStephen Boyd .parent_names = (const char *[]){ "cpp_clk_src" }, 2521c2526597SStephen Boyd .num_parents = 1, 2522c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2523c2526597SStephen Boyd .ops = &clk_branch2_ops, 2524c2526597SStephen Boyd }, 2525c2526597SStephen Boyd }, 2526c2526597SStephen Boyd }; 2527c2526597SStephen Boyd 2528c2526597SStephen Boyd static struct clk_branch camss_cpp_ahb_clk = { 2529c2526597SStephen Boyd .halt_reg = 0x36b4, 2530c2526597SStephen Boyd .clkr = { 2531c2526597SStephen Boyd .enable_reg = 0x36b4, 2532c2526597SStephen Boyd .enable_mask = BIT(0), 2533c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2534c2526597SStephen Boyd .name = "camss_cpp_ahb_clk", 2535c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2536c2526597SStephen Boyd .num_parents = 1, 2537c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2538c2526597SStephen Boyd .ops = &clk_branch2_ops, 2539c2526597SStephen Boyd }, 2540c2526597SStephen Boyd }, 2541c2526597SStephen Boyd }; 2542c2526597SStephen Boyd 2543c2526597SStephen Boyd static struct clk_branch camss_csi0_clk = { 2544c2526597SStephen Boyd .halt_reg = 0x30b4, 2545c2526597SStephen Boyd .clkr = { 2546c2526597SStephen Boyd .enable_reg = 0x30b4, 2547c2526597SStephen Boyd .enable_mask = BIT(0), 2548c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2549c2526597SStephen Boyd .name = "camss_csi0_clk", 2550c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0_clk_src" }, 2551c2526597SStephen Boyd .num_parents = 1, 2552c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2553c2526597SStephen Boyd .ops = &clk_branch2_ops, 2554c2526597SStephen Boyd }, 2555c2526597SStephen Boyd }, 2556c2526597SStephen Boyd }; 2557c2526597SStephen Boyd 2558c2526597SStephen Boyd static struct clk_branch camss_csi0_ahb_clk = { 2559c2526597SStephen Boyd .halt_reg = 0x30bc, 2560c2526597SStephen Boyd .clkr = { 2561c2526597SStephen Boyd .enable_reg = 0x30bc, 2562c2526597SStephen Boyd .enable_mask = BIT(0), 2563c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2564c2526597SStephen Boyd .name = "camss_csi0_ahb_clk", 2565c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2566c2526597SStephen Boyd .num_parents = 1, 2567c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2568c2526597SStephen Boyd .ops = &clk_branch2_ops, 2569c2526597SStephen Boyd }, 2570c2526597SStephen Boyd }, 2571c2526597SStephen Boyd }; 2572c2526597SStephen Boyd 2573c2526597SStephen Boyd static struct clk_branch camss_csi0phy_clk = { 2574c2526597SStephen Boyd .halt_reg = 0x30c4, 2575c2526597SStephen Boyd .clkr = { 2576c2526597SStephen Boyd .enable_reg = 0x30c4, 2577c2526597SStephen Boyd .enable_mask = BIT(0), 2578c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2579c2526597SStephen Boyd .name = "camss_csi0phy_clk", 2580c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0_clk_src" }, 2581c2526597SStephen Boyd .num_parents = 1, 2582c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2583c2526597SStephen Boyd .ops = &clk_branch2_ops, 2584c2526597SStephen Boyd }, 2585c2526597SStephen Boyd }, 2586c2526597SStephen Boyd }; 2587c2526597SStephen Boyd 2588c2526597SStephen Boyd static struct clk_branch camss_csi0rdi_clk = { 2589c2526597SStephen Boyd .halt_reg = 0x30d4, 2590c2526597SStephen Boyd .clkr = { 2591c2526597SStephen Boyd .enable_reg = 0x30d4, 2592c2526597SStephen Boyd .enable_mask = BIT(0), 2593c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2594c2526597SStephen Boyd .name = "camss_csi0rdi_clk", 2595c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0_clk_src" }, 2596c2526597SStephen Boyd .num_parents = 1, 2597c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2598c2526597SStephen Boyd .ops = &clk_branch2_ops, 2599c2526597SStephen Boyd }, 2600c2526597SStephen Boyd }, 2601c2526597SStephen Boyd }; 2602c2526597SStephen Boyd 2603c2526597SStephen Boyd static struct clk_branch camss_csi0pix_clk = { 2604c2526597SStephen Boyd .halt_reg = 0x30e4, 2605c2526597SStephen Boyd .clkr = { 2606c2526597SStephen Boyd .enable_reg = 0x30e4, 2607c2526597SStephen Boyd .enable_mask = BIT(0), 2608c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2609c2526597SStephen Boyd .name = "camss_csi0pix_clk", 2610c2526597SStephen Boyd .parent_names = (const char *[]){ "csi0_clk_src" }, 2611c2526597SStephen Boyd .num_parents = 1, 2612c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2613c2526597SStephen Boyd .ops = &clk_branch2_ops, 2614c2526597SStephen Boyd }, 2615c2526597SStephen Boyd }, 2616c2526597SStephen Boyd }; 2617c2526597SStephen Boyd 2618c2526597SStephen Boyd static struct clk_branch camss_csi1_clk = { 2619c2526597SStephen Boyd .halt_reg = 0x3124, 2620c2526597SStephen Boyd .clkr = { 2621c2526597SStephen Boyd .enable_reg = 0x3124, 2622c2526597SStephen Boyd .enable_mask = BIT(0), 2623c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2624c2526597SStephen Boyd .name = "camss_csi1_clk", 2625c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1_clk_src" }, 2626c2526597SStephen Boyd .num_parents = 1, 2627c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2628c2526597SStephen Boyd .ops = &clk_branch2_ops, 2629c2526597SStephen Boyd }, 2630c2526597SStephen Boyd }, 2631c2526597SStephen Boyd }; 2632c2526597SStephen Boyd 2633c2526597SStephen Boyd static struct clk_branch camss_csi1_ahb_clk = { 2634c2526597SStephen Boyd .halt_reg = 0x3128, 2635c2526597SStephen Boyd .clkr = { 2636c2526597SStephen Boyd .enable_reg = 0x3128, 2637c2526597SStephen Boyd .enable_mask = BIT(0), 2638c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2639c2526597SStephen Boyd .name = "camss_csi1_ahb_clk", 2640c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2641c2526597SStephen Boyd .num_parents = 1, 2642c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2643c2526597SStephen Boyd .ops = &clk_branch2_ops, 2644c2526597SStephen Boyd }, 2645c2526597SStephen Boyd }, 2646c2526597SStephen Boyd }; 2647c2526597SStephen Boyd 2648c2526597SStephen Boyd static struct clk_branch camss_csi1phy_clk = { 2649c2526597SStephen Boyd .halt_reg = 0x3134, 2650c2526597SStephen Boyd .clkr = { 2651c2526597SStephen Boyd .enable_reg = 0x3134, 2652c2526597SStephen Boyd .enable_mask = BIT(0), 2653c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2654c2526597SStephen Boyd .name = "camss_csi1phy_clk", 2655c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1_clk_src" }, 2656c2526597SStephen Boyd .num_parents = 1, 2657c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2658c2526597SStephen Boyd .ops = &clk_branch2_ops, 2659c2526597SStephen Boyd }, 2660c2526597SStephen Boyd }, 2661c2526597SStephen Boyd }; 2662c2526597SStephen Boyd 2663c2526597SStephen Boyd static struct clk_branch camss_csi1rdi_clk = { 2664c2526597SStephen Boyd .halt_reg = 0x3144, 2665c2526597SStephen Boyd .clkr = { 2666c2526597SStephen Boyd .enable_reg = 0x3144, 2667c2526597SStephen Boyd .enable_mask = BIT(0), 2668c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2669c2526597SStephen Boyd .name = "camss_csi1rdi_clk", 2670c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1_clk_src" }, 2671c2526597SStephen Boyd .num_parents = 1, 2672c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2673c2526597SStephen Boyd .ops = &clk_branch2_ops, 2674c2526597SStephen Boyd }, 2675c2526597SStephen Boyd }, 2676c2526597SStephen Boyd }; 2677c2526597SStephen Boyd 2678c2526597SStephen Boyd static struct clk_branch camss_csi1pix_clk = { 2679c2526597SStephen Boyd .halt_reg = 0x3154, 2680c2526597SStephen Boyd .clkr = { 2681c2526597SStephen Boyd .enable_reg = 0x3154, 2682c2526597SStephen Boyd .enable_mask = BIT(0), 2683c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2684c2526597SStephen Boyd .name = "camss_csi1pix_clk", 2685c2526597SStephen Boyd .parent_names = (const char *[]){ "csi1_clk_src" }, 2686c2526597SStephen Boyd .num_parents = 1, 2687c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2688c2526597SStephen Boyd .ops = &clk_branch2_ops, 2689c2526597SStephen Boyd }, 2690c2526597SStephen Boyd }, 2691c2526597SStephen Boyd }; 2692c2526597SStephen Boyd 2693c2526597SStephen Boyd static struct clk_branch camss_csi2_clk = { 2694c2526597SStephen Boyd .halt_reg = 0x3184, 2695c2526597SStephen Boyd .clkr = { 2696c2526597SStephen Boyd .enable_reg = 0x3184, 2697c2526597SStephen Boyd .enable_mask = BIT(0), 2698c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2699c2526597SStephen Boyd .name = "camss_csi2_clk", 2700c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2_clk_src" }, 2701c2526597SStephen Boyd .num_parents = 1, 2702c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2703c2526597SStephen Boyd .ops = &clk_branch2_ops, 2704c2526597SStephen Boyd }, 2705c2526597SStephen Boyd }, 2706c2526597SStephen Boyd }; 2707c2526597SStephen Boyd 2708c2526597SStephen Boyd static struct clk_branch camss_csi2_ahb_clk = { 2709c2526597SStephen Boyd .halt_reg = 0x3188, 2710c2526597SStephen Boyd .clkr = { 2711c2526597SStephen Boyd .enable_reg = 0x3188, 2712c2526597SStephen Boyd .enable_mask = BIT(0), 2713c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2714c2526597SStephen Boyd .name = "camss_csi2_ahb_clk", 2715c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2716c2526597SStephen Boyd .num_parents = 1, 2717c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2718c2526597SStephen Boyd .ops = &clk_branch2_ops, 2719c2526597SStephen Boyd }, 2720c2526597SStephen Boyd }, 2721c2526597SStephen Boyd }; 2722c2526597SStephen Boyd 2723c2526597SStephen Boyd static struct clk_branch camss_csi2phy_clk = { 2724c2526597SStephen Boyd .halt_reg = 0x3194, 2725c2526597SStephen Boyd .clkr = { 2726c2526597SStephen Boyd .enable_reg = 0x3194, 2727c2526597SStephen Boyd .enable_mask = BIT(0), 2728c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2729c2526597SStephen Boyd .name = "camss_csi2phy_clk", 2730c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2_clk_src" }, 2731c2526597SStephen Boyd .num_parents = 1, 2732c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2733c2526597SStephen Boyd .ops = &clk_branch2_ops, 2734c2526597SStephen Boyd }, 2735c2526597SStephen Boyd }, 2736c2526597SStephen Boyd }; 2737c2526597SStephen Boyd 2738c2526597SStephen Boyd static struct clk_branch camss_csi2rdi_clk = { 2739c2526597SStephen Boyd .halt_reg = 0x31a4, 2740c2526597SStephen Boyd .clkr = { 2741c2526597SStephen Boyd .enable_reg = 0x31a4, 2742c2526597SStephen Boyd .enable_mask = BIT(0), 2743c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2744c2526597SStephen Boyd .name = "camss_csi2rdi_clk", 2745c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2_clk_src" }, 2746c2526597SStephen Boyd .num_parents = 1, 2747c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2748c2526597SStephen Boyd .ops = &clk_branch2_ops, 2749c2526597SStephen Boyd }, 2750c2526597SStephen Boyd }, 2751c2526597SStephen Boyd }; 2752c2526597SStephen Boyd 2753c2526597SStephen Boyd static struct clk_branch camss_csi2pix_clk = { 2754c2526597SStephen Boyd .halt_reg = 0x31b4, 2755c2526597SStephen Boyd .clkr = { 2756c2526597SStephen Boyd .enable_reg = 0x31b4, 2757c2526597SStephen Boyd .enable_mask = BIT(0), 2758c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2759c2526597SStephen Boyd .name = "camss_csi2pix_clk", 2760c2526597SStephen Boyd .parent_names = (const char *[]){ "csi2_clk_src" }, 2761c2526597SStephen Boyd .num_parents = 1, 2762c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2763c2526597SStephen Boyd .ops = &clk_branch2_ops, 2764c2526597SStephen Boyd }, 2765c2526597SStephen Boyd }, 2766c2526597SStephen Boyd }; 2767c2526597SStephen Boyd 2768c2526597SStephen Boyd static struct clk_branch camss_csi3_clk = { 2769c2526597SStephen Boyd .halt_reg = 0x31e4, 2770c2526597SStephen Boyd .clkr = { 2771c2526597SStephen Boyd .enable_reg = 0x31e4, 2772c2526597SStephen Boyd .enable_mask = BIT(0), 2773c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2774c2526597SStephen Boyd .name = "camss_csi3_clk", 2775c2526597SStephen Boyd .parent_names = (const char *[]){ "csi3_clk_src" }, 2776c2526597SStephen Boyd .num_parents = 1, 2777c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2778c2526597SStephen Boyd .ops = &clk_branch2_ops, 2779c2526597SStephen Boyd }, 2780c2526597SStephen Boyd }, 2781c2526597SStephen Boyd }; 2782c2526597SStephen Boyd 2783c2526597SStephen Boyd static struct clk_branch camss_csi3_ahb_clk = { 2784c2526597SStephen Boyd .halt_reg = 0x31e8, 2785c2526597SStephen Boyd .clkr = { 2786c2526597SStephen Boyd .enable_reg = 0x31e8, 2787c2526597SStephen Boyd .enable_mask = BIT(0), 2788c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2789c2526597SStephen Boyd .name = "camss_csi3_ahb_clk", 2790c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2791c2526597SStephen Boyd .num_parents = 1, 2792c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2793c2526597SStephen Boyd .ops = &clk_branch2_ops, 2794c2526597SStephen Boyd }, 2795c2526597SStephen Boyd }, 2796c2526597SStephen Boyd }; 2797c2526597SStephen Boyd 2798c2526597SStephen Boyd static struct clk_branch camss_csi3phy_clk = { 2799c2526597SStephen Boyd .halt_reg = 0x31f4, 2800c2526597SStephen Boyd .clkr = { 2801c2526597SStephen Boyd .enable_reg = 0x31f4, 2802c2526597SStephen Boyd .enable_mask = BIT(0), 2803c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2804c2526597SStephen Boyd .name = "camss_csi3phy_clk", 2805c2526597SStephen Boyd .parent_names = (const char *[]){ "csi3_clk_src" }, 2806c2526597SStephen Boyd .num_parents = 1, 2807c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2808c2526597SStephen Boyd .ops = &clk_branch2_ops, 2809c2526597SStephen Boyd }, 2810c2526597SStephen Boyd }, 2811c2526597SStephen Boyd }; 2812c2526597SStephen Boyd 2813c2526597SStephen Boyd static struct clk_branch camss_csi3rdi_clk = { 2814c2526597SStephen Boyd .halt_reg = 0x3204, 2815c2526597SStephen Boyd .clkr = { 2816c2526597SStephen Boyd .enable_reg = 0x3204, 2817c2526597SStephen Boyd .enable_mask = BIT(0), 2818c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2819c2526597SStephen Boyd .name = "camss_csi3rdi_clk", 2820c2526597SStephen Boyd .parent_names = (const char *[]){ "csi3_clk_src" }, 2821c2526597SStephen Boyd .num_parents = 1, 2822c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2823c2526597SStephen Boyd .ops = &clk_branch2_ops, 2824c2526597SStephen Boyd }, 2825c2526597SStephen Boyd }, 2826c2526597SStephen Boyd }; 2827c2526597SStephen Boyd 2828c2526597SStephen Boyd static struct clk_branch camss_csi3pix_clk = { 2829c2526597SStephen Boyd .halt_reg = 0x3214, 2830c2526597SStephen Boyd .clkr = { 2831c2526597SStephen Boyd .enable_reg = 0x3214, 2832c2526597SStephen Boyd .enable_mask = BIT(0), 2833c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2834c2526597SStephen Boyd .name = "camss_csi3pix_clk", 2835c2526597SStephen Boyd .parent_names = (const char *[]){ "csi3_clk_src" }, 2836c2526597SStephen Boyd .num_parents = 1, 2837c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2838c2526597SStephen Boyd .ops = &clk_branch2_ops, 2839c2526597SStephen Boyd }, 2840c2526597SStephen Boyd }, 2841c2526597SStephen Boyd }; 2842c2526597SStephen Boyd 2843c2526597SStephen Boyd static struct clk_branch camss_ispif_ahb_clk = { 2844c2526597SStephen Boyd .halt_reg = 0x3224, 2845c2526597SStephen Boyd .clkr = { 2846c2526597SStephen Boyd .enable_reg = 0x3224, 2847c2526597SStephen Boyd .enable_mask = BIT(0), 2848c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2849c2526597SStephen Boyd .name = "camss_ispif_ahb_clk", 2850c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2851c2526597SStephen Boyd .num_parents = 1, 2852c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2853c2526597SStephen Boyd .ops = &clk_branch2_ops, 2854c2526597SStephen Boyd }, 2855c2526597SStephen Boyd }, 2856c2526597SStephen Boyd }; 2857c2526597SStephen Boyd 2858c2526597SStephen Boyd static struct clk_branch fd_core_clk = { 2859c2526597SStephen Boyd .halt_reg = 0x3b68, 2860c2526597SStephen Boyd .clkr = { 2861c2526597SStephen Boyd .enable_reg = 0x3b68, 2862c2526597SStephen Boyd .enable_mask = BIT(0), 2863c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2864c2526597SStephen Boyd .name = "fd_core_clk", 2865c2526597SStephen Boyd .parent_names = (const char *[]){ "fd_core_clk_src" }, 2866c2526597SStephen Boyd .num_parents = 1, 2867c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2868c2526597SStephen Boyd .ops = &clk_branch2_ops, 2869c2526597SStephen Boyd }, 2870c2526597SStephen Boyd }, 2871c2526597SStephen Boyd }; 2872c2526597SStephen Boyd 2873c2526597SStephen Boyd static struct clk_branch fd_core_uar_clk = { 2874c2526597SStephen Boyd .halt_reg = 0x3b6c, 2875c2526597SStephen Boyd .clkr = { 2876c2526597SStephen Boyd .enable_reg = 0x3b6c, 2877c2526597SStephen Boyd .enable_mask = BIT(0), 2878c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2879c2526597SStephen Boyd .name = "fd_core_uar_clk", 2880c2526597SStephen Boyd .parent_names = (const char *[]){ "fd_core_clk_src" }, 2881c2526597SStephen Boyd .num_parents = 1, 2882c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2883c2526597SStephen Boyd .ops = &clk_branch2_ops, 2884c2526597SStephen Boyd }, 2885c2526597SStephen Boyd }, 2886c2526597SStephen Boyd }; 2887c2526597SStephen Boyd 2888c2526597SStephen Boyd static struct clk_branch fd_ahb_clk = { 2889c2526597SStephen Boyd .halt_reg = 0x3ba74, 2890c2526597SStephen Boyd .clkr = { 2891c2526597SStephen Boyd .enable_reg = 0x3ba74, 2892c2526597SStephen Boyd .enable_mask = BIT(0), 2893c2526597SStephen Boyd .hw.init = &(struct clk_init_data){ 2894c2526597SStephen Boyd .name = "fd_ahb_clk", 2895c2526597SStephen Boyd .parent_names = (const char *[]){ "ahb_clk_src" }, 2896c2526597SStephen Boyd .num_parents = 1, 2897c2526597SStephen Boyd .flags = CLK_SET_RATE_PARENT, 2898c2526597SStephen Boyd .ops = &clk_branch2_ops, 2899c2526597SStephen Boyd }, 2900c2526597SStephen Boyd }, 2901c2526597SStephen Boyd }; 2902c2526597SStephen Boyd 2903c2526597SStephen Boyd static struct clk_hw *mmcc_msm8996_hws[] = { 2904c2526597SStephen Boyd &gpll0_div.hw, 2905c2526597SStephen Boyd }; 2906c2526597SStephen Boyd 290763bb4fd6SRajendra Nayak static struct gdsc mmagic_bimc_gdsc = { 290863bb4fd6SRajendra Nayak .gdscr = 0x529c, 290963bb4fd6SRajendra Nayak .pd = { 291063bb4fd6SRajendra Nayak .name = "mmagic_bimc", 291163bb4fd6SRajendra Nayak }, 291263bb4fd6SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 291363bb4fd6SRajendra Nayak }; 291463bb4fd6SRajendra Nayak 29157e824d50SRajendra Nayak static struct gdsc mmagic_video_gdsc = { 29167e824d50SRajendra Nayak .gdscr = 0x119c, 29177e824d50SRajendra Nayak .gds_hw_ctrl = 0x120c, 29187e824d50SRajendra Nayak .pd = { 29197e824d50SRajendra Nayak .name = "mmagic_video", 29207e824d50SRajendra Nayak }, 29217e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29227e824d50SRajendra Nayak .flags = VOTABLE, 29237e824d50SRajendra Nayak }; 29247e824d50SRajendra Nayak 29257e824d50SRajendra Nayak static struct gdsc mmagic_mdss_gdsc = { 29267e824d50SRajendra Nayak .gdscr = 0x247c, 29277e824d50SRajendra Nayak .gds_hw_ctrl = 0x2480, 29287e824d50SRajendra Nayak .pd = { 29297e824d50SRajendra Nayak .name = "mmagic_mdss", 29307e824d50SRajendra Nayak }, 29317e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29327e824d50SRajendra Nayak .flags = VOTABLE, 29337e824d50SRajendra Nayak }; 29347e824d50SRajendra Nayak 29357e824d50SRajendra Nayak static struct gdsc mmagic_camss_gdsc = { 29367e824d50SRajendra Nayak .gdscr = 0x3c4c, 29377e824d50SRajendra Nayak .gds_hw_ctrl = 0x3c50, 29387e824d50SRajendra Nayak .pd = { 29397e824d50SRajendra Nayak .name = "mmagic_camss", 29407e824d50SRajendra Nayak }, 29417e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29427e824d50SRajendra Nayak .flags = VOTABLE, 29437e824d50SRajendra Nayak }; 29447e824d50SRajendra Nayak 29457e824d50SRajendra Nayak static struct gdsc venus_gdsc = { 29467e824d50SRajendra Nayak .gdscr = 0x1024, 29477e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 }, 29487e824d50SRajendra Nayak .cxc_count = 3, 29497e824d50SRajendra Nayak .pd = { 29507e824d50SRajendra Nayak .name = "venus", 29517e824d50SRajendra Nayak }, 29527e824d50SRajendra Nayak .parent = &mmagic_video_gdsc.pd, 29537e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29547e824d50SRajendra Nayak }; 29557e824d50SRajendra Nayak 29567e824d50SRajendra Nayak static struct gdsc venus_core0_gdsc = { 29577e824d50SRajendra Nayak .gdscr = 0x1040, 29587e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x1048 }, 29597e824d50SRajendra Nayak .cxc_count = 1, 29607e824d50SRajendra Nayak .pd = { 29617e824d50SRajendra Nayak .name = "venus_core0", 29627e824d50SRajendra Nayak }, 29634a43e35dSStanimir Varbanov .parent = &venus_gdsc.pd, 29647e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 296596893e10SSricharan R .flags = HW_CTRL, 29667e824d50SRajendra Nayak }; 29677e824d50SRajendra Nayak 29687e824d50SRajendra Nayak static struct gdsc venus_core1_gdsc = { 29697e824d50SRajendra Nayak .gdscr = 0x1044, 29707e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x104c }, 29717e824d50SRajendra Nayak .cxc_count = 1, 29727e824d50SRajendra Nayak .pd = { 29737e824d50SRajendra Nayak .name = "venus_core1", 29747e824d50SRajendra Nayak }, 29754a43e35dSStanimir Varbanov .parent = &venus_gdsc.pd, 29767e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 297796893e10SSricharan R .flags = HW_CTRL, 29787e824d50SRajendra Nayak }; 29797e824d50SRajendra Nayak 29807e824d50SRajendra Nayak static struct gdsc camss_gdsc = { 29817e824d50SRajendra Nayak .gdscr = 0x34a0, 29827e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36bc, 0x36c4 }, 29837e824d50SRajendra Nayak .cxc_count = 2, 29847e824d50SRajendra Nayak .pd = { 29857e824d50SRajendra Nayak .name = "camss", 29867e824d50SRajendra Nayak }, 29877e824d50SRajendra Nayak .parent = &mmagic_camss_gdsc.pd, 29887e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 29897e824d50SRajendra Nayak }; 29907e824d50SRajendra Nayak 29917e824d50SRajendra Nayak static struct gdsc vfe0_gdsc = { 29927e824d50SRajendra Nayak .gdscr = 0x3664, 29937e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36a8 }, 29947e824d50SRajendra Nayak .cxc_count = 1, 29957e824d50SRajendra Nayak .pd = { 29967e824d50SRajendra Nayak .name = "vfe0", 29977e824d50SRajendra Nayak }, 29987e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 29997e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30007e824d50SRajendra Nayak }; 30017e824d50SRajendra Nayak 30027e824d50SRajendra Nayak static struct gdsc vfe1_gdsc = { 30037e824d50SRajendra Nayak .gdscr = 0x3674, 30047e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36ac }, 30057e824d50SRajendra Nayak .cxc_count = 1, 30067e824d50SRajendra Nayak .pd = { 3007a62ca337SRajendra Nayak .name = "vfe1", 30087e824d50SRajendra Nayak }, 30097e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 30107e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30117e824d50SRajendra Nayak }; 30127e824d50SRajendra Nayak 30137e824d50SRajendra Nayak static struct gdsc jpeg_gdsc = { 30147e824d50SRajendra Nayak .gdscr = 0x35a4, 30157e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 }, 30167e824d50SRajendra Nayak .cxc_count = 4, 30177e824d50SRajendra Nayak .pd = { 30187e824d50SRajendra Nayak .name = "jpeg", 30197e824d50SRajendra Nayak }, 30207e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 30217e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30227e824d50SRajendra Nayak }; 30237e824d50SRajendra Nayak 30247e824d50SRajendra Nayak static struct gdsc cpp_gdsc = { 30257e824d50SRajendra Nayak .gdscr = 0x36d4, 30267e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x36b0 }, 30277e824d50SRajendra Nayak .cxc_count = 1, 30287e824d50SRajendra Nayak .pd = { 30297e824d50SRajendra Nayak .name = "cpp", 30307e824d50SRajendra Nayak }, 30317e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 30327e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30337e824d50SRajendra Nayak }; 30347e824d50SRajendra Nayak 30357e824d50SRajendra Nayak static struct gdsc fd_gdsc = { 30367e824d50SRajendra Nayak .gdscr = 0x3b64, 30377e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x3b68, 0x3b6c }, 30387e824d50SRajendra Nayak .cxc_count = 2, 30397e824d50SRajendra Nayak .pd = { 30407e824d50SRajendra Nayak .name = "fd", 30417e824d50SRajendra Nayak }, 30427e824d50SRajendra Nayak .parent = &camss_gdsc.pd, 30437e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30447e824d50SRajendra Nayak }; 30457e824d50SRajendra Nayak 30467e824d50SRajendra Nayak static struct gdsc mdss_gdsc = { 30477e824d50SRajendra Nayak .gdscr = 0x2304, 30487e824d50SRajendra Nayak .cxcs = (unsigned int []){ 0x2310, 0x231c }, 30497e824d50SRajendra Nayak .cxc_count = 2, 30507e824d50SRajendra Nayak .pd = { 30517e824d50SRajendra Nayak .name = "mdss", 30527e824d50SRajendra Nayak }, 30537e824d50SRajendra Nayak .parent = &mmagic_mdss_gdsc.pd, 30547e824d50SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30557e824d50SRajendra Nayak }; 30567e824d50SRajendra Nayak 30574154f619SRajendra Nayak static struct gdsc gpu_gdsc = { 30584154f619SRajendra Nayak .gdscr = 0x4034, 30594154f619SRajendra Nayak .gds_hw_ctrl = 0x4038, 30604154f619SRajendra Nayak .pd = { 30614154f619SRajendra Nayak .name = "gpu", 30624154f619SRajendra Nayak }, 30634154f619SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30644154f619SRajendra Nayak .flags = VOTABLE, 30654154f619SRajendra Nayak }; 30664154f619SRajendra Nayak 30674154f619SRajendra Nayak static struct gdsc gpu_gx_gdsc = { 30684154f619SRajendra Nayak .gdscr = 0x4024, 30694154f619SRajendra Nayak .clamp_io_ctrl = 0x4300, 30704154f619SRajendra Nayak .cxcs = (unsigned int []){ 0x4028 }, 30714154f619SRajendra Nayak .cxc_count = 1, 30724154f619SRajendra Nayak .pd = { 30734154f619SRajendra Nayak .name = "gpu_gx", 30744154f619SRajendra Nayak }, 30754154f619SRajendra Nayak .pwrsts = PWRSTS_OFF_ON, 30764154f619SRajendra Nayak .flags = CLAMP_IO, 30774154f619SRajendra Nayak }; 30784154f619SRajendra Nayak 3079c2526597SStephen Boyd static struct clk_regmap *mmcc_msm8996_clocks[] = { 3080c2526597SStephen Boyd [MMPLL0_EARLY] = &mmpll0_early.clkr, 3081c2526597SStephen Boyd [MMPLL0_PLL] = &mmpll0.clkr, 3082c2526597SStephen Boyd [MMPLL1_EARLY] = &mmpll1_early.clkr, 3083c2526597SStephen Boyd [MMPLL1_PLL] = &mmpll1.clkr, 3084c2526597SStephen Boyd [MMPLL2_EARLY] = &mmpll2_early.clkr, 3085c2526597SStephen Boyd [MMPLL2_PLL] = &mmpll2.clkr, 3086c2526597SStephen Boyd [MMPLL3_EARLY] = &mmpll3_early.clkr, 3087c2526597SStephen Boyd [MMPLL3_PLL] = &mmpll3.clkr, 3088c2526597SStephen Boyd [MMPLL4_EARLY] = &mmpll4_early.clkr, 3089c2526597SStephen Boyd [MMPLL4_PLL] = &mmpll4.clkr, 3090c2526597SStephen Boyd [MMPLL5_EARLY] = &mmpll5_early.clkr, 3091c2526597SStephen Boyd [MMPLL5_PLL] = &mmpll5.clkr, 3092c2526597SStephen Boyd [MMPLL8_EARLY] = &mmpll8_early.clkr, 3093c2526597SStephen Boyd [MMPLL8_PLL] = &mmpll8.clkr, 3094c2526597SStephen Boyd [MMPLL9_EARLY] = &mmpll9_early.clkr, 3095c2526597SStephen Boyd [MMPLL9_PLL] = &mmpll9.clkr, 3096c2526597SStephen Boyd [AHB_CLK_SRC] = &ahb_clk_src.clkr, 3097c2526597SStephen Boyd [AXI_CLK_SRC] = &axi_clk_src.clkr, 3098c2526597SStephen Boyd [MAXI_CLK_SRC] = &maxi_clk_src.clkr, 3099c2526597SStephen Boyd [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 3100c2526597SStephen Boyd [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 3101c2526597SStephen Boyd [ISENSE_CLK_SRC] = &isense_clk_src.clkr, 3102c2526597SStephen Boyd [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 3103c2526597SStephen Boyd [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, 3104c2526597SStephen Boyd [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr, 3105c2526597SStephen Boyd [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr, 3106c2526597SStephen Boyd [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3107c2526597SStephen Boyd [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 3108c2526597SStephen Boyd [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3109c2526597SStephen Boyd [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 3110c2526597SStephen Boyd [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3111c2526597SStephen Boyd [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 3112c2526597SStephen Boyd [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3113c2526597SStephen Boyd [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 3114c2526597SStephen Boyd [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3115c2526597SStephen Boyd [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 3116c2526597SStephen Boyd [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3117c2526597SStephen Boyd [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3118c2526597SStephen Boyd [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3119c2526597SStephen Boyd [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3120c2526597SStephen Boyd [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 3121c2526597SStephen Boyd [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 3122c2526597SStephen Boyd [CCI_CLK_SRC] = &cci_clk_src.clkr, 3123c2526597SStephen Boyd [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3124c2526597SStephen Boyd [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3125c2526597SStephen Boyd [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 3126c2526597SStephen Boyd [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr, 3127c2526597SStephen Boyd [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr, 3128c2526597SStephen Boyd [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr, 3129c2526597SStephen Boyd [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3130c2526597SStephen Boyd [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, 3131c2526597SStephen Boyd [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr, 3132c2526597SStephen Boyd [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3133c2526597SStephen Boyd [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 3134c2526597SStephen Boyd [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3135c2526597SStephen Boyd [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3136c2526597SStephen Boyd [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3137c2526597SStephen Boyd [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 3138c2526597SStephen Boyd [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 3139c2526597SStephen Boyd [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr, 3140c2526597SStephen Boyd [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr, 3141c2526597SStephen Boyd [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr, 3142c2526597SStephen Boyd [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, 3143c2526597SStephen Boyd [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, 3144c2526597SStephen Boyd [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr, 3145c2526597SStephen Boyd [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr, 3146c2526597SStephen Boyd [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr, 3147c2526597SStephen Boyd [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr, 3148c2526597SStephen Boyd [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr, 3149c2526597SStephen Boyd [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr, 3150c2526597SStephen Boyd [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr, 3151c2526597SStephen Boyd [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr, 3152c2526597SStephen Boyd [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr, 3153c2526597SStephen Boyd [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr, 3154c2526597SStephen Boyd [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr, 3155c2526597SStephen Boyd [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr, 3156c2526597SStephen Boyd [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr, 3157c2526597SStephen Boyd [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr, 3158c2526597SStephen Boyd [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr, 3159c2526597SStephen Boyd [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr, 3160c2526597SStephen Boyd [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr, 3161c2526597SStephen Boyd [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr, 3162c2526597SStephen Boyd [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr, 3163c2526597SStephen Boyd [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr, 3164c2526597SStephen Boyd [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr, 3165c2526597SStephen Boyd [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr, 3166c2526597SStephen Boyd [GPU_AHB_CLK] = &gpu_ahb_clk.clkr, 3167c2526597SStephen Boyd [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr, 3168c2526597SStephen Boyd [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr, 3169c2526597SStephen Boyd [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr, 3170c2526597SStephen Boyd [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr, 3171c2526597SStephen Boyd [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr, 3172c2526597SStephen Boyd [VIDEO_CORE_CLK] = &video_core_clk.clkr, 3173c2526597SStephen Boyd [VIDEO_AXI_CLK] = &video_axi_clk.clkr, 3174c2526597SStephen Boyd [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr, 3175c2526597SStephen Boyd [VIDEO_AHB_CLK] = &video_ahb_clk.clkr, 3176c2526597SStephen Boyd [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr, 3177c2526597SStephen Boyd [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr, 3178c2526597SStephen Boyd [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 3179c2526597SStephen Boyd [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, 3180c2526597SStephen Boyd [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 3181c2526597SStephen Boyd [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 3182c2526597SStephen Boyd [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 3183c2526597SStephen Boyd [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 3184c2526597SStephen Boyd [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 3185c2526597SStephen Boyd [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 3186c2526597SStephen Boyd [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 3187c2526597SStephen Boyd [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 3188c2526597SStephen Boyd [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 3189c2526597SStephen Boyd [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 3190c2526597SStephen Boyd [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 3191c2526597SStephen Boyd [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 3192c2526597SStephen Boyd [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, 3193c2526597SStephen Boyd [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 3194c2526597SStephen Boyd [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 3195c2526597SStephen Boyd [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 3196c2526597SStephen Boyd [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 3197c2526597SStephen Boyd [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 3198c2526597SStephen Boyd [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 3199c2526597SStephen Boyd [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 3200c2526597SStephen Boyd [CAMSS_CCI_CLK] = &camss_cci_clk.clkr, 3201c2526597SStephen Boyd [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr, 3202c2526597SStephen Boyd [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr, 3203c2526597SStephen Boyd [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr, 3204c2526597SStephen Boyd [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr, 3205c2526597SStephen Boyd [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr, 3206c2526597SStephen Boyd [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr, 3207c2526597SStephen Boyd [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr, 3208c2526597SStephen Boyd [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr, 3209c2526597SStephen Boyd [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr, 3210c2526597SStephen Boyd [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr, 3211c2526597SStephen Boyd [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr, 3212c2526597SStephen Boyd [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr, 3213c2526597SStephen Boyd [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr, 3214c2526597SStephen Boyd [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr, 3215c2526597SStephen Boyd [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr, 3216c2526597SStephen Boyd [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr, 3217c2526597SStephen Boyd [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr, 3218c2526597SStephen Boyd [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr, 3219c2526597SStephen Boyd [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr, 3220c2526597SStephen Boyd [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr, 3221c2526597SStephen Boyd [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 3222c2526597SStephen Boyd [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 3223c2526597SStephen Boyd [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr, 3224c2526597SStephen Boyd [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr, 3225c2526597SStephen Boyd [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr, 3226c2526597SStephen Boyd [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr, 3227c2526597SStephen Boyd [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 3228c2526597SStephen Boyd [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 3229c2526597SStephen Boyd [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, 3230c2526597SStephen Boyd [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 3231c2526597SStephen Boyd [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 3232c2526597SStephen Boyd [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 3233c2526597SStephen Boyd [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 3234c2526597SStephen Boyd [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, 3235c2526597SStephen Boyd [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 3236c2526597SStephen Boyd [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 3237c2526597SStephen Boyd [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 3238c2526597SStephen Boyd [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 3239c2526597SStephen Boyd [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, 3240c2526597SStephen Boyd [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 3241c2526597SStephen Boyd [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 3242c2526597SStephen Boyd [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 3243c2526597SStephen Boyd [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 3244c2526597SStephen Boyd [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, 3245c2526597SStephen Boyd [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 3246c2526597SStephen Boyd [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 3247c2526597SStephen Boyd [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 3248c2526597SStephen Boyd [FD_CORE_CLK] = &fd_core_clk.clkr, 3249c2526597SStephen Boyd [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr, 3250c2526597SStephen Boyd [FD_AHB_CLK] = &fd_ahb_clk.clkr, 3251c2526597SStephen Boyd }; 3252c2526597SStephen Boyd 32537e824d50SRajendra Nayak static struct gdsc *mmcc_msm8996_gdscs[] = { 325463bb4fd6SRajendra Nayak [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc, 32557e824d50SRajendra Nayak [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc, 32567e824d50SRajendra Nayak [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc, 32577e824d50SRajendra Nayak [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc, 32587e824d50SRajendra Nayak [VENUS_GDSC] = &venus_gdsc, 32597e824d50SRajendra Nayak [VENUS_CORE0_GDSC] = &venus_core0_gdsc, 32607e824d50SRajendra Nayak [VENUS_CORE1_GDSC] = &venus_core1_gdsc, 32617e824d50SRajendra Nayak [CAMSS_GDSC] = &camss_gdsc, 32627e824d50SRajendra Nayak [VFE0_GDSC] = &vfe0_gdsc, 32637e824d50SRajendra Nayak [VFE1_GDSC] = &vfe1_gdsc, 32647e824d50SRajendra Nayak [JPEG_GDSC] = &jpeg_gdsc, 32657e824d50SRajendra Nayak [CPP_GDSC] = &cpp_gdsc, 32667e824d50SRajendra Nayak [FD_GDSC] = &fd_gdsc, 32677e824d50SRajendra Nayak [MDSS_GDSC] = &mdss_gdsc, 32684154f619SRajendra Nayak [GPU_GDSC] = &gpu_gdsc, 32694154f619SRajendra Nayak [GPU_GX_GDSC] = &gpu_gx_gdsc, 32707e824d50SRajendra Nayak }; 32717e824d50SRajendra Nayak 3272c2526597SStephen Boyd static const struct qcom_reset_map mmcc_msm8996_resets[] = { 3273c2526597SStephen Boyd [MMAGICAHB_BCR] = { 0x5020 }, 3274c2526597SStephen Boyd [MMAGIC_CFG_BCR] = { 0x5050 }, 3275c2526597SStephen Boyd [MISC_BCR] = { 0x5010 }, 3276c2526597SStephen Boyd [BTO_BCR] = { 0x5030 }, 3277c2526597SStephen Boyd [MMAGICAXI_BCR] = { 0x5060 }, 3278c2526597SStephen Boyd [MMAGICMAXI_BCR] = { 0x5070 }, 3279c2526597SStephen Boyd [DSA_BCR] = { 0x50a0 }, 3280c2526597SStephen Boyd [MMAGIC_CAMSS_BCR] = { 0x3c40 }, 3281c2526597SStephen Boyd [THROTTLE_CAMSS_BCR] = { 0x3c30 }, 3282c2526597SStephen Boyd [SMMU_VFE_BCR] = { 0x3c00 }, 3283c2526597SStephen Boyd [SMMU_CPP_BCR] = { 0x3c10 }, 3284c2526597SStephen Boyd [SMMU_JPEG_BCR] = { 0x3c20 }, 3285c2526597SStephen Boyd [MMAGIC_MDSS_BCR] = { 0x2470 }, 3286c2526597SStephen Boyd [THROTTLE_MDSS_BCR] = { 0x2460 }, 3287c2526597SStephen Boyd [SMMU_ROT_BCR] = { 0x2440 }, 3288c2526597SStephen Boyd [SMMU_MDP_BCR] = { 0x2450 }, 3289c2526597SStephen Boyd [MMAGIC_VIDEO_BCR] = { 0x1190 }, 3290c2526597SStephen Boyd [THROTTLE_VIDEO_BCR] = { 0x1180 }, 3291c2526597SStephen Boyd [SMMU_VIDEO_BCR] = { 0x1170 }, 3292c2526597SStephen Boyd [MMAGIC_BIMC_BCR] = { 0x5290 }, 3293c2526597SStephen Boyd [GPU_GX_BCR] = { 0x4020 }, 3294c2526597SStephen Boyd [GPU_BCR] = { 0x4030 }, 3295c2526597SStephen Boyd [GPU_AON_BCR] = { 0x4040 }, 3296c2526597SStephen Boyd [VMEM_BCR] = { 0x1200 }, 3297c2526597SStephen Boyd [MMSS_RBCPR_BCR] = { 0x4080 }, 3298c2526597SStephen Boyd [VIDEO_BCR] = { 0x1020 }, 3299c2526597SStephen Boyd [MDSS_BCR] = { 0x2300 }, 3300c2526597SStephen Boyd [CAMSS_TOP_BCR] = { 0x3480 }, 3301c2526597SStephen Boyd [CAMSS_AHB_BCR] = { 0x3488 }, 3302c2526597SStephen Boyd [CAMSS_MICRO_BCR] = { 0x3490 }, 3303c2526597SStephen Boyd [CAMSS_CCI_BCR] = { 0x3340 }, 3304c2526597SStephen Boyd [CAMSS_PHY0_BCR] = { 0x3020 }, 3305c2526597SStephen Boyd [CAMSS_PHY1_BCR] = { 0x3050 }, 3306c2526597SStephen Boyd [CAMSS_PHY2_BCR] = { 0x3080 }, 3307c2526597SStephen Boyd [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 }, 3308c2526597SStephen Boyd [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 }, 3309c2526597SStephen Boyd [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 }, 3310c2526597SStephen Boyd [CAMSS_JPEG_BCR] = { 0x35a0 }, 3311c2526597SStephen Boyd [CAMSS_VFE_BCR] = { 0x36a0 }, 3312c2526597SStephen Boyd [CAMSS_VFE0_BCR] = { 0x3660 }, 3313c2526597SStephen Boyd [CAMSS_VFE1_BCR] = { 0x3670 }, 3314c2526597SStephen Boyd [CAMSS_CSI_VFE0_BCR] = { 0x3700 }, 3315c2526597SStephen Boyd [CAMSS_CSI_VFE1_BCR] = { 0x3710 }, 3316c2526597SStephen Boyd [CAMSS_CPP_TOP_BCR] = { 0x36c0 }, 3317c2526597SStephen Boyd [CAMSS_CPP_BCR] = { 0x36d0 }, 3318c2526597SStephen Boyd [CAMSS_CSI0_BCR] = { 0x30b0 }, 3319c2526597SStephen Boyd [CAMSS_CSI0RDI_BCR] = { 0x30d0 }, 3320c2526597SStephen Boyd [CAMSS_CSI0PIX_BCR] = { 0x30e0 }, 3321c2526597SStephen Boyd [CAMSS_CSI1_BCR] = { 0x3120 }, 3322c2526597SStephen Boyd [CAMSS_CSI1RDI_BCR] = { 0x3140 }, 3323c2526597SStephen Boyd [CAMSS_CSI1PIX_BCR] = { 0x3150 }, 3324c2526597SStephen Boyd [CAMSS_CSI2_BCR] = { 0x3180 }, 3325c2526597SStephen Boyd [CAMSS_CSI2RDI_BCR] = { 0x31a0 }, 3326c2526597SStephen Boyd [CAMSS_CSI2PIX_BCR] = { 0x31b0 }, 3327c2526597SStephen Boyd [CAMSS_CSI3_BCR] = { 0x31e0 }, 3328c2526597SStephen Boyd [CAMSS_CSI3RDI_BCR] = { 0x3200 }, 3329c2526597SStephen Boyd [CAMSS_CSI3PIX_BCR] = { 0x3210 }, 3330c2526597SStephen Boyd [CAMSS_ISPIF_BCR] = { 0x3220 }, 3331c2526597SStephen Boyd [FD_BCR] = { 0x3b60 }, 3332c2526597SStephen Boyd [MMSS_SPDM_RM_BCR] = { 0x300 }, 3333c2526597SStephen Boyd }; 3334c2526597SStephen Boyd 3335c2526597SStephen Boyd static const struct regmap_config mmcc_msm8996_regmap_config = { 3336c2526597SStephen Boyd .reg_bits = 32, 3337c2526597SStephen Boyd .reg_stride = 4, 3338c2526597SStephen Boyd .val_bits = 32, 3339c2526597SStephen Boyd .max_register = 0xb008, 3340c2526597SStephen Boyd .fast_io = true, 3341c2526597SStephen Boyd }; 3342c2526597SStephen Boyd 3343c2526597SStephen Boyd static const struct qcom_cc_desc mmcc_msm8996_desc = { 3344c2526597SStephen Boyd .config = &mmcc_msm8996_regmap_config, 3345c2526597SStephen Boyd .clks = mmcc_msm8996_clocks, 3346c2526597SStephen Boyd .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks), 3347c2526597SStephen Boyd .resets = mmcc_msm8996_resets, 3348c2526597SStephen Boyd .num_resets = ARRAY_SIZE(mmcc_msm8996_resets), 33497e824d50SRajendra Nayak .gdscs = mmcc_msm8996_gdscs, 33507e824d50SRajendra Nayak .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs), 3351c2526597SStephen Boyd }; 3352c2526597SStephen Boyd 3353c2526597SStephen Boyd static const struct of_device_id mmcc_msm8996_match_table[] = { 3354c2526597SStephen Boyd { .compatible = "qcom,mmcc-msm8996" }, 3355c2526597SStephen Boyd { } 3356c2526597SStephen Boyd }; 3357c2526597SStephen Boyd MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table); 3358c2526597SStephen Boyd 3359c2526597SStephen Boyd static int mmcc_msm8996_probe(struct platform_device *pdev) 3360c2526597SStephen Boyd { 3361c2526597SStephen Boyd struct device *dev = &pdev->dev; 3362120c1552SStephen Boyd int i, ret; 3363c2526597SStephen Boyd struct regmap *regmap; 3364c2526597SStephen Boyd 3365c2526597SStephen Boyd regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc); 3366c2526597SStephen Boyd if (IS_ERR(regmap)) 3367c2526597SStephen Boyd return PTR_ERR(regmap); 3368c2526597SStephen Boyd 3369c2526597SStephen Boyd /* Disable the AHB DCD */ 3370c2526597SStephen Boyd regmap_update_bits(regmap, 0x50d8, BIT(31), 0); 3371c2526597SStephen Boyd /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */ 3372c2526597SStephen Boyd regmap_update_bits(regmap, 0x5054, BIT(15), 0); 3373c2526597SStephen Boyd 3374c2526597SStephen Boyd for (i = 0; i < ARRAY_SIZE(mmcc_msm8996_hws); i++) { 3375120c1552SStephen Boyd ret = devm_clk_hw_register(dev, mmcc_msm8996_hws[i]); 3376120c1552SStephen Boyd if (ret) 3377120c1552SStephen Boyd return ret; 3378c2526597SStephen Boyd } 3379c2526597SStephen Boyd 3380c2526597SStephen Boyd return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap); 3381c2526597SStephen Boyd } 3382c2526597SStephen Boyd 3383c2526597SStephen Boyd static struct platform_driver mmcc_msm8996_driver = { 3384c2526597SStephen Boyd .probe = mmcc_msm8996_probe, 3385c2526597SStephen Boyd .driver = { 3386c2526597SStephen Boyd .name = "mmcc-msm8996", 3387c2526597SStephen Boyd .of_match_table = mmcc_msm8996_match_table, 3388c2526597SStephen Boyd }, 3389c2526597SStephen Boyd }; 3390c2526597SStephen Boyd module_platform_driver(mmcc_msm8996_driver); 3391c2526597SStephen Boyd 3392c2526597SStephen Boyd MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver"); 3393c2526597SStephen Boyd MODULE_LICENSE("GPL v2"); 3394c2526597SStephen Boyd MODULE_ALIAS("platform:mmcc-msm8996"); 3395