1 /* 2 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 25 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 26 #include <dt-bindings/reset/qcom,mmcc-msm8974.h> 27 28 #include "common.h" 29 #include "clk-regmap.h" 30 #include "clk-pll.h" 31 #include "clk-rcg.h" 32 #include "clk-branch.h" 33 #include "reset.h" 34 35 enum { 36 P_XO, 37 P_MMPLL0, 38 P_EDPLINK, 39 P_MMPLL1, 40 P_HDMIPLL, 41 P_GPLL0, 42 P_EDPVCO, 43 P_GPLL1, 44 P_DSI0PLL, 45 P_DSI0PLL_BYTE, 46 P_MMPLL2, 47 P_MMPLL3, 48 P_DSI1PLL, 49 P_DSI1PLL_BYTE, 50 }; 51 52 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { 53 { P_XO, 0 }, 54 { P_MMPLL0, 1 }, 55 { P_MMPLL1, 2 }, 56 { P_GPLL0, 5 } 57 }; 58 59 static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = { 60 "xo", 61 "mmpll0_vote", 62 "mmpll1_vote", 63 "mmss_gpll0_vote", 64 }; 65 66 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { 67 { P_XO, 0 }, 68 { P_MMPLL0, 1 }, 69 { P_HDMIPLL, 4 }, 70 { P_GPLL0, 5 }, 71 { P_DSI0PLL, 2 }, 72 { P_DSI1PLL, 3 } 73 }; 74 75 static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { 76 "xo", 77 "mmpll0_vote", 78 "hdmipll", 79 "mmss_gpll0_vote", 80 "dsi0pll", 81 "dsi1pll", 82 }; 83 84 static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = { 85 { P_XO, 0 }, 86 { P_MMPLL0, 1 }, 87 { P_MMPLL1, 2 }, 88 { P_GPLL0, 5 }, 89 { P_MMPLL2, 3 } 90 }; 91 92 static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = { 93 "xo", 94 "mmpll0_vote", 95 "mmpll1_vote", 96 "mmss_gpll0_vote", 97 "mmpll2", 98 }; 99 100 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = { 101 { P_XO, 0 }, 102 { P_MMPLL0, 1 }, 103 { P_MMPLL1, 2 }, 104 { P_GPLL0, 5 }, 105 { P_MMPLL3, 3 } 106 }; 107 108 static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = { 109 "xo", 110 "mmpll0_vote", 111 "mmpll1_vote", 112 "mmss_gpll0_vote", 113 "mmpll3", 114 }; 115 116 static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = { 117 { P_XO, 0 }, 118 { P_MMPLL0, 1 }, 119 { P_MMPLL1, 2 }, 120 { P_GPLL0, 5 }, 121 { P_GPLL1, 4 } 122 }; 123 124 static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = { 125 "xo", 126 "mmpll0_vote", 127 "mmpll1_vote", 128 "mmss_gpll0_vote", 129 "gpll1_vote", 130 }; 131 132 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = { 133 { P_XO, 0 }, 134 { P_EDPLINK, 4 }, 135 { P_HDMIPLL, 3 }, 136 { P_EDPVCO, 5 }, 137 { P_DSI0PLL, 1 }, 138 { P_DSI1PLL, 2 } 139 }; 140 141 static const char * const mmcc_xo_dsi_hdmi_edp[] = { 142 "xo", 143 "edp_link_clk", 144 "hdmipll", 145 "edp_vco_div", 146 "dsi0pll", 147 "dsi1pll", 148 }; 149 150 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { 151 { P_XO, 0 }, 152 { P_EDPLINK, 4 }, 153 { P_HDMIPLL, 3 }, 154 { P_GPLL0, 5 }, 155 { P_DSI0PLL, 1 }, 156 { P_DSI1PLL, 2 } 157 }; 158 159 static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = { 160 "xo", 161 "edp_link_clk", 162 "hdmipll", 163 "gpll0_vote", 164 "dsi0pll", 165 "dsi1pll", 166 }; 167 168 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { 169 { P_XO, 0 }, 170 { P_EDPLINK, 4 }, 171 { P_HDMIPLL, 3 }, 172 { P_GPLL0, 5 }, 173 { P_DSI0PLL_BYTE, 1 }, 174 { P_DSI1PLL_BYTE, 2 } 175 }; 176 177 static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { 178 "xo", 179 "edp_link_clk", 180 "hdmipll", 181 "gpll0_vote", 182 "dsi0pllbyte", 183 "dsi1pllbyte", 184 }; 185 186 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 187 188 static struct clk_pll mmpll0 = { 189 .l_reg = 0x0004, 190 .m_reg = 0x0008, 191 .n_reg = 0x000c, 192 .config_reg = 0x0014, 193 .mode_reg = 0x0000, 194 .status_reg = 0x001c, 195 .status_bit = 17, 196 .clkr.hw.init = &(struct clk_init_data){ 197 .name = "mmpll0", 198 .parent_names = (const char *[]){ "xo" }, 199 .num_parents = 1, 200 .ops = &clk_pll_ops, 201 }, 202 }; 203 204 static struct clk_regmap mmpll0_vote = { 205 .enable_reg = 0x0100, 206 .enable_mask = BIT(0), 207 .hw.init = &(struct clk_init_data){ 208 .name = "mmpll0_vote", 209 .parent_names = (const char *[]){ "mmpll0" }, 210 .num_parents = 1, 211 .ops = &clk_pll_vote_ops, 212 }, 213 }; 214 215 static struct clk_pll mmpll1 = { 216 .l_reg = 0x0044, 217 .m_reg = 0x0048, 218 .n_reg = 0x004c, 219 .config_reg = 0x0050, 220 .mode_reg = 0x0040, 221 .status_reg = 0x005c, 222 .status_bit = 17, 223 .clkr.hw.init = &(struct clk_init_data){ 224 .name = "mmpll1", 225 .parent_names = (const char *[]){ "xo" }, 226 .num_parents = 1, 227 .ops = &clk_pll_ops, 228 }, 229 }; 230 231 static struct clk_regmap mmpll1_vote = { 232 .enable_reg = 0x0100, 233 .enable_mask = BIT(1), 234 .hw.init = &(struct clk_init_data){ 235 .name = "mmpll1_vote", 236 .parent_names = (const char *[]){ "mmpll1" }, 237 .num_parents = 1, 238 .ops = &clk_pll_vote_ops, 239 }, 240 }; 241 242 static struct clk_pll mmpll2 = { 243 .l_reg = 0x4104, 244 .m_reg = 0x4108, 245 .n_reg = 0x410c, 246 .config_reg = 0x4110, 247 .mode_reg = 0x4100, 248 .status_reg = 0x411c, 249 .clkr.hw.init = &(struct clk_init_data){ 250 .name = "mmpll2", 251 .parent_names = (const char *[]){ "xo" }, 252 .num_parents = 1, 253 .ops = &clk_pll_ops, 254 }, 255 }; 256 257 static struct clk_pll mmpll3 = { 258 .l_reg = 0x0084, 259 .m_reg = 0x0088, 260 .n_reg = 0x008c, 261 .config_reg = 0x0090, 262 .mode_reg = 0x0080, 263 .status_reg = 0x009c, 264 .status_bit = 17, 265 .clkr.hw.init = &(struct clk_init_data){ 266 .name = "mmpll3", 267 .parent_names = (const char *[]){ "xo" }, 268 .num_parents = 1, 269 .ops = &clk_pll_ops, 270 }, 271 }; 272 273 static struct clk_rcg2 mmss_ahb_clk_src = { 274 .cmd_rcgr = 0x5000, 275 .hid_width = 5, 276 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 277 .clkr.hw.init = &(struct clk_init_data){ 278 .name = "mmss_ahb_clk_src", 279 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 280 .num_parents = 4, 281 .ops = &clk_rcg2_ops, 282 }, 283 }; 284 285 static struct freq_tbl ftbl_mmss_axi_clk[] = { 286 F( 19200000, P_XO, 1, 0, 0), 287 F( 37500000, P_GPLL0, 16, 0, 0), 288 F( 50000000, P_GPLL0, 12, 0, 0), 289 F( 75000000, P_GPLL0, 8, 0, 0), 290 F(100000000, P_GPLL0, 6, 0, 0), 291 F(150000000, P_GPLL0, 4, 0, 0), 292 F(291750000, P_MMPLL1, 4, 0, 0), 293 F(400000000, P_MMPLL0, 2, 0, 0), 294 F(466800000, P_MMPLL1, 2.5, 0, 0), 295 }; 296 297 static struct clk_rcg2 mmss_axi_clk_src = { 298 .cmd_rcgr = 0x5040, 299 .hid_width = 5, 300 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 301 .freq_tbl = ftbl_mmss_axi_clk, 302 .clkr.hw.init = &(struct clk_init_data){ 303 .name = "mmss_axi_clk_src", 304 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 305 .num_parents = 4, 306 .ops = &clk_rcg2_ops, 307 }, 308 }; 309 310 static struct freq_tbl ftbl_ocmemnoc_clk[] = { 311 F( 19200000, P_XO, 1, 0, 0), 312 F( 37500000, P_GPLL0, 16, 0, 0), 313 F( 50000000, P_GPLL0, 12, 0, 0), 314 F( 75000000, P_GPLL0, 8, 0, 0), 315 F(100000000, P_GPLL0, 6, 0, 0), 316 F(150000000, P_GPLL0, 4, 0, 0), 317 F(291750000, P_MMPLL1, 4, 0, 0), 318 F(400000000, P_MMPLL0, 2, 0, 0), 319 }; 320 321 static struct clk_rcg2 ocmemnoc_clk_src = { 322 .cmd_rcgr = 0x5090, 323 .hid_width = 5, 324 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 325 .freq_tbl = ftbl_ocmemnoc_clk, 326 .clkr.hw.init = &(struct clk_init_data){ 327 .name = "ocmemnoc_clk_src", 328 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 329 .num_parents = 4, 330 .ops = &clk_rcg2_ops, 331 }, 332 }; 333 334 static struct freq_tbl ftbl_camss_csi0_3_clk[] = { 335 F(100000000, P_GPLL0, 6, 0, 0), 336 F(200000000, P_MMPLL0, 4, 0, 0), 337 { } 338 }; 339 340 static struct clk_rcg2 csi0_clk_src = { 341 .cmd_rcgr = 0x3090, 342 .hid_width = 5, 343 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 344 .freq_tbl = ftbl_camss_csi0_3_clk, 345 .clkr.hw.init = &(struct clk_init_data){ 346 .name = "csi0_clk_src", 347 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 348 .num_parents = 4, 349 .ops = &clk_rcg2_ops, 350 }, 351 }; 352 353 static struct clk_rcg2 csi1_clk_src = { 354 .cmd_rcgr = 0x3100, 355 .hid_width = 5, 356 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 357 .freq_tbl = ftbl_camss_csi0_3_clk, 358 .clkr.hw.init = &(struct clk_init_data){ 359 .name = "csi1_clk_src", 360 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 361 .num_parents = 4, 362 .ops = &clk_rcg2_ops, 363 }, 364 }; 365 366 static struct clk_rcg2 csi2_clk_src = { 367 .cmd_rcgr = 0x3160, 368 .hid_width = 5, 369 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 370 .freq_tbl = ftbl_camss_csi0_3_clk, 371 .clkr.hw.init = &(struct clk_init_data){ 372 .name = "csi2_clk_src", 373 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 374 .num_parents = 4, 375 .ops = &clk_rcg2_ops, 376 }, 377 }; 378 379 static struct clk_rcg2 csi3_clk_src = { 380 .cmd_rcgr = 0x31c0, 381 .hid_width = 5, 382 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 383 .freq_tbl = ftbl_camss_csi0_3_clk, 384 .clkr.hw.init = &(struct clk_init_data){ 385 .name = "csi3_clk_src", 386 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 387 .num_parents = 4, 388 .ops = &clk_rcg2_ops, 389 }, 390 }; 391 392 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = { 393 F(37500000, P_GPLL0, 16, 0, 0), 394 F(50000000, P_GPLL0, 12, 0, 0), 395 F(60000000, P_GPLL0, 10, 0, 0), 396 F(80000000, P_GPLL0, 7.5, 0, 0), 397 F(100000000, P_GPLL0, 6, 0, 0), 398 F(109090000, P_GPLL0, 5.5, 0, 0), 399 F(133330000, P_GPLL0, 4.5, 0, 0), 400 F(200000000, P_GPLL0, 3, 0, 0), 401 F(228570000, P_MMPLL0, 3.5, 0, 0), 402 F(266670000, P_MMPLL0, 3, 0, 0), 403 F(320000000, P_MMPLL0, 2.5, 0, 0), 404 F(400000000, P_MMPLL0, 2, 0, 0), 405 F(465000000, P_MMPLL3, 2, 0, 0), 406 { } 407 }; 408 409 static struct clk_rcg2 vfe0_clk_src = { 410 .cmd_rcgr = 0x3600, 411 .hid_width = 5, 412 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 413 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, 414 .clkr.hw.init = &(struct clk_init_data){ 415 .name = "vfe0_clk_src", 416 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 417 .num_parents = 4, 418 .ops = &clk_rcg2_ops, 419 }, 420 }; 421 422 static struct clk_rcg2 vfe1_clk_src = { 423 .cmd_rcgr = 0x3620, 424 .hid_width = 5, 425 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 426 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, 427 .clkr.hw.init = &(struct clk_init_data){ 428 .name = "vfe1_clk_src", 429 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 430 .num_parents = 4, 431 .ops = &clk_rcg2_ops, 432 }, 433 }; 434 435 static struct freq_tbl ftbl_mdss_mdp_clk[] = { 436 F(37500000, P_GPLL0, 16, 0, 0), 437 F(60000000, P_GPLL0, 10, 0, 0), 438 F(75000000, P_GPLL0, 8, 0, 0), 439 F(85710000, P_GPLL0, 7, 0, 0), 440 F(100000000, P_GPLL0, 6, 0, 0), 441 F(133330000, P_MMPLL0, 6, 0, 0), 442 F(160000000, P_MMPLL0, 5, 0, 0), 443 F(200000000, P_MMPLL0, 4, 0, 0), 444 F(228570000, P_MMPLL0, 3.5, 0, 0), 445 F(240000000, P_GPLL0, 2.5, 0, 0), 446 F(266670000, P_MMPLL0, 3, 0, 0), 447 F(320000000, P_MMPLL0, 2.5, 0, 0), 448 { } 449 }; 450 451 static struct clk_rcg2 mdp_clk_src = { 452 .cmd_rcgr = 0x2040, 453 .hid_width = 5, 454 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map, 455 .freq_tbl = ftbl_mdss_mdp_clk, 456 .clkr.hw.init = &(struct clk_init_data){ 457 .name = "mdp_clk_src", 458 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0, 459 .num_parents = 6, 460 .ops = &clk_rcg2_ops, 461 }, 462 }; 463 464 static struct clk_rcg2 gfx3d_clk_src = { 465 .cmd_rcgr = 0x4000, 466 .hid_width = 5, 467 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map, 468 .clkr.hw.init = &(struct clk_init_data){ 469 .name = "gfx3d_clk_src", 470 .parent_names = mmcc_xo_mmpll0_1_2_gpll0, 471 .num_parents = 5, 472 .ops = &clk_rcg2_ops, 473 }, 474 }; 475 476 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = { 477 F(75000000, P_GPLL0, 8, 0, 0), 478 F(133330000, P_GPLL0, 4.5, 0, 0), 479 F(200000000, P_GPLL0, 3, 0, 0), 480 F(228570000, P_MMPLL0, 3.5, 0, 0), 481 F(266670000, P_MMPLL0, 3, 0, 0), 482 F(320000000, P_MMPLL0, 2.5, 0, 0), 483 { } 484 }; 485 486 static struct clk_rcg2 jpeg0_clk_src = { 487 .cmd_rcgr = 0x3500, 488 .hid_width = 5, 489 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 490 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 491 .clkr.hw.init = &(struct clk_init_data){ 492 .name = "jpeg0_clk_src", 493 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 494 .num_parents = 4, 495 .ops = &clk_rcg2_ops, 496 }, 497 }; 498 499 static struct clk_rcg2 jpeg1_clk_src = { 500 .cmd_rcgr = 0x3520, 501 .hid_width = 5, 502 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 503 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 504 .clkr.hw.init = &(struct clk_init_data){ 505 .name = "jpeg1_clk_src", 506 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 507 .num_parents = 4, 508 .ops = &clk_rcg2_ops, 509 }, 510 }; 511 512 static struct clk_rcg2 jpeg2_clk_src = { 513 .cmd_rcgr = 0x3540, 514 .hid_width = 5, 515 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 516 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 517 .clkr.hw.init = &(struct clk_init_data){ 518 .name = "jpeg2_clk_src", 519 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 520 .num_parents = 4, 521 .ops = &clk_rcg2_ops, 522 }, 523 }; 524 525 static struct freq_tbl pixel_freq_tbl[] = { 526 { .src = P_DSI0PLL }, 527 { } 528 }; 529 530 static struct clk_rcg2 pclk0_clk_src = { 531 .cmd_rcgr = 0x2000, 532 .mnd_width = 8, 533 .hid_width = 5, 534 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 535 .freq_tbl = pixel_freq_tbl, 536 .clkr.hw.init = &(struct clk_init_data){ 537 .name = "pclk0_clk_src", 538 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, 539 .num_parents = 6, 540 .ops = &clk_pixel_ops, 541 .flags = CLK_SET_RATE_PARENT, 542 }, 543 }; 544 545 static struct clk_rcg2 pclk1_clk_src = { 546 .cmd_rcgr = 0x2020, 547 .mnd_width = 8, 548 .hid_width = 5, 549 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 550 .freq_tbl = pixel_freq_tbl, 551 .clkr.hw.init = &(struct clk_init_data){ 552 .name = "pclk1_clk_src", 553 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, 554 .num_parents = 6, 555 .ops = &clk_pixel_ops, 556 .flags = CLK_SET_RATE_PARENT, 557 }, 558 }; 559 560 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = { 561 F(50000000, P_GPLL0, 12, 0, 0), 562 F(100000000, P_GPLL0, 6, 0, 0), 563 F(133330000, P_MMPLL0, 6, 0, 0), 564 F(200000000, P_MMPLL0, 4, 0, 0), 565 F(266670000, P_MMPLL0, 3, 0, 0), 566 F(465000000, P_MMPLL3, 2, 0, 0), 567 { } 568 }; 569 570 static struct clk_rcg2 vcodec0_clk_src = { 571 .cmd_rcgr = 0x1000, 572 .mnd_width = 8, 573 .hid_width = 5, 574 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map, 575 .freq_tbl = ftbl_venus0_vcodec0_clk, 576 .clkr.hw.init = &(struct clk_init_data){ 577 .name = "vcodec0_clk_src", 578 .parent_names = mmcc_xo_mmpll0_1_3_gpll0, 579 .num_parents = 5, 580 .ops = &clk_rcg2_ops, 581 }, 582 }; 583 584 static struct freq_tbl ftbl_camss_cci_cci_clk[] = { 585 F(19200000, P_XO, 1, 0, 0), 586 { } 587 }; 588 589 static struct clk_rcg2 cci_clk_src = { 590 .cmd_rcgr = 0x3300, 591 .hid_width = 5, 592 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 593 .freq_tbl = ftbl_camss_cci_cci_clk, 594 .clkr.hw.init = &(struct clk_init_data){ 595 .name = "cci_clk_src", 596 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 597 .num_parents = 4, 598 .ops = &clk_rcg2_ops, 599 }, 600 }; 601 602 static struct freq_tbl ftbl_camss_gp0_1_clk[] = { 603 F(10000, P_XO, 16, 1, 120), 604 F(24000, P_XO, 16, 1, 50), 605 F(6000000, P_GPLL0, 10, 1, 10), 606 F(12000000, P_GPLL0, 10, 1, 5), 607 F(13000000, P_GPLL0, 4, 13, 150), 608 F(24000000, P_GPLL0, 5, 1, 5), 609 { } 610 }; 611 612 static struct clk_rcg2 camss_gp0_clk_src = { 613 .cmd_rcgr = 0x3420, 614 .mnd_width = 8, 615 .hid_width = 5, 616 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map, 617 .freq_tbl = ftbl_camss_gp0_1_clk, 618 .clkr.hw.init = &(struct clk_init_data){ 619 .name = "camss_gp0_clk_src", 620 .parent_names = mmcc_xo_mmpll0_1_gpll1_0, 621 .num_parents = 5, 622 .ops = &clk_rcg2_ops, 623 }, 624 }; 625 626 static struct clk_rcg2 camss_gp1_clk_src = { 627 .cmd_rcgr = 0x3450, 628 .mnd_width = 8, 629 .hid_width = 5, 630 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map, 631 .freq_tbl = ftbl_camss_gp0_1_clk, 632 .clkr.hw.init = &(struct clk_init_data){ 633 .name = "camss_gp1_clk_src", 634 .parent_names = mmcc_xo_mmpll0_1_gpll1_0, 635 .num_parents = 5, 636 .ops = &clk_rcg2_ops, 637 }, 638 }; 639 640 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = { 641 F(4800000, P_XO, 4, 0, 0), 642 F(6000000, P_GPLL0, 10, 1, 10), 643 F(8000000, P_GPLL0, 15, 1, 5), 644 F(9600000, P_XO, 2, 0, 0), 645 F(16000000, P_GPLL0, 12.5, 1, 3), 646 F(19200000, P_XO, 1, 0, 0), 647 F(24000000, P_GPLL0, 5, 1, 5), 648 F(32000000, P_MMPLL0, 5, 1, 5), 649 F(48000000, P_GPLL0, 12.5, 0, 0), 650 F(64000000, P_MMPLL0, 12.5, 0, 0), 651 F(66670000, P_GPLL0, 9, 0, 0), 652 { } 653 }; 654 655 static struct clk_rcg2 mclk0_clk_src = { 656 .cmd_rcgr = 0x3360, 657 .hid_width = 5, 658 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 659 .freq_tbl = ftbl_camss_mclk0_3_clk, 660 .clkr.hw.init = &(struct clk_init_data){ 661 .name = "mclk0_clk_src", 662 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 663 .num_parents = 4, 664 .ops = &clk_rcg2_ops, 665 }, 666 }; 667 668 static struct clk_rcg2 mclk1_clk_src = { 669 .cmd_rcgr = 0x3390, 670 .hid_width = 5, 671 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 672 .freq_tbl = ftbl_camss_mclk0_3_clk, 673 .clkr.hw.init = &(struct clk_init_data){ 674 .name = "mclk1_clk_src", 675 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 676 .num_parents = 4, 677 .ops = &clk_rcg2_ops, 678 }, 679 }; 680 681 static struct clk_rcg2 mclk2_clk_src = { 682 .cmd_rcgr = 0x33c0, 683 .hid_width = 5, 684 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 685 .freq_tbl = ftbl_camss_mclk0_3_clk, 686 .clkr.hw.init = &(struct clk_init_data){ 687 .name = "mclk2_clk_src", 688 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 689 .num_parents = 4, 690 .ops = &clk_rcg2_ops, 691 }, 692 }; 693 694 static struct clk_rcg2 mclk3_clk_src = { 695 .cmd_rcgr = 0x33f0, 696 .hid_width = 5, 697 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 698 .freq_tbl = ftbl_camss_mclk0_3_clk, 699 .clkr.hw.init = &(struct clk_init_data){ 700 .name = "mclk3_clk_src", 701 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 702 .num_parents = 4, 703 .ops = &clk_rcg2_ops, 704 }, 705 }; 706 707 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = { 708 F(100000000, P_GPLL0, 6, 0, 0), 709 F(200000000, P_MMPLL0, 4, 0, 0), 710 { } 711 }; 712 713 static struct clk_rcg2 csi0phytimer_clk_src = { 714 .cmd_rcgr = 0x3000, 715 .hid_width = 5, 716 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 717 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 718 .clkr.hw.init = &(struct clk_init_data){ 719 .name = "csi0phytimer_clk_src", 720 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 721 .num_parents = 4, 722 .ops = &clk_rcg2_ops, 723 }, 724 }; 725 726 static struct clk_rcg2 csi1phytimer_clk_src = { 727 .cmd_rcgr = 0x3030, 728 .hid_width = 5, 729 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 730 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 731 .clkr.hw.init = &(struct clk_init_data){ 732 .name = "csi1phytimer_clk_src", 733 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 734 .num_parents = 4, 735 .ops = &clk_rcg2_ops, 736 }, 737 }; 738 739 static struct clk_rcg2 csi2phytimer_clk_src = { 740 .cmd_rcgr = 0x3060, 741 .hid_width = 5, 742 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 743 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 744 .clkr.hw.init = &(struct clk_init_data){ 745 .name = "csi2phytimer_clk_src", 746 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 747 .num_parents = 4, 748 .ops = &clk_rcg2_ops, 749 }, 750 }; 751 752 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = { 753 F(133330000, P_GPLL0, 4.5, 0, 0), 754 F(266670000, P_MMPLL0, 3, 0, 0), 755 F(320000000, P_MMPLL0, 2.5, 0, 0), 756 F(400000000, P_MMPLL0, 2, 0, 0), 757 F(465000000, P_MMPLL3, 2, 0, 0), 758 { } 759 }; 760 761 static struct clk_rcg2 cpp_clk_src = { 762 .cmd_rcgr = 0x3640, 763 .hid_width = 5, 764 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 765 .freq_tbl = ftbl_camss_vfe_cpp_clk, 766 .clkr.hw.init = &(struct clk_init_data){ 767 .name = "cpp_clk_src", 768 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 769 .num_parents = 4, 770 .ops = &clk_rcg2_ops, 771 }, 772 }; 773 774 static struct freq_tbl byte_freq_tbl[] = { 775 { .src = P_DSI0PLL_BYTE }, 776 { } 777 }; 778 779 static struct clk_rcg2 byte0_clk_src = { 780 .cmd_rcgr = 0x2120, 781 .hid_width = 5, 782 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 783 .freq_tbl = byte_freq_tbl, 784 .clkr.hw.init = &(struct clk_init_data){ 785 .name = "byte0_clk_src", 786 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, 787 .num_parents = 6, 788 .ops = &clk_byte_ops, 789 .flags = CLK_SET_RATE_PARENT, 790 }, 791 }; 792 793 static struct clk_rcg2 byte1_clk_src = { 794 .cmd_rcgr = 0x2140, 795 .hid_width = 5, 796 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 797 .freq_tbl = byte_freq_tbl, 798 .clkr.hw.init = &(struct clk_init_data){ 799 .name = "byte1_clk_src", 800 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, 801 .num_parents = 6, 802 .ops = &clk_byte_ops, 803 .flags = CLK_SET_RATE_PARENT, 804 }, 805 }; 806 807 static struct freq_tbl ftbl_mdss_edpaux_clk[] = { 808 F(19200000, P_XO, 1, 0, 0), 809 { } 810 }; 811 812 static struct clk_rcg2 edpaux_clk_src = { 813 .cmd_rcgr = 0x20e0, 814 .hid_width = 5, 815 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 816 .freq_tbl = ftbl_mdss_edpaux_clk, 817 .clkr.hw.init = &(struct clk_init_data){ 818 .name = "edpaux_clk_src", 819 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 820 .num_parents = 4, 821 .ops = &clk_rcg2_ops, 822 }, 823 }; 824 825 static struct freq_tbl ftbl_mdss_edplink_clk[] = { 826 F(135000000, P_EDPLINK, 2, 0, 0), 827 F(270000000, P_EDPLINK, 11, 0, 0), 828 { } 829 }; 830 831 static struct clk_rcg2 edplink_clk_src = { 832 .cmd_rcgr = 0x20c0, 833 .hid_width = 5, 834 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 835 .freq_tbl = ftbl_mdss_edplink_clk, 836 .clkr.hw.init = &(struct clk_init_data){ 837 .name = "edplink_clk_src", 838 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, 839 .num_parents = 6, 840 .ops = &clk_rcg2_ops, 841 .flags = CLK_SET_RATE_PARENT, 842 }, 843 }; 844 845 static struct freq_tbl edp_pixel_freq_tbl[] = { 846 { .src = P_EDPVCO }, 847 { } 848 }; 849 850 static struct clk_rcg2 edppixel_clk_src = { 851 .cmd_rcgr = 0x20a0, 852 .mnd_width = 8, 853 .hid_width = 5, 854 .parent_map = mmcc_xo_dsi_hdmi_edp_map, 855 .freq_tbl = edp_pixel_freq_tbl, 856 .clkr.hw.init = &(struct clk_init_data){ 857 .name = "edppixel_clk_src", 858 .parent_names = mmcc_xo_dsi_hdmi_edp, 859 .num_parents = 6, 860 .ops = &clk_edp_pixel_ops, 861 }, 862 }; 863 864 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { 865 F(19200000, P_XO, 1, 0, 0), 866 { } 867 }; 868 869 static struct clk_rcg2 esc0_clk_src = { 870 .cmd_rcgr = 0x2160, 871 .hid_width = 5, 872 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 873 .freq_tbl = ftbl_mdss_esc0_1_clk, 874 .clkr.hw.init = &(struct clk_init_data){ 875 .name = "esc0_clk_src", 876 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, 877 .num_parents = 6, 878 .ops = &clk_rcg2_ops, 879 }, 880 }; 881 882 static struct clk_rcg2 esc1_clk_src = { 883 .cmd_rcgr = 0x2180, 884 .hid_width = 5, 885 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 886 .freq_tbl = ftbl_mdss_esc0_1_clk, 887 .clkr.hw.init = &(struct clk_init_data){ 888 .name = "esc1_clk_src", 889 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, 890 .num_parents = 6, 891 .ops = &clk_rcg2_ops, 892 }, 893 }; 894 895 static struct freq_tbl extpclk_freq_tbl[] = { 896 { .src = P_HDMIPLL }, 897 { } 898 }; 899 900 static struct clk_rcg2 extpclk_clk_src = { 901 .cmd_rcgr = 0x2060, 902 .hid_width = 5, 903 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 904 .freq_tbl = extpclk_freq_tbl, 905 .clkr.hw.init = &(struct clk_init_data){ 906 .name = "extpclk_clk_src", 907 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, 908 .num_parents = 6, 909 .ops = &clk_byte_ops, 910 .flags = CLK_SET_RATE_PARENT, 911 }, 912 }; 913 914 static struct freq_tbl ftbl_mdss_hdmi_clk[] = { 915 F(19200000, P_XO, 1, 0, 0), 916 { } 917 }; 918 919 static struct clk_rcg2 hdmi_clk_src = { 920 .cmd_rcgr = 0x2100, 921 .hid_width = 5, 922 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 923 .freq_tbl = ftbl_mdss_hdmi_clk, 924 .clkr.hw.init = &(struct clk_init_data){ 925 .name = "hdmi_clk_src", 926 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 927 .num_parents = 4, 928 .ops = &clk_rcg2_ops, 929 }, 930 }; 931 932 static struct freq_tbl ftbl_mdss_vsync_clk[] = { 933 F(19200000, P_XO, 1, 0, 0), 934 { } 935 }; 936 937 static struct clk_rcg2 vsync_clk_src = { 938 .cmd_rcgr = 0x2080, 939 .hid_width = 5, 940 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 941 .freq_tbl = ftbl_mdss_vsync_clk, 942 .clkr.hw.init = &(struct clk_init_data){ 943 .name = "vsync_clk_src", 944 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, 945 .num_parents = 4, 946 .ops = &clk_rcg2_ops, 947 }, 948 }; 949 950 static struct clk_branch camss_cci_cci_ahb_clk = { 951 .halt_reg = 0x3348, 952 .clkr = { 953 .enable_reg = 0x3348, 954 .enable_mask = BIT(0), 955 .hw.init = &(struct clk_init_data){ 956 .name = "camss_cci_cci_ahb_clk", 957 .parent_names = (const char *[]){ 958 "mmss_ahb_clk_src", 959 }, 960 .num_parents = 1, 961 .ops = &clk_branch2_ops, 962 }, 963 }, 964 }; 965 966 static struct clk_branch camss_cci_cci_clk = { 967 .halt_reg = 0x3344, 968 .clkr = { 969 .enable_reg = 0x3344, 970 .enable_mask = BIT(0), 971 .hw.init = &(struct clk_init_data){ 972 .name = "camss_cci_cci_clk", 973 .parent_names = (const char *[]){ 974 "cci_clk_src", 975 }, 976 .num_parents = 1, 977 .flags = CLK_SET_RATE_PARENT, 978 .ops = &clk_branch2_ops, 979 }, 980 }, 981 }; 982 983 static struct clk_branch camss_csi0_ahb_clk = { 984 .halt_reg = 0x30bc, 985 .clkr = { 986 .enable_reg = 0x30bc, 987 .enable_mask = BIT(0), 988 .hw.init = &(struct clk_init_data){ 989 .name = "camss_csi0_ahb_clk", 990 .parent_names = (const char *[]){ 991 "mmss_ahb_clk_src", 992 }, 993 .num_parents = 1, 994 .ops = &clk_branch2_ops, 995 }, 996 }, 997 }; 998 999 static struct clk_branch camss_csi0_clk = { 1000 .halt_reg = 0x30b4, 1001 .clkr = { 1002 .enable_reg = 0x30b4, 1003 .enable_mask = BIT(0), 1004 .hw.init = &(struct clk_init_data){ 1005 .name = "camss_csi0_clk", 1006 .parent_names = (const char *[]){ 1007 "csi0_clk_src", 1008 }, 1009 .num_parents = 1, 1010 .flags = CLK_SET_RATE_PARENT, 1011 .ops = &clk_branch2_ops, 1012 }, 1013 }, 1014 }; 1015 1016 static struct clk_branch camss_csi0phy_clk = { 1017 .halt_reg = 0x30c4, 1018 .clkr = { 1019 .enable_reg = 0x30c4, 1020 .enable_mask = BIT(0), 1021 .hw.init = &(struct clk_init_data){ 1022 .name = "camss_csi0phy_clk", 1023 .parent_names = (const char *[]){ 1024 "csi0_clk_src", 1025 }, 1026 .num_parents = 1, 1027 .flags = CLK_SET_RATE_PARENT, 1028 .ops = &clk_branch2_ops, 1029 }, 1030 }, 1031 }; 1032 1033 static struct clk_branch camss_csi0pix_clk = { 1034 .halt_reg = 0x30e4, 1035 .clkr = { 1036 .enable_reg = 0x30e4, 1037 .enable_mask = BIT(0), 1038 .hw.init = &(struct clk_init_data){ 1039 .name = "camss_csi0pix_clk", 1040 .parent_names = (const char *[]){ 1041 "csi0_clk_src", 1042 }, 1043 .num_parents = 1, 1044 .flags = CLK_SET_RATE_PARENT, 1045 .ops = &clk_branch2_ops, 1046 }, 1047 }, 1048 }; 1049 1050 static struct clk_branch camss_csi0rdi_clk = { 1051 .halt_reg = 0x30d4, 1052 .clkr = { 1053 .enable_reg = 0x30d4, 1054 .enable_mask = BIT(0), 1055 .hw.init = &(struct clk_init_data){ 1056 .name = "camss_csi0rdi_clk", 1057 .parent_names = (const char *[]){ 1058 "csi0_clk_src", 1059 }, 1060 .num_parents = 1, 1061 .flags = CLK_SET_RATE_PARENT, 1062 .ops = &clk_branch2_ops, 1063 }, 1064 }, 1065 }; 1066 1067 static struct clk_branch camss_csi1_ahb_clk = { 1068 .halt_reg = 0x3128, 1069 .clkr = { 1070 .enable_reg = 0x3128, 1071 .enable_mask = BIT(0), 1072 .hw.init = &(struct clk_init_data){ 1073 .name = "camss_csi1_ahb_clk", 1074 .parent_names = (const char *[]){ 1075 "mmss_ahb_clk_src", 1076 }, 1077 .num_parents = 1, 1078 .ops = &clk_branch2_ops, 1079 }, 1080 }, 1081 }; 1082 1083 static struct clk_branch camss_csi1_clk = { 1084 .halt_reg = 0x3124, 1085 .clkr = { 1086 .enable_reg = 0x3124, 1087 .enable_mask = BIT(0), 1088 .hw.init = &(struct clk_init_data){ 1089 .name = "camss_csi1_clk", 1090 .parent_names = (const char *[]){ 1091 "csi1_clk_src", 1092 }, 1093 .num_parents = 1, 1094 .flags = CLK_SET_RATE_PARENT, 1095 .ops = &clk_branch2_ops, 1096 }, 1097 }, 1098 }; 1099 1100 static struct clk_branch camss_csi1phy_clk = { 1101 .halt_reg = 0x3134, 1102 .clkr = { 1103 .enable_reg = 0x3134, 1104 .enable_mask = BIT(0), 1105 .hw.init = &(struct clk_init_data){ 1106 .name = "camss_csi1phy_clk", 1107 .parent_names = (const char *[]){ 1108 "csi1_clk_src", 1109 }, 1110 .num_parents = 1, 1111 .flags = CLK_SET_RATE_PARENT, 1112 .ops = &clk_branch2_ops, 1113 }, 1114 }, 1115 }; 1116 1117 static struct clk_branch camss_csi1pix_clk = { 1118 .halt_reg = 0x3154, 1119 .clkr = { 1120 .enable_reg = 0x3154, 1121 .enable_mask = BIT(0), 1122 .hw.init = &(struct clk_init_data){ 1123 .name = "camss_csi1pix_clk", 1124 .parent_names = (const char *[]){ 1125 "csi1_clk_src", 1126 }, 1127 .num_parents = 1, 1128 .flags = CLK_SET_RATE_PARENT, 1129 .ops = &clk_branch2_ops, 1130 }, 1131 }, 1132 }; 1133 1134 static struct clk_branch camss_csi1rdi_clk = { 1135 .halt_reg = 0x3144, 1136 .clkr = { 1137 .enable_reg = 0x3144, 1138 .enable_mask = BIT(0), 1139 .hw.init = &(struct clk_init_data){ 1140 .name = "camss_csi1rdi_clk", 1141 .parent_names = (const char *[]){ 1142 "csi1_clk_src", 1143 }, 1144 .num_parents = 1, 1145 .flags = CLK_SET_RATE_PARENT, 1146 .ops = &clk_branch2_ops, 1147 }, 1148 }, 1149 }; 1150 1151 static struct clk_branch camss_csi2_ahb_clk = { 1152 .halt_reg = 0x3188, 1153 .clkr = { 1154 .enable_reg = 0x3188, 1155 .enable_mask = BIT(0), 1156 .hw.init = &(struct clk_init_data){ 1157 .name = "camss_csi2_ahb_clk", 1158 .parent_names = (const char *[]){ 1159 "mmss_ahb_clk_src", 1160 }, 1161 .num_parents = 1, 1162 .ops = &clk_branch2_ops, 1163 }, 1164 }, 1165 }; 1166 1167 static struct clk_branch camss_csi2_clk = { 1168 .halt_reg = 0x3184, 1169 .clkr = { 1170 .enable_reg = 0x3184, 1171 .enable_mask = BIT(0), 1172 .hw.init = &(struct clk_init_data){ 1173 .name = "camss_csi2_clk", 1174 .parent_names = (const char *[]){ 1175 "csi2_clk_src", 1176 }, 1177 .num_parents = 1, 1178 .flags = CLK_SET_RATE_PARENT, 1179 .ops = &clk_branch2_ops, 1180 }, 1181 }, 1182 }; 1183 1184 static struct clk_branch camss_csi2phy_clk = { 1185 .halt_reg = 0x3194, 1186 .clkr = { 1187 .enable_reg = 0x3194, 1188 .enable_mask = BIT(0), 1189 .hw.init = &(struct clk_init_data){ 1190 .name = "camss_csi2phy_clk", 1191 .parent_names = (const char *[]){ 1192 "csi2_clk_src", 1193 }, 1194 .num_parents = 1, 1195 .flags = CLK_SET_RATE_PARENT, 1196 .ops = &clk_branch2_ops, 1197 }, 1198 }, 1199 }; 1200 1201 static struct clk_branch camss_csi2pix_clk = { 1202 .halt_reg = 0x31b4, 1203 .clkr = { 1204 .enable_reg = 0x31b4, 1205 .enable_mask = BIT(0), 1206 .hw.init = &(struct clk_init_data){ 1207 .name = "camss_csi2pix_clk", 1208 .parent_names = (const char *[]){ 1209 "csi2_clk_src", 1210 }, 1211 .num_parents = 1, 1212 .flags = CLK_SET_RATE_PARENT, 1213 .ops = &clk_branch2_ops, 1214 }, 1215 }, 1216 }; 1217 1218 static struct clk_branch camss_csi2rdi_clk = { 1219 .halt_reg = 0x31a4, 1220 .clkr = { 1221 .enable_reg = 0x31a4, 1222 .enable_mask = BIT(0), 1223 .hw.init = &(struct clk_init_data){ 1224 .name = "camss_csi2rdi_clk", 1225 .parent_names = (const char *[]){ 1226 "csi2_clk_src", 1227 }, 1228 .num_parents = 1, 1229 .flags = CLK_SET_RATE_PARENT, 1230 .ops = &clk_branch2_ops, 1231 }, 1232 }, 1233 }; 1234 1235 static struct clk_branch camss_csi3_ahb_clk = { 1236 .halt_reg = 0x31e8, 1237 .clkr = { 1238 .enable_reg = 0x31e8, 1239 .enable_mask = BIT(0), 1240 .hw.init = &(struct clk_init_data){ 1241 .name = "camss_csi3_ahb_clk", 1242 .parent_names = (const char *[]){ 1243 "mmss_ahb_clk_src", 1244 }, 1245 .num_parents = 1, 1246 .ops = &clk_branch2_ops, 1247 }, 1248 }, 1249 }; 1250 1251 static struct clk_branch camss_csi3_clk = { 1252 .halt_reg = 0x31e4, 1253 .clkr = { 1254 .enable_reg = 0x31e4, 1255 .enable_mask = BIT(0), 1256 .hw.init = &(struct clk_init_data){ 1257 .name = "camss_csi3_clk", 1258 .parent_names = (const char *[]){ 1259 "csi3_clk_src", 1260 }, 1261 .num_parents = 1, 1262 .flags = CLK_SET_RATE_PARENT, 1263 .ops = &clk_branch2_ops, 1264 }, 1265 }, 1266 }; 1267 1268 static struct clk_branch camss_csi3phy_clk = { 1269 .halt_reg = 0x31f4, 1270 .clkr = { 1271 .enable_reg = 0x31f4, 1272 .enable_mask = BIT(0), 1273 .hw.init = &(struct clk_init_data){ 1274 .name = "camss_csi3phy_clk", 1275 .parent_names = (const char *[]){ 1276 "csi3_clk_src", 1277 }, 1278 .num_parents = 1, 1279 .flags = CLK_SET_RATE_PARENT, 1280 .ops = &clk_branch2_ops, 1281 }, 1282 }, 1283 }; 1284 1285 static struct clk_branch camss_csi3pix_clk = { 1286 .halt_reg = 0x3214, 1287 .clkr = { 1288 .enable_reg = 0x3214, 1289 .enable_mask = BIT(0), 1290 .hw.init = &(struct clk_init_data){ 1291 .name = "camss_csi3pix_clk", 1292 .parent_names = (const char *[]){ 1293 "csi3_clk_src", 1294 }, 1295 .num_parents = 1, 1296 .flags = CLK_SET_RATE_PARENT, 1297 .ops = &clk_branch2_ops, 1298 }, 1299 }, 1300 }; 1301 1302 static struct clk_branch camss_csi3rdi_clk = { 1303 .halt_reg = 0x3204, 1304 .clkr = { 1305 .enable_reg = 0x3204, 1306 .enable_mask = BIT(0), 1307 .hw.init = &(struct clk_init_data){ 1308 .name = "camss_csi3rdi_clk", 1309 .parent_names = (const char *[]){ 1310 "csi3_clk_src", 1311 }, 1312 .num_parents = 1, 1313 .flags = CLK_SET_RATE_PARENT, 1314 .ops = &clk_branch2_ops, 1315 }, 1316 }, 1317 }; 1318 1319 static struct clk_branch camss_csi_vfe0_clk = { 1320 .halt_reg = 0x3704, 1321 .clkr = { 1322 .enable_reg = 0x3704, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(struct clk_init_data){ 1325 .name = "camss_csi_vfe0_clk", 1326 .parent_names = (const char *[]){ 1327 "vfe0_clk_src", 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch camss_csi_vfe1_clk = { 1337 .halt_reg = 0x3714, 1338 .clkr = { 1339 .enable_reg = 0x3714, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(struct clk_init_data){ 1342 .name = "camss_csi_vfe1_clk", 1343 .parent_names = (const char *[]){ 1344 "vfe1_clk_src", 1345 }, 1346 .num_parents = 1, 1347 .flags = CLK_SET_RATE_PARENT, 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351 }; 1352 1353 static struct clk_branch camss_gp0_clk = { 1354 .halt_reg = 0x3444, 1355 .clkr = { 1356 .enable_reg = 0x3444, 1357 .enable_mask = BIT(0), 1358 .hw.init = &(struct clk_init_data){ 1359 .name = "camss_gp0_clk", 1360 .parent_names = (const char *[]){ 1361 "camss_gp0_clk_src", 1362 }, 1363 .num_parents = 1, 1364 .flags = CLK_SET_RATE_PARENT, 1365 .ops = &clk_branch2_ops, 1366 }, 1367 }, 1368 }; 1369 1370 static struct clk_branch camss_gp1_clk = { 1371 .halt_reg = 0x3474, 1372 .clkr = { 1373 .enable_reg = 0x3474, 1374 .enable_mask = BIT(0), 1375 .hw.init = &(struct clk_init_data){ 1376 .name = "camss_gp1_clk", 1377 .parent_names = (const char *[]){ 1378 "camss_gp1_clk_src", 1379 }, 1380 .num_parents = 1, 1381 .flags = CLK_SET_RATE_PARENT, 1382 .ops = &clk_branch2_ops, 1383 }, 1384 }, 1385 }; 1386 1387 static struct clk_branch camss_ispif_ahb_clk = { 1388 .halt_reg = 0x3224, 1389 .clkr = { 1390 .enable_reg = 0x3224, 1391 .enable_mask = BIT(0), 1392 .hw.init = &(struct clk_init_data){ 1393 .name = "camss_ispif_ahb_clk", 1394 .parent_names = (const char *[]){ 1395 "mmss_ahb_clk_src", 1396 }, 1397 .num_parents = 1, 1398 .ops = &clk_branch2_ops, 1399 }, 1400 }, 1401 }; 1402 1403 static struct clk_branch camss_jpeg_jpeg0_clk = { 1404 .halt_reg = 0x35a8, 1405 .clkr = { 1406 .enable_reg = 0x35a8, 1407 .enable_mask = BIT(0), 1408 .hw.init = &(struct clk_init_data){ 1409 .name = "camss_jpeg_jpeg0_clk", 1410 .parent_names = (const char *[]){ 1411 "jpeg0_clk_src", 1412 }, 1413 .num_parents = 1, 1414 .flags = CLK_SET_RATE_PARENT, 1415 .ops = &clk_branch2_ops, 1416 }, 1417 }, 1418 }; 1419 1420 static struct clk_branch camss_jpeg_jpeg1_clk = { 1421 .halt_reg = 0x35ac, 1422 .clkr = { 1423 .enable_reg = 0x35ac, 1424 .enable_mask = BIT(0), 1425 .hw.init = &(struct clk_init_data){ 1426 .name = "camss_jpeg_jpeg1_clk", 1427 .parent_names = (const char *[]){ 1428 "jpeg1_clk_src", 1429 }, 1430 .num_parents = 1, 1431 .flags = CLK_SET_RATE_PARENT, 1432 .ops = &clk_branch2_ops, 1433 }, 1434 }, 1435 }; 1436 1437 static struct clk_branch camss_jpeg_jpeg2_clk = { 1438 .halt_reg = 0x35b0, 1439 .clkr = { 1440 .enable_reg = 0x35b0, 1441 .enable_mask = BIT(0), 1442 .hw.init = &(struct clk_init_data){ 1443 .name = "camss_jpeg_jpeg2_clk", 1444 .parent_names = (const char *[]){ 1445 "jpeg2_clk_src", 1446 }, 1447 .num_parents = 1, 1448 .flags = CLK_SET_RATE_PARENT, 1449 .ops = &clk_branch2_ops, 1450 }, 1451 }, 1452 }; 1453 1454 static struct clk_branch camss_jpeg_jpeg_ahb_clk = { 1455 .halt_reg = 0x35b4, 1456 .clkr = { 1457 .enable_reg = 0x35b4, 1458 .enable_mask = BIT(0), 1459 .hw.init = &(struct clk_init_data){ 1460 .name = "camss_jpeg_jpeg_ahb_clk", 1461 .parent_names = (const char *[]){ 1462 "mmss_ahb_clk_src", 1463 }, 1464 .num_parents = 1, 1465 .ops = &clk_branch2_ops, 1466 }, 1467 }, 1468 }; 1469 1470 static struct clk_branch camss_jpeg_jpeg_axi_clk = { 1471 .halt_reg = 0x35b8, 1472 .clkr = { 1473 .enable_reg = 0x35b8, 1474 .enable_mask = BIT(0), 1475 .hw.init = &(struct clk_init_data){ 1476 .name = "camss_jpeg_jpeg_axi_clk", 1477 .parent_names = (const char *[]){ 1478 "mmss_axi_clk_src", 1479 }, 1480 .num_parents = 1, 1481 .ops = &clk_branch2_ops, 1482 }, 1483 }, 1484 }; 1485 1486 static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = { 1487 .halt_reg = 0x35bc, 1488 .clkr = { 1489 .enable_reg = 0x35bc, 1490 .enable_mask = BIT(0), 1491 .hw.init = &(struct clk_init_data){ 1492 .name = "camss_jpeg_jpeg_ocmemnoc_clk", 1493 .parent_names = (const char *[]){ 1494 "ocmemnoc_clk_src", 1495 }, 1496 .num_parents = 1, 1497 .flags = CLK_SET_RATE_PARENT, 1498 .ops = &clk_branch2_ops, 1499 }, 1500 }, 1501 }; 1502 1503 static struct clk_branch camss_mclk0_clk = { 1504 .halt_reg = 0x3384, 1505 .clkr = { 1506 .enable_reg = 0x3384, 1507 .enable_mask = BIT(0), 1508 .hw.init = &(struct clk_init_data){ 1509 .name = "camss_mclk0_clk", 1510 .parent_names = (const char *[]){ 1511 "mclk0_clk_src", 1512 }, 1513 .num_parents = 1, 1514 .flags = CLK_SET_RATE_PARENT, 1515 .ops = &clk_branch2_ops, 1516 }, 1517 }, 1518 }; 1519 1520 static struct clk_branch camss_mclk1_clk = { 1521 .halt_reg = 0x33b4, 1522 .clkr = { 1523 .enable_reg = 0x33b4, 1524 .enable_mask = BIT(0), 1525 .hw.init = &(struct clk_init_data){ 1526 .name = "camss_mclk1_clk", 1527 .parent_names = (const char *[]){ 1528 "mclk1_clk_src", 1529 }, 1530 .num_parents = 1, 1531 .flags = CLK_SET_RATE_PARENT, 1532 .ops = &clk_branch2_ops, 1533 }, 1534 }, 1535 }; 1536 1537 static struct clk_branch camss_mclk2_clk = { 1538 .halt_reg = 0x33e4, 1539 .clkr = { 1540 .enable_reg = 0x33e4, 1541 .enable_mask = BIT(0), 1542 .hw.init = &(struct clk_init_data){ 1543 .name = "camss_mclk2_clk", 1544 .parent_names = (const char *[]){ 1545 "mclk2_clk_src", 1546 }, 1547 .num_parents = 1, 1548 .flags = CLK_SET_RATE_PARENT, 1549 .ops = &clk_branch2_ops, 1550 }, 1551 }, 1552 }; 1553 1554 static struct clk_branch camss_mclk3_clk = { 1555 .halt_reg = 0x3414, 1556 .clkr = { 1557 .enable_reg = 0x3414, 1558 .enable_mask = BIT(0), 1559 .hw.init = &(struct clk_init_data){ 1560 .name = "camss_mclk3_clk", 1561 .parent_names = (const char *[]){ 1562 "mclk3_clk_src", 1563 }, 1564 .num_parents = 1, 1565 .flags = CLK_SET_RATE_PARENT, 1566 .ops = &clk_branch2_ops, 1567 }, 1568 }, 1569 }; 1570 1571 static struct clk_branch camss_micro_ahb_clk = { 1572 .halt_reg = 0x3494, 1573 .clkr = { 1574 .enable_reg = 0x3494, 1575 .enable_mask = BIT(0), 1576 .hw.init = &(struct clk_init_data){ 1577 .name = "camss_micro_ahb_clk", 1578 .parent_names = (const char *[]){ 1579 "mmss_ahb_clk_src", 1580 }, 1581 .num_parents = 1, 1582 .ops = &clk_branch2_ops, 1583 }, 1584 }, 1585 }; 1586 1587 static struct clk_branch camss_phy0_csi0phytimer_clk = { 1588 .halt_reg = 0x3024, 1589 .clkr = { 1590 .enable_reg = 0x3024, 1591 .enable_mask = BIT(0), 1592 .hw.init = &(struct clk_init_data){ 1593 .name = "camss_phy0_csi0phytimer_clk", 1594 .parent_names = (const char *[]){ 1595 "csi0phytimer_clk_src", 1596 }, 1597 .num_parents = 1, 1598 .flags = CLK_SET_RATE_PARENT, 1599 .ops = &clk_branch2_ops, 1600 }, 1601 }, 1602 }; 1603 1604 static struct clk_branch camss_phy1_csi1phytimer_clk = { 1605 .halt_reg = 0x3054, 1606 .clkr = { 1607 .enable_reg = 0x3054, 1608 .enable_mask = BIT(0), 1609 .hw.init = &(struct clk_init_data){ 1610 .name = "camss_phy1_csi1phytimer_clk", 1611 .parent_names = (const char *[]){ 1612 "csi1phytimer_clk_src", 1613 }, 1614 .num_parents = 1, 1615 .flags = CLK_SET_RATE_PARENT, 1616 .ops = &clk_branch2_ops, 1617 }, 1618 }, 1619 }; 1620 1621 static struct clk_branch camss_phy2_csi2phytimer_clk = { 1622 .halt_reg = 0x3084, 1623 .clkr = { 1624 .enable_reg = 0x3084, 1625 .enable_mask = BIT(0), 1626 .hw.init = &(struct clk_init_data){ 1627 .name = "camss_phy2_csi2phytimer_clk", 1628 .parent_names = (const char *[]){ 1629 "csi2phytimer_clk_src", 1630 }, 1631 .num_parents = 1, 1632 .flags = CLK_SET_RATE_PARENT, 1633 .ops = &clk_branch2_ops, 1634 }, 1635 }, 1636 }; 1637 1638 static struct clk_branch camss_top_ahb_clk = { 1639 .halt_reg = 0x3484, 1640 .clkr = { 1641 .enable_reg = 0x3484, 1642 .enable_mask = BIT(0), 1643 .hw.init = &(struct clk_init_data){ 1644 .name = "camss_top_ahb_clk", 1645 .parent_names = (const char *[]){ 1646 "mmss_ahb_clk_src", 1647 }, 1648 .num_parents = 1, 1649 .ops = &clk_branch2_ops, 1650 }, 1651 }, 1652 }; 1653 1654 static struct clk_branch camss_vfe_cpp_ahb_clk = { 1655 .halt_reg = 0x36b4, 1656 .clkr = { 1657 .enable_reg = 0x36b4, 1658 .enable_mask = BIT(0), 1659 .hw.init = &(struct clk_init_data){ 1660 .name = "camss_vfe_cpp_ahb_clk", 1661 .parent_names = (const char *[]){ 1662 "mmss_ahb_clk_src", 1663 }, 1664 .num_parents = 1, 1665 .ops = &clk_branch2_ops, 1666 }, 1667 }, 1668 }; 1669 1670 static struct clk_branch camss_vfe_cpp_clk = { 1671 .halt_reg = 0x36b0, 1672 .clkr = { 1673 .enable_reg = 0x36b0, 1674 .enable_mask = BIT(0), 1675 .hw.init = &(struct clk_init_data){ 1676 .name = "camss_vfe_cpp_clk", 1677 .parent_names = (const char *[]){ 1678 "cpp_clk_src", 1679 }, 1680 .num_parents = 1, 1681 .flags = CLK_SET_RATE_PARENT, 1682 .ops = &clk_branch2_ops, 1683 }, 1684 }, 1685 }; 1686 1687 static struct clk_branch camss_vfe_vfe0_clk = { 1688 .halt_reg = 0x36a8, 1689 .clkr = { 1690 .enable_reg = 0x36a8, 1691 .enable_mask = BIT(0), 1692 .hw.init = &(struct clk_init_data){ 1693 .name = "camss_vfe_vfe0_clk", 1694 .parent_names = (const char *[]){ 1695 "vfe0_clk_src", 1696 }, 1697 .num_parents = 1, 1698 .flags = CLK_SET_RATE_PARENT, 1699 .ops = &clk_branch2_ops, 1700 }, 1701 }, 1702 }; 1703 1704 static struct clk_branch camss_vfe_vfe1_clk = { 1705 .halt_reg = 0x36ac, 1706 .clkr = { 1707 .enable_reg = 0x36ac, 1708 .enable_mask = BIT(0), 1709 .hw.init = &(struct clk_init_data){ 1710 .name = "camss_vfe_vfe1_clk", 1711 .parent_names = (const char *[]){ 1712 "vfe1_clk_src", 1713 }, 1714 .num_parents = 1, 1715 .flags = CLK_SET_RATE_PARENT, 1716 .ops = &clk_branch2_ops, 1717 }, 1718 }, 1719 }; 1720 1721 static struct clk_branch camss_vfe_vfe_ahb_clk = { 1722 .halt_reg = 0x36b8, 1723 .clkr = { 1724 .enable_reg = 0x36b8, 1725 .enable_mask = BIT(0), 1726 .hw.init = &(struct clk_init_data){ 1727 .name = "camss_vfe_vfe_ahb_clk", 1728 .parent_names = (const char *[]){ 1729 "mmss_ahb_clk_src", 1730 }, 1731 .num_parents = 1, 1732 .ops = &clk_branch2_ops, 1733 }, 1734 }, 1735 }; 1736 1737 static struct clk_branch camss_vfe_vfe_axi_clk = { 1738 .halt_reg = 0x36bc, 1739 .clkr = { 1740 .enable_reg = 0x36bc, 1741 .enable_mask = BIT(0), 1742 .hw.init = &(struct clk_init_data){ 1743 .name = "camss_vfe_vfe_axi_clk", 1744 .parent_names = (const char *[]){ 1745 "mmss_axi_clk_src", 1746 }, 1747 .num_parents = 1, 1748 .ops = &clk_branch2_ops, 1749 }, 1750 }, 1751 }; 1752 1753 static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = { 1754 .halt_reg = 0x36c0, 1755 .clkr = { 1756 .enable_reg = 0x36c0, 1757 .enable_mask = BIT(0), 1758 .hw.init = &(struct clk_init_data){ 1759 .name = "camss_vfe_vfe_ocmemnoc_clk", 1760 .parent_names = (const char *[]){ 1761 "ocmemnoc_clk_src", 1762 }, 1763 .num_parents = 1, 1764 .flags = CLK_SET_RATE_PARENT, 1765 .ops = &clk_branch2_ops, 1766 }, 1767 }, 1768 }; 1769 1770 static struct clk_branch mdss_ahb_clk = { 1771 .halt_reg = 0x2308, 1772 .clkr = { 1773 .enable_reg = 0x2308, 1774 .enable_mask = BIT(0), 1775 .hw.init = &(struct clk_init_data){ 1776 .name = "mdss_ahb_clk", 1777 .parent_names = (const char *[]){ 1778 "mmss_ahb_clk_src", 1779 }, 1780 .num_parents = 1, 1781 .ops = &clk_branch2_ops, 1782 }, 1783 }, 1784 }; 1785 1786 static struct clk_branch mdss_axi_clk = { 1787 .halt_reg = 0x2310, 1788 .clkr = { 1789 .enable_reg = 0x2310, 1790 .enable_mask = BIT(0), 1791 .hw.init = &(struct clk_init_data){ 1792 .name = "mdss_axi_clk", 1793 .parent_names = (const char *[]){ 1794 "mmss_axi_clk_src", 1795 }, 1796 .num_parents = 1, 1797 .flags = CLK_SET_RATE_PARENT, 1798 .ops = &clk_branch2_ops, 1799 }, 1800 }, 1801 }; 1802 1803 static struct clk_branch mdss_byte0_clk = { 1804 .halt_reg = 0x233c, 1805 .clkr = { 1806 .enable_reg = 0x233c, 1807 .enable_mask = BIT(0), 1808 .hw.init = &(struct clk_init_data){ 1809 .name = "mdss_byte0_clk", 1810 .parent_names = (const char *[]){ 1811 "byte0_clk_src", 1812 }, 1813 .num_parents = 1, 1814 .flags = CLK_SET_RATE_PARENT, 1815 .ops = &clk_branch2_ops, 1816 }, 1817 }, 1818 }; 1819 1820 static struct clk_branch mdss_byte1_clk = { 1821 .halt_reg = 0x2340, 1822 .clkr = { 1823 .enable_reg = 0x2340, 1824 .enable_mask = BIT(0), 1825 .hw.init = &(struct clk_init_data){ 1826 .name = "mdss_byte1_clk", 1827 .parent_names = (const char *[]){ 1828 "byte1_clk_src", 1829 }, 1830 .num_parents = 1, 1831 .flags = CLK_SET_RATE_PARENT, 1832 .ops = &clk_branch2_ops, 1833 }, 1834 }, 1835 }; 1836 1837 static struct clk_branch mdss_edpaux_clk = { 1838 .halt_reg = 0x2334, 1839 .clkr = { 1840 .enable_reg = 0x2334, 1841 .enable_mask = BIT(0), 1842 .hw.init = &(struct clk_init_data){ 1843 .name = "mdss_edpaux_clk", 1844 .parent_names = (const char *[]){ 1845 "edpaux_clk_src", 1846 }, 1847 .num_parents = 1, 1848 .flags = CLK_SET_RATE_PARENT, 1849 .ops = &clk_branch2_ops, 1850 }, 1851 }, 1852 }; 1853 1854 static struct clk_branch mdss_edplink_clk = { 1855 .halt_reg = 0x2330, 1856 .clkr = { 1857 .enable_reg = 0x2330, 1858 .enable_mask = BIT(0), 1859 .hw.init = &(struct clk_init_data){ 1860 .name = "mdss_edplink_clk", 1861 .parent_names = (const char *[]){ 1862 "edplink_clk_src", 1863 }, 1864 .num_parents = 1, 1865 .flags = CLK_SET_RATE_PARENT, 1866 .ops = &clk_branch2_ops, 1867 }, 1868 }, 1869 }; 1870 1871 static struct clk_branch mdss_edppixel_clk = { 1872 .halt_reg = 0x232c, 1873 .clkr = { 1874 .enable_reg = 0x232c, 1875 .enable_mask = BIT(0), 1876 .hw.init = &(struct clk_init_data){ 1877 .name = "mdss_edppixel_clk", 1878 .parent_names = (const char *[]){ 1879 "edppixel_clk_src", 1880 }, 1881 .num_parents = 1, 1882 .flags = CLK_SET_RATE_PARENT, 1883 .ops = &clk_branch2_ops, 1884 }, 1885 }, 1886 }; 1887 1888 static struct clk_branch mdss_esc0_clk = { 1889 .halt_reg = 0x2344, 1890 .clkr = { 1891 .enable_reg = 0x2344, 1892 .enable_mask = BIT(0), 1893 .hw.init = &(struct clk_init_data){ 1894 .name = "mdss_esc0_clk", 1895 .parent_names = (const char *[]){ 1896 "esc0_clk_src", 1897 }, 1898 .num_parents = 1, 1899 .flags = CLK_SET_RATE_PARENT, 1900 .ops = &clk_branch2_ops, 1901 }, 1902 }, 1903 }; 1904 1905 static struct clk_branch mdss_esc1_clk = { 1906 .halt_reg = 0x2348, 1907 .clkr = { 1908 .enable_reg = 0x2348, 1909 .enable_mask = BIT(0), 1910 .hw.init = &(struct clk_init_data){ 1911 .name = "mdss_esc1_clk", 1912 .parent_names = (const char *[]){ 1913 "esc1_clk_src", 1914 }, 1915 .num_parents = 1, 1916 .flags = CLK_SET_RATE_PARENT, 1917 .ops = &clk_branch2_ops, 1918 }, 1919 }, 1920 }; 1921 1922 static struct clk_branch mdss_extpclk_clk = { 1923 .halt_reg = 0x2324, 1924 .clkr = { 1925 .enable_reg = 0x2324, 1926 .enable_mask = BIT(0), 1927 .hw.init = &(struct clk_init_data){ 1928 .name = "mdss_extpclk_clk", 1929 .parent_names = (const char *[]){ 1930 "extpclk_clk_src", 1931 }, 1932 .num_parents = 1, 1933 .flags = CLK_SET_RATE_PARENT, 1934 .ops = &clk_branch2_ops, 1935 }, 1936 }, 1937 }; 1938 1939 static struct clk_branch mdss_hdmi_ahb_clk = { 1940 .halt_reg = 0x230c, 1941 .clkr = { 1942 .enable_reg = 0x230c, 1943 .enable_mask = BIT(0), 1944 .hw.init = &(struct clk_init_data){ 1945 .name = "mdss_hdmi_ahb_clk", 1946 .parent_names = (const char *[]){ 1947 "mmss_ahb_clk_src", 1948 }, 1949 .num_parents = 1, 1950 .ops = &clk_branch2_ops, 1951 }, 1952 }, 1953 }; 1954 1955 static struct clk_branch mdss_hdmi_clk = { 1956 .halt_reg = 0x2338, 1957 .clkr = { 1958 .enable_reg = 0x2338, 1959 .enable_mask = BIT(0), 1960 .hw.init = &(struct clk_init_data){ 1961 .name = "mdss_hdmi_clk", 1962 .parent_names = (const char *[]){ 1963 "hdmi_clk_src", 1964 }, 1965 .num_parents = 1, 1966 .flags = CLK_SET_RATE_PARENT, 1967 .ops = &clk_branch2_ops, 1968 }, 1969 }, 1970 }; 1971 1972 static struct clk_branch mdss_mdp_clk = { 1973 .halt_reg = 0x231c, 1974 .clkr = { 1975 .enable_reg = 0x231c, 1976 .enable_mask = BIT(0), 1977 .hw.init = &(struct clk_init_data){ 1978 .name = "mdss_mdp_clk", 1979 .parent_names = (const char *[]){ 1980 "mdp_clk_src", 1981 }, 1982 .num_parents = 1, 1983 .flags = CLK_SET_RATE_PARENT, 1984 .ops = &clk_branch2_ops, 1985 }, 1986 }, 1987 }; 1988 1989 static struct clk_branch mdss_mdp_lut_clk = { 1990 .halt_reg = 0x2320, 1991 .clkr = { 1992 .enable_reg = 0x2320, 1993 .enable_mask = BIT(0), 1994 .hw.init = &(struct clk_init_data){ 1995 .name = "mdss_mdp_lut_clk", 1996 .parent_names = (const char *[]){ 1997 "mdp_clk_src", 1998 }, 1999 .num_parents = 1, 2000 .flags = CLK_SET_RATE_PARENT, 2001 .ops = &clk_branch2_ops, 2002 }, 2003 }, 2004 }; 2005 2006 static struct clk_branch mdss_pclk0_clk = { 2007 .halt_reg = 0x2314, 2008 .clkr = { 2009 .enable_reg = 0x2314, 2010 .enable_mask = BIT(0), 2011 .hw.init = &(struct clk_init_data){ 2012 .name = "mdss_pclk0_clk", 2013 .parent_names = (const char *[]){ 2014 "pclk0_clk_src", 2015 }, 2016 .num_parents = 1, 2017 .flags = CLK_SET_RATE_PARENT, 2018 .ops = &clk_branch2_ops, 2019 }, 2020 }, 2021 }; 2022 2023 static struct clk_branch mdss_pclk1_clk = { 2024 .halt_reg = 0x2318, 2025 .clkr = { 2026 .enable_reg = 0x2318, 2027 .enable_mask = BIT(0), 2028 .hw.init = &(struct clk_init_data){ 2029 .name = "mdss_pclk1_clk", 2030 .parent_names = (const char *[]){ 2031 "pclk1_clk_src", 2032 }, 2033 .num_parents = 1, 2034 .flags = CLK_SET_RATE_PARENT, 2035 .ops = &clk_branch2_ops, 2036 }, 2037 }, 2038 }; 2039 2040 static struct clk_branch mdss_vsync_clk = { 2041 .halt_reg = 0x2328, 2042 .clkr = { 2043 .enable_reg = 0x2328, 2044 .enable_mask = BIT(0), 2045 .hw.init = &(struct clk_init_data){ 2046 .name = "mdss_vsync_clk", 2047 .parent_names = (const char *[]){ 2048 "vsync_clk_src", 2049 }, 2050 .num_parents = 1, 2051 .flags = CLK_SET_RATE_PARENT, 2052 .ops = &clk_branch2_ops, 2053 }, 2054 }, 2055 }; 2056 2057 static struct clk_branch mmss_misc_ahb_clk = { 2058 .halt_reg = 0x502c, 2059 .clkr = { 2060 .enable_reg = 0x502c, 2061 .enable_mask = BIT(0), 2062 .hw.init = &(struct clk_init_data){ 2063 .name = "mmss_misc_ahb_clk", 2064 .parent_names = (const char *[]){ 2065 "mmss_ahb_clk_src", 2066 }, 2067 .num_parents = 1, 2068 .ops = &clk_branch2_ops, 2069 }, 2070 }, 2071 }; 2072 2073 static struct clk_branch mmss_mmssnoc_ahb_clk = { 2074 .halt_reg = 0x5024, 2075 .clkr = { 2076 .enable_reg = 0x5024, 2077 .enable_mask = BIT(0), 2078 .hw.init = &(struct clk_init_data){ 2079 .name = "mmss_mmssnoc_ahb_clk", 2080 .parent_names = (const char *[]){ 2081 "mmss_ahb_clk_src", 2082 }, 2083 .num_parents = 1, 2084 .ops = &clk_branch2_ops, 2085 .flags = CLK_IGNORE_UNUSED, 2086 }, 2087 }, 2088 }; 2089 2090 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = { 2091 .halt_reg = 0x5028, 2092 .clkr = { 2093 .enable_reg = 0x5028, 2094 .enable_mask = BIT(0), 2095 .hw.init = &(struct clk_init_data){ 2096 .name = "mmss_mmssnoc_bto_ahb_clk", 2097 .parent_names = (const char *[]){ 2098 "mmss_ahb_clk_src", 2099 }, 2100 .num_parents = 1, 2101 .ops = &clk_branch2_ops, 2102 .flags = CLK_IGNORE_UNUSED, 2103 }, 2104 }, 2105 }; 2106 2107 static struct clk_branch mmss_mmssnoc_axi_clk = { 2108 .halt_reg = 0x506c, 2109 .clkr = { 2110 .enable_reg = 0x506c, 2111 .enable_mask = BIT(0), 2112 .hw.init = &(struct clk_init_data){ 2113 .name = "mmss_mmssnoc_axi_clk", 2114 .parent_names = (const char *[]){ 2115 "mmss_axi_clk_src", 2116 }, 2117 .num_parents = 1, 2118 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2119 .ops = &clk_branch2_ops, 2120 }, 2121 }, 2122 }; 2123 2124 static struct clk_branch mmss_s0_axi_clk = { 2125 .halt_reg = 0x5064, 2126 .clkr = { 2127 .enable_reg = 0x5064, 2128 .enable_mask = BIT(0), 2129 .hw.init = &(struct clk_init_data){ 2130 .name = "mmss_s0_axi_clk", 2131 .parent_names = (const char *[]){ 2132 "mmss_axi_clk_src", 2133 }, 2134 .num_parents = 1, 2135 .ops = &clk_branch2_ops, 2136 .flags = CLK_IGNORE_UNUSED, 2137 }, 2138 }, 2139 }; 2140 2141 static struct clk_branch ocmemcx_ahb_clk = { 2142 .halt_reg = 0x405c, 2143 .clkr = { 2144 .enable_reg = 0x405c, 2145 .enable_mask = BIT(0), 2146 .hw.init = &(struct clk_init_data){ 2147 .name = "ocmemcx_ahb_clk", 2148 .parent_names = (const char *[]){ 2149 "mmss_ahb_clk_src", 2150 }, 2151 .num_parents = 1, 2152 .ops = &clk_branch2_ops, 2153 }, 2154 }, 2155 }; 2156 2157 static struct clk_branch ocmemcx_ocmemnoc_clk = { 2158 .halt_reg = 0x4058, 2159 .clkr = { 2160 .enable_reg = 0x4058, 2161 .enable_mask = BIT(0), 2162 .hw.init = &(struct clk_init_data){ 2163 .name = "ocmemcx_ocmemnoc_clk", 2164 .parent_names = (const char *[]){ 2165 "ocmemnoc_clk_src", 2166 }, 2167 .num_parents = 1, 2168 .flags = CLK_SET_RATE_PARENT, 2169 .ops = &clk_branch2_ops, 2170 }, 2171 }, 2172 }; 2173 2174 static struct clk_branch oxili_ocmemgx_clk = { 2175 .halt_reg = 0x402c, 2176 .clkr = { 2177 .enable_reg = 0x402c, 2178 .enable_mask = BIT(0), 2179 .hw.init = &(struct clk_init_data){ 2180 .name = "oxili_ocmemgx_clk", 2181 .parent_names = (const char *[]){ 2182 "gfx3d_clk_src", 2183 }, 2184 .num_parents = 1, 2185 .flags = CLK_SET_RATE_PARENT, 2186 .ops = &clk_branch2_ops, 2187 }, 2188 }, 2189 }; 2190 2191 static struct clk_branch ocmemnoc_clk = { 2192 .halt_reg = 0x50b4, 2193 .clkr = { 2194 .enable_reg = 0x50b4, 2195 .enable_mask = BIT(0), 2196 .hw.init = &(struct clk_init_data){ 2197 .name = "ocmemnoc_clk", 2198 .parent_names = (const char *[]){ 2199 "ocmemnoc_clk_src", 2200 }, 2201 .num_parents = 1, 2202 .flags = CLK_SET_RATE_PARENT, 2203 .ops = &clk_branch2_ops, 2204 }, 2205 }, 2206 }; 2207 2208 static struct clk_branch oxili_gfx3d_clk = { 2209 .halt_reg = 0x4028, 2210 .clkr = { 2211 .enable_reg = 0x4028, 2212 .enable_mask = BIT(0), 2213 .hw.init = &(struct clk_init_data){ 2214 .name = "oxili_gfx3d_clk", 2215 .parent_names = (const char *[]){ 2216 "gfx3d_clk_src", 2217 }, 2218 .num_parents = 1, 2219 .flags = CLK_SET_RATE_PARENT, 2220 .ops = &clk_branch2_ops, 2221 }, 2222 }, 2223 }; 2224 2225 static struct clk_branch oxilicx_ahb_clk = { 2226 .halt_reg = 0x403c, 2227 .clkr = { 2228 .enable_reg = 0x403c, 2229 .enable_mask = BIT(0), 2230 .hw.init = &(struct clk_init_data){ 2231 .name = "oxilicx_ahb_clk", 2232 .parent_names = (const char *[]){ 2233 "mmss_ahb_clk_src", 2234 }, 2235 .num_parents = 1, 2236 .ops = &clk_branch2_ops, 2237 }, 2238 }, 2239 }; 2240 2241 static struct clk_branch oxilicx_axi_clk = { 2242 .halt_reg = 0x4038, 2243 .clkr = { 2244 .enable_reg = 0x4038, 2245 .enable_mask = BIT(0), 2246 .hw.init = &(struct clk_init_data){ 2247 .name = "oxilicx_axi_clk", 2248 .parent_names = (const char *[]){ 2249 "mmss_axi_clk_src", 2250 }, 2251 .num_parents = 1, 2252 .ops = &clk_branch2_ops, 2253 }, 2254 }, 2255 }; 2256 2257 static struct clk_branch venus0_ahb_clk = { 2258 .halt_reg = 0x1030, 2259 .clkr = { 2260 .enable_reg = 0x1030, 2261 .enable_mask = BIT(0), 2262 .hw.init = &(struct clk_init_data){ 2263 .name = "venus0_ahb_clk", 2264 .parent_names = (const char *[]){ 2265 "mmss_ahb_clk_src", 2266 }, 2267 .num_parents = 1, 2268 .ops = &clk_branch2_ops, 2269 }, 2270 }, 2271 }; 2272 2273 static struct clk_branch venus0_axi_clk = { 2274 .halt_reg = 0x1034, 2275 .clkr = { 2276 .enable_reg = 0x1034, 2277 .enable_mask = BIT(0), 2278 .hw.init = &(struct clk_init_data){ 2279 .name = "venus0_axi_clk", 2280 .parent_names = (const char *[]){ 2281 "mmss_axi_clk_src", 2282 }, 2283 .num_parents = 1, 2284 .ops = &clk_branch2_ops, 2285 }, 2286 }, 2287 }; 2288 2289 static struct clk_branch venus0_ocmemnoc_clk = { 2290 .halt_reg = 0x1038, 2291 .clkr = { 2292 .enable_reg = 0x1038, 2293 .enable_mask = BIT(0), 2294 .hw.init = &(struct clk_init_data){ 2295 .name = "venus0_ocmemnoc_clk", 2296 .parent_names = (const char *[]){ 2297 "ocmemnoc_clk_src", 2298 }, 2299 .num_parents = 1, 2300 .flags = CLK_SET_RATE_PARENT, 2301 .ops = &clk_branch2_ops, 2302 }, 2303 }, 2304 }; 2305 2306 static struct clk_branch venus0_vcodec0_clk = { 2307 .halt_reg = 0x1028, 2308 .clkr = { 2309 .enable_reg = 0x1028, 2310 .enable_mask = BIT(0), 2311 .hw.init = &(struct clk_init_data){ 2312 .name = "venus0_vcodec0_clk", 2313 .parent_names = (const char *[]){ 2314 "vcodec0_clk_src", 2315 }, 2316 .num_parents = 1, 2317 .flags = CLK_SET_RATE_PARENT, 2318 .ops = &clk_branch2_ops, 2319 }, 2320 }, 2321 }; 2322 2323 static const struct pll_config mmpll1_config = { 2324 .l = 60, 2325 .m = 25, 2326 .n = 32, 2327 .vco_val = 0x0, 2328 .vco_mask = 0x3 << 20, 2329 .pre_div_val = 0x0, 2330 .pre_div_mask = 0x7 << 12, 2331 .post_div_val = 0x0, 2332 .post_div_mask = 0x3 << 8, 2333 .mn_ena_mask = BIT(24), 2334 .main_output_mask = BIT(0), 2335 }; 2336 2337 static struct pll_config mmpll3_config = { 2338 .l = 48, 2339 .m = 7, 2340 .n = 16, 2341 .vco_val = 0x0, 2342 .vco_mask = 0x3 << 20, 2343 .pre_div_val = 0x0, 2344 .pre_div_mask = 0x7 << 12, 2345 .post_div_val = 0x0, 2346 .post_div_mask = 0x3 << 8, 2347 .mn_ena_mask = BIT(24), 2348 .main_output_mask = BIT(0), 2349 .aux_output_mask = BIT(1), 2350 }; 2351 2352 static struct clk_regmap *mmcc_msm8974_clocks[] = { 2353 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, 2354 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, 2355 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr, 2356 [MMPLL0] = &mmpll0.clkr, 2357 [MMPLL0_VOTE] = &mmpll0_vote, 2358 [MMPLL1] = &mmpll1.clkr, 2359 [MMPLL1_VOTE] = &mmpll1_vote, 2360 [MMPLL2] = &mmpll2.clkr, 2361 [MMPLL3] = &mmpll3.clkr, 2362 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 2363 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 2364 [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 2365 [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 2366 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 2367 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 2368 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 2369 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 2370 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 2371 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr, 2372 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, 2373 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 2374 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 2375 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, 2376 [CCI_CLK_SRC] = &cci_clk_src.clkr, 2377 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 2378 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 2379 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 2380 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 2381 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 2382 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 2383 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 2384 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 2385 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 2386 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 2387 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 2388 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 2389 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr, 2390 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr, 2391 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr, 2392 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 2393 [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 2394 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 2395 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 2396 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 2397 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr, 2398 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr, 2399 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 2400 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 2401 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, 2402 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 2403 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 2404 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 2405 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 2406 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, 2407 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 2408 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 2409 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 2410 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 2411 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, 2412 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 2413 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 2414 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 2415 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 2416 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, 2417 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 2418 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 2419 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 2420 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 2421 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 2422 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 2423 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 2424 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr, 2425 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr, 2426 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr, 2427 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr, 2428 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr, 2429 [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr, 2430 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 2431 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 2432 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 2433 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 2434 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 2435 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr, 2436 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr, 2437 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr, 2438 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 2439 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr, 2440 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr, 2441 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr, 2442 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr, 2443 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr, 2444 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr, 2445 [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr, 2446 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 2447 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 2448 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 2449 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 2450 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr, 2451 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr, 2452 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr, 2453 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 2454 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 2455 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 2456 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, 2457 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 2458 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 2459 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr, 2460 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 2461 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 2462 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 2463 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, 2464 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr, 2465 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr, 2466 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr, 2467 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr, 2468 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr, 2469 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr, 2470 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr, 2471 [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr, 2472 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr, 2473 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr, 2474 [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr, 2475 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr, 2476 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr, 2477 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr, 2478 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr, 2479 }; 2480 2481 static const struct qcom_reset_map mmcc_msm8974_resets[] = { 2482 [SPDM_RESET] = { 0x0200 }, 2483 [SPDM_RM_RESET] = { 0x0300 }, 2484 [VENUS0_RESET] = { 0x1020 }, 2485 [MDSS_RESET] = { 0x2300 }, 2486 [CAMSS_PHY0_RESET] = { 0x3020 }, 2487 [CAMSS_PHY1_RESET] = { 0x3050 }, 2488 [CAMSS_PHY2_RESET] = { 0x3080 }, 2489 [CAMSS_CSI0_RESET] = { 0x30b0 }, 2490 [CAMSS_CSI0PHY_RESET] = { 0x30c0 }, 2491 [CAMSS_CSI0RDI_RESET] = { 0x30d0 }, 2492 [CAMSS_CSI0PIX_RESET] = { 0x30e0 }, 2493 [CAMSS_CSI1_RESET] = { 0x3120 }, 2494 [CAMSS_CSI1PHY_RESET] = { 0x3130 }, 2495 [CAMSS_CSI1RDI_RESET] = { 0x3140 }, 2496 [CAMSS_CSI1PIX_RESET] = { 0x3150 }, 2497 [CAMSS_CSI2_RESET] = { 0x3180 }, 2498 [CAMSS_CSI2PHY_RESET] = { 0x3190 }, 2499 [CAMSS_CSI2RDI_RESET] = { 0x31a0 }, 2500 [CAMSS_CSI2PIX_RESET] = { 0x31b0 }, 2501 [CAMSS_CSI3_RESET] = { 0x31e0 }, 2502 [CAMSS_CSI3PHY_RESET] = { 0x31f0 }, 2503 [CAMSS_CSI3RDI_RESET] = { 0x3200 }, 2504 [CAMSS_CSI3PIX_RESET] = { 0x3210 }, 2505 [CAMSS_ISPIF_RESET] = { 0x3220 }, 2506 [CAMSS_CCI_RESET] = { 0x3340 }, 2507 [CAMSS_MCLK0_RESET] = { 0x3380 }, 2508 [CAMSS_MCLK1_RESET] = { 0x33b0 }, 2509 [CAMSS_MCLK2_RESET] = { 0x33e0 }, 2510 [CAMSS_MCLK3_RESET] = { 0x3410 }, 2511 [CAMSS_GP0_RESET] = { 0x3440 }, 2512 [CAMSS_GP1_RESET] = { 0x3470 }, 2513 [CAMSS_TOP_RESET] = { 0x3480 }, 2514 [CAMSS_MICRO_RESET] = { 0x3490 }, 2515 [CAMSS_JPEG_RESET] = { 0x35a0 }, 2516 [CAMSS_VFE_RESET] = { 0x36a0 }, 2517 [CAMSS_CSI_VFE0_RESET] = { 0x3700 }, 2518 [CAMSS_CSI_VFE1_RESET] = { 0x3710 }, 2519 [OXILI_RESET] = { 0x4020 }, 2520 [OXILICX_RESET] = { 0x4030 }, 2521 [OCMEMCX_RESET] = { 0x4050 }, 2522 [MMSS_RBCRP_RESET] = { 0x4080 }, 2523 [MMSSNOCAHB_RESET] = { 0x5020 }, 2524 [MMSSNOCAXI_RESET] = { 0x5060 }, 2525 [OCMEMNOC_RESET] = { 0x50b0 }, 2526 }; 2527 2528 static const struct regmap_config mmcc_msm8974_regmap_config = { 2529 .reg_bits = 32, 2530 .reg_stride = 4, 2531 .val_bits = 32, 2532 .max_register = 0x5104, 2533 .fast_io = true, 2534 }; 2535 2536 static const struct qcom_cc_desc mmcc_msm8974_desc = { 2537 .config = &mmcc_msm8974_regmap_config, 2538 .clks = mmcc_msm8974_clocks, 2539 .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks), 2540 .resets = mmcc_msm8974_resets, 2541 .num_resets = ARRAY_SIZE(mmcc_msm8974_resets), 2542 }; 2543 2544 static const struct of_device_id mmcc_msm8974_match_table[] = { 2545 { .compatible = "qcom,mmcc-msm8974" }, 2546 { } 2547 }; 2548 MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table); 2549 2550 static int mmcc_msm8974_probe(struct platform_device *pdev) 2551 { 2552 struct regmap *regmap; 2553 2554 regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc); 2555 if (IS_ERR(regmap)) 2556 return PTR_ERR(regmap); 2557 2558 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); 2559 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); 2560 2561 return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap); 2562 } 2563 2564 static int mmcc_msm8974_remove(struct platform_device *pdev) 2565 { 2566 qcom_cc_remove(pdev); 2567 return 0; 2568 } 2569 2570 static struct platform_driver mmcc_msm8974_driver = { 2571 .probe = mmcc_msm8974_probe, 2572 .remove = mmcc_msm8974_remove, 2573 .driver = { 2574 .name = "mmcc-msm8974", 2575 .of_match_table = mmcc_msm8974_match_table, 2576 }, 2577 }; 2578 module_platform_driver(mmcc_msm8974_driver); 2579 2580 MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver"); 2581 MODULE_LICENSE("GPL v2"); 2582 MODULE_ALIAS("platform:mmcc-msm8974"); 2583