1 /* 2 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/delay.h> 18 #include <linux/platform_device.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/clk-provider.h> 23 #include <linux/regmap.h> 24 #include <linux/reset-controller.h> 25 26 #include <dt-bindings/clock/qcom,mmcc-msm8960.h> 27 #include <dt-bindings/reset/qcom,mmcc-msm8960.h> 28 29 #include "common.h" 30 #include "clk-regmap.h" 31 #include "clk-pll.h" 32 #include "clk-rcg.h" 33 #include "clk-branch.h" 34 #include "reset.h" 35 36 enum { 37 P_PXO, 38 P_PLL8, 39 P_PLL2, 40 P_PLL3, 41 P_PLL15, 42 P_HDMI_PLL, 43 }; 44 45 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } 46 47 static const struct parent_map mmcc_pxo_pll8_pll2_map[] = { 48 { P_PXO, 0 }, 49 { P_PLL8, 2 }, 50 { P_PLL2, 1 } 51 }; 52 53 static const char *mmcc_pxo_pll8_pll2[] = { 54 "pxo", 55 "pll8_vote", 56 "pll2", 57 }; 58 59 static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = { 60 { P_PXO, 0 }, 61 { P_PLL8, 2 }, 62 { P_PLL2, 1 }, 63 { P_PLL3, 3 } 64 }; 65 66 static const char *mmcc_pxo_pll8_pll2_pll15[] = { 67 "pxo", 68 "pll8_vote", 69 "pll2", 70 "pll15", 71 }; 72 73 static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = { 74 { P_PXO, 0 }, 75 { P_PLL8, 2 }, 76 { P_PLL2, 1 }, 77 { P_PLL15, 3 } 78 }; 79 80 static const char *mmcc_pxo_pll8_pll2_pll3[] = { 81 "pxo", 82 "pll8_vote", 83 "pll2", 84 "pll3", 85 }; 86 87 static struct clk_pll pll2 = { 88 .l_reg = 0x320, 89 .m_reg = 0x324, 90 .n_reg = 0x328, 91 .config_reg = 0x32c, 92 .mode_reg = 0x31c, 93 .status_reg = 0x334, 94 .status_bit = 16, 95 .clkr.hw.init = &(struct clk_init_data){ 96 .name = "pll2", 97 .parent_names = (const char *[]){ "pxo" }, 98 .num_parents = 1, 99 .ops = &clk_pll_ops, 100 }, 101 }; 102 103 static struct clk_pll pll15 = { 104 .l_reg = 0x33c, 105 .m_reg = 0x340, 106 .n_reg = 0x344, 107 .config_reg = 0x348, 108 .mode_reg = 0x338, 109 .status_reg = 0x350, 110 .status_bit = 16, 111 .clkr.hw.init = &(struct clk_init_data){ 112 .name = "pll15", 113 .parent_names = (const char *[]){ "pxo" }, 114 .num_parents = 1, 115 .ops = &clk_pll_ops, 116 }, 117 }; 118 119 static const struct pll_config pll15_config = { 120 .l = 33, 121 .m = 1, 122 .n = 3, 123 .vco_val = 0x2 << 16, 124 .vco_mask = 0x3 << 16, 125 .pre_div_val = 0x0, 126 .pre_div_mask = BIT(19), 127 .post_div_val = 0x0, 128 .post_div_mask = 0x3 << 20, 129 .mn_ena_mask = BIT(22), 130 .main_output_mask = BIT(23), 131 }; 132 133 static struct freq_tbl clk_tbl_cam[] = { 134 { 6000000, P_PLL8, 4, 1, 16 }, 135 { 8000000, P_PLL8, 4, 1, 12 }, 136 { 12000000, P_PLL8, 4, 1, 8 }, 137 { 16000000, P_PLL8, 4, 1, 6 }, 138 { 19200000, P_PLL8, 4, 1, 5 }, 139 { 24000000, P_PLL8, 4, 1, 4 }, 140 { 32000000, P_PLL8, 4, 1, 3 }, 141 { 48000000, P_PLL8, 4, 1, 2 }, 142 { 64000000, P_PLL8, 3, 1, 2 }, 143 { 96000000, P_PLL8, 4, 0, 0 }, 144 { 128000000, P_PLL8, 3, 0, 0 }, 145 { } 146 }; 147 148 static struct clk_rcg camclk0_src = { 149 .ns_reg = 0x0148, 150 .md_reg = 0x0144, 151 .mn = { 152 .mnctr_en_bit = 5, 153 .mnctr_reset_bit = 8, 154 .reset_in_cc = true, 155 .mnctr_mode_shift = 6, 156 .n_val_shift = 24, 157 .m_val_shift = 8, 158 .width = 8, 159 }, 160 .p = { 161 .pre_div_shift = 14, 162 .pre_div_width = 2, 163 }, 164 .s = { 165 .src_sel_shift = 0, 166 .parent_map = mmcc_pxo_pll8_pll2_map, 167 }, 168 .freq_tbl = clk_tbl_cam, 169 .clkr = { 170 .enable_reg = 0x0140, 171 .enable_mask = BIT(2), 172 .hw.init = &(struct clk_init_data){ 173 .name = "camclk0_src", 174 .parent_names = mmcc_pxo_pll8_pll2, 175 .num_parents = 3, 176 .ops = &clk_rcg_ops, 177 }, 178 }, 179 }; 180 181 static struct clk_branch camclk0_clk = { 182 .halt_reg = 0x01e8, 183 .halt_bit = 15, 184 .clkr = { 185 .enable_reg = 0x0140, 186 .enable_mask = BIT(0), 187 .hw.init = &(struct clk_init_data){ 188 .name = "camclk0_clk", 189 .parent_names = (const char *[]){ "camclk0_src" }, 190 .num_parents = 1, 191 .ops = &clk_branch_ops, 192 }, 193 }, 194 195 }; 196 197 static struct clk_rcg camclk1_src = { 198 .ns_reg = 0x015c, 199 .md_reg = 0x0158, 200 .mn = { 201 .mnctr_en_bit = 5, 202 .mnctr_reset_bit = 8, 203 .reset_in_cc = true, 204 .mnctr_mode_shift = 6, 205 .n_val_shift = 24, 206 .m_val_shift = 8, 207 .width = 8, 208 }, 209 .p = { 210 .pre_div_shift = 14, 211 .pre_div_width = 2, 212 }, 213 .s = { 214 .src_sel_shift = 0, 215 .parent_map = mmcc_pxo_pll8_pll2_map, 216 }, 217 .freq_tbl = clk_tbl_cam, 218 .clkr = { 219 .enable_reg = 0x0154, 220 .enable_mask = BIT(2), 221 .hw.init = &(struct clk_init_data){ 222 .name = "camclk1_src", 223 .parent_names = mmcc_pxo_pll8_pll2, 224 .num_parents = 3, 225 .ops = &clk_rcg_ops, 226 }, 227 }, 228 }; 229 230 static struct clk_branch camclk1_clk = { 231 .halt_reg = 0x01e8, 232 .halt_bit = 16, 233 .clkr = { 234 .enable_reg = 0x0154, 235 .enable_mask = BIT(0), 236 .hw.init = &(struct clk_init_data){ 237 .name = "camclk1_clk", 238 .parent_names = (const char *[]){ "camclk1_src" }, 239 .num_parents = 1, 240 .ops = &clk_branch_ops, 241 }, 242 }, 243 244 }; 245 246 static struct clk_rcg camclk2_src = { 247 .ns_reg = 0x0228, 248 .md_reg = 0x0224, 249 .mn = { 250 .mnctr_en_bit = 5, 251 .mnctr_reset_bit = 8, 252 .reset_in_cc = true, 253 .mnctr_mode_shift = 6, 254 .n_val_shift = 24, 255 .m_val_shift = 8, 256 .width = 8, 257 }, 258 .p = { 259 .pre_div_shift = 14, 260 .pre_div_width = 2, 261 }, 262 .s = { 263 .src_sel_shift = 0, 264 .parent_map = mmcc_pxo_pll8_pll2_map, 265 }, 266 .freq_tbl = clk_tbl_cam, 267 .clkr = { 268 .enable_reg = 0x0220, 269 .enable_mask = BIT(2), 270 .hw.init = &(struct clk_init_data){ 271 .name = "camclk2_src", 272 .parent_names = mmcc_pxo_pll8_pll2, 273 .num_parents = 3, 274 .ops = &clk_rcg_ops, 275 }, 276 }, 277 }; 278 279 static struct clk_branch camclk2_clk = { 280 .halt_reg = 0x01e8, 281 .halt_bit = 16, 282 .clkr = { 283 .enable_reg = 0x0220, 284 .enable_mask = BIT(0), 285 .hw.init = &(struct clk_init_data){ 286 .name = "camclk2_clk", 287 .parent_names = (const char *[]){ "camclk2_src" }, 288 .num_parents = 1, 289 .ops = &clk_branch_ops, 290 }, 291 }, 292 293 }; 294 295 static struct freq_tbl clk_tbl_csi[] = { 296 { 27000000, P_PXO, 1, 0, 0 }, 297 { 85330000, P_PLL8, 1, 2, 9 }, 298 { 177780000, P_PLL2, 1, 2, 9 }, 299 { } 300 }; 301 302 static struct clk_rcg csi0_src = { 303 .ns_reg = 0x0048, 304 .md_reg = 0x0044, 305 .mn = { 306 .mnctr_en_bit = 5, 307 .mnctr_reset_bit = 7, 308 .mnctr_mode_shift = 6, 309 .n_val_shift = 24, 310 .m_val_shift = 8, 311 .width = 8, 312 }, 313 .p = { 314 .pre_div_shift = 14, 315 .pre_div_width = 2, 316 }, 317 .s = { 318 .src_sel_shift = 0, 319 .parent_map = mmcc_pxo_pll8_pll2_map, 320 }, 321 .freq_tbl = clk_tbl_csi, 322 .clkr = { 323 .enable_reg = 0x0040, 324 .enable_mask = BIT(2), 325 .hw.init = &(struct clk_init_data){ 326 .name = "csi0_src", 327 .parent_names = mmcc_pxo_pll8_pll2, 328 .num_parents = 3, 329 .ops = &clk_rcg_ops, 330 }, 331 }, 332 }; 333 334 static struct clk_branch csi0_clk = { 335 .halt_reg = 0x01cc, 336 .halt_bit = 13, 337 .clkr = { 338 .enable_reg = 0x0040, 339 .enable_mask = BIT(0), 340 .hw.init = &(struct clk_init_data){ 341 .parent_names = (const char *[]){ "csi0_src" }, 342 .num_parents = 1, 343 .name = "csi0_clk", 344 .ops = &clk_branch_ops, 345 .flags = CLK_SET_RATE_PARENT, 346 }, 347 }, 348 }; 349 350 static struct clk_branch csi0_phy_clk = { 351 .halt_reg = 0x01e8, 352 .halt_bit = 9, 353 .clkr = { 354 .enable_reg = 0x0040, 355 .enable_mask = BIT(8), 356 .hw.init = &(struct clk_init_data){ 357 .parent_names = (const char *[]){ "csi0_src" }, 358 .num_parents = 1, 359 .name = "csi0_phy_clk", 360 .ops = &clk_branch_ops, 361 .flags = CLK_SET_RATE_PARENT, 362 }, 363 }, 364 }; 365 366 static struct clk_rcg csi1_src = { 367 .ns_reg = 0x0010, 368 .md_reg = 0x0028, 369 .mn = { 370 .mnctr_en_bit = 5, 371 .mnctr_reset_bit = 7, 372 .mnctr_mode_shift = 6, 373 .n_val_shift = 24, 374 .m_val_shift = 8, 375 .width = 8, 376 }, 377 .p = { 378 .pre_div_shift = 14, 379 .pre_div_width = 2, 380 }, 381 .s = { 382 .src_sel_shift = 0, 383 .parent_map = mmcc_pxo_pll8_pll2_map, 384 }, 385 .freq_tbl = clk_tbl_csi, 386 .clkr = { 387 .enable_reg = 0x0024, 388 .enable_mask = BIT(2), 389 .hw.init = &(struct clk_init_data){ 390 .name = "csi1_src", 391 .parent_names = mmcc_pxo_pll8_pll2, 392 .num_parents = 3, 393 .ops = &clk_rcg_ops, 394 }, 395 }, 396 }; 397 398 static struct clk_branch csi1_clk = { 399 .halt_reg = 0x01cc, 400 .halt_bit = 14, 401 .clkr = { 402 .enable_reg = 0x0024, 403 .enable_mask = BIT(0), 404 .hw.init = &(struct clk_init_data){ 405 .parent_names = (const char *[]){ "csi1_src" }, 406 .num_parents = 1, 407 .name = "csi1_clk", 408 .ops = &clk_branch_ops, 409 .flags = CLK_SET_RATE_PARENT, 410 }, 411 }, 412 }; 413 414 static struct clk_branch csi1_phy_clk = { 415 .halt_reg = 0x01e8, 416 .halt_bit = 10, 417 .clkr = { 418 .enable_reg = 0x0024, 419 .enable_mask = BIT(8), 420 .hw.init = &(struct clk_init_data){ 421 .parent_names = (const char *[]){ "csi1_src" }, 422 .num_parents = 1, 423 .name = "csi1_phy_clk", 424 .ops = &clk_branch_ops, 425 .flags = CLK_SET_RATE_PARENT, 426 }, 427 }, 428 }; 429 430 static struct clk_rcg csi2_src = { 431 .ns_reg = 0x0234, 432 .md_reg = 0x022c, 433 .mn = { 434 .mnctr_en_bit = 5, 435 .mnctr_reset_bit = 7, 436 .mnctr_mode_shift = 6, 437 .n_val_shift = 24, 438 .m_val_shift = 8, 439 .width = 8, 440 }, 441 .p = { 442 .pre_div_shift = 14, 443 .pre_div_width = 2, 444 }, 445 .s = { 446 .src_sel_shift = 0, 447 .parent_map = mmcc_pxo_pll8_pll2_map, 448 }, 449 .freq_tbl = clk_tbl_csi, 450 .clkr = { 451 .enable_reg = 0x022c, 452 .enable_mask = BIT(2), 453 .hw.init = &(struct clk_init_data){ 454 .name = "csi2_src", 455 .parent_names = mmcc_pxo_pll8_pll2, 456 .num_parents = 3, 457 .ops = &clk_rcg_ops, 458 }, 459 }, 460 }; 461 462 static struct clk_branch csi2_clk = { 463 .halt_reg = 0x01cc, 464 .halt_bit = 29, 465 .clkr = { 466 .enable_reg = 0x022c, 467 .enable_mask = BIT(0), 468 .hw.init = &(struct clk_init_data){ 469 .parent_names = (const char *[]){ "csi2_src" }, 470 .num_parents = 1, 471 .name = "csi2_clk", 472 .ops = &clk_branch_ops, 473 .flags = CLK_SET_RATE_PARENT, 474 }, 475 }, 476 }; 477 478 static struct clk_branch csi2_phy_clk = { 479 .halt_reg = 0x01e8, 480 .halt_bit = 29, 481 .clkr = { 482 .enable_reg = 0x022c, 483 .enable_mask = BIT(8), 484 .hw.init = &(struct clk_init_data){ 485 .parent_names = (const char *[]){ "csi2_src" }, 486 .num_parents = 1, 487 .name = "csi2_phy_clk", 488 .ops = &clk_branch_ops, 489 .flags = CLK_SET_RATE_PARENT, 490 }, 491 }, 492 }; 493 494 struct clk_pix_rdi { 495 u32 s_reg; 496 u32 s_mask; 497 u32 s2_reg; 498 u32 s2_mask; 499 struct clk_regmap clkr; 500 }; 501 502 #define to_clk_pix_rdi(_hw) \ 503 container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr) 504 505 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) 506 { 507 int i; 508 int ret = 0; 509 u32 val; 510 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); 511 struct clk *clk = hw->clk; 512 int num_parents = __clk_get_num_parents(hw->clk); 513 514 /* 515 * These clocks select three inputs via two muxes. One mux selects 516 * between csi0 and csi1 and the second mux selects between that mux's 517 * output and csi2. The source and destination selections for each 518 * mux must be clocking for the switch to succeed so just turn on 519 * all three sources because it's easier than figuring out what source 520 * needs to be on at what time. 521 */ 522 for (i = 0; i < num_parents; i++) { 523 ret = clk_prepare_enable(clk_get_parent_by_index(clk, i)); 524 if (ret) 525 goto err; 526 } 527 528 if (index == 2) 529 val = rdi->s2_mask; 530 else 531 val = 0; 532 regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val); 533 /* 534 * Wait at least 6 cycles of slowest clock 535 * for the glitch-free MUX to fully switch sources. 536 */ 537 udelay(1); 538 539 if (index == 1) 540 val = rdi->s_mask; 541 else 542 val = 0; 543 regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val); 544 /* 545 * Wait at least 6 cycles of slowest clock 546 * for the glitch-free MUX to fully switch sources. 547 */ 548 udelay(1); 549 550 err: 551 for (i--; i >= 0; i--) 552 clk_disable_unprepare(clk_get_parent_by_index(clk, i)); 553 554 return ret; 555 } 556 557 static u8 pix_rdi_get_parent(struct clk_hw *hw) 558 { 559 u32 val; 560 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); 561 562 563 regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val); 564 if (val & rdi->s2_mask) 565 return 2; 566 567 regmap_read(rdi->clkr.regmap, rdi->s_reg, &val); 568 if (val & rdi->s_mask) 569 return 1; 570 571 return 0; 572 } 573 574 static const struct clk_ops clk_ops_pix_rdi = { 575 .enable = clk_enable_regmap, 576 .disable = clk_disable_regmap, 577 .set_parent = pix_rdi_set_parent, 578 .get_parent = pix_rdi_get_parent, 579 .determine_rate = __clk_mux_determine_rate, 580 }; 581 582 static const char *pix_rdi_parents[] = { 583 "csi0_clk", 584 "csi1_clk", 585 "csi2_clk", 586 }; 587 588 static struct clk_pix_rdi csi_pix_clk = { 589 .s_reg = 0x0058, 590 .s_mask = BIT(25), 591 .s2_reg = 0x0238, 592 .s2_mask = BIT(13), 593 .clkr = { 594 .enable_reg = 0x0058, 595 .enable_mask = BIT(26), 596 .hw.init = &(struct clk_init_data){ 597 .name = "csi_pix_clk", 598 .parent_names = pix_rdi_parents, 599 .num_parents = 3, 600 .ops = &clk_ops_pix_rdi, 601 }, 602 }, 603 }; 604 605 static struct clk_pix_rdi csi_pix1_clk = { 606 .s_reg = 0x0238, 607 .s_mask = BIT(8), 608 .s2_reg = 0x0238, 609 .s2_mask = BIT(9), 610 .clkr = { 611 .enable_reg = 0x0238, 612 .enable_mask = BIT(10), 613 .hw.init = &(struct clk_init_data){ 614 .name = "csi_pix1_clk", 615 .parent_names = pix_rdi_parents, 616 .num_parents = 3, 617 .ops = &clk_ops_pix_rdi, 618 }, 619 }, 620 }; 621 622 static struct clk_pix_rdi csi_rdi_clk = { 623 .s_reg = 0x0058, 624 .s_mask = BIT(12), 625 .s2_reg = 0x0238, 626 .s2_mask = BIT(12), 627 .clkr = { 628 .enable_reg = 0x0058, 629 .enable_mask = BIT(13), 630 .hw.init = &(struct clk_init_data){ 631 .name = "csi_rdi_clk", 632 .parent_names = pix_rdi_parents, 633 .num_parents = 3, 634 .ops = &clk_ops_pix_rdi, 635 }, 636 }, 637 }; 638 639 static struct clk_pix_rdi csi_rdi1_clk = { 640 .s_reg = 0x0238, 641 .s_mask = BIT(0), 642 .s2_reg = 0x0238, 643 .s2_mask = BIT(1), 644 .clkr = { 645 .enable_reg = 0x0238, 646 .enable_mask = BIT(2), 647 .hw.init = &(struct clk_init_data){ 648 .name = "csi_rdi1_clk", 649 .parent_names = pix_rdi_parents, 650 .num_parents = 3, 651 .ops = &clk_ops_pix_rdi, 652 }, 653 }, 654 }; 655 656 static struct clk_pix_rdi csi_rdi2_clk = { 657 .s_reg = 0x0238, 658 .s_mask = BIT(4), 659 .s2_reg = 0x0238, 660 .s2_mask = BIT(5), 661 .clkr = { 662 .enable_reg = 0x0238, 663 .enable_mask = BIT(6), 664 .hw.init = &(struct clk_init_data){ 665 .name = "csi_rdi2_clk", 666 .parent_names = pix_rdi_parents, 667 .num_parents = 3, 668 .ops = &clk_ops_pix_rdi, 669 }, 670 }, 671 }; 672 673 static struct freq_tbl clk_tbl_csiphytimer[] = { 674 { 85330000, P_PLL8, 1, 2, 9 }, 675 { 177780000, P_PLL2, 1, 2, 9 }, 676 { } 677 }; 678 679 static struct clk_rcg csiphytimer_src = { 680 .ns_reg = 0x0168, 681 .md_reg = 0x0164, 682 .mn = { 683 .mnctr_en_bit = 5, 684 .mnctr_reset_bit = 8, 685 .reset_in_cc = true, 686 .mnctr_mode_shift = 6, 687 .n_val_shift = 24, 688 .m_val_shift = 8, 689 .width = 8, 690 }, 691 .p = { 692 .pre_div_shift = 14, 693 .pre_div_width = 2, 694 }, 695 .s = { 696 .src_sel_shift = 0, 697 .parent_map = mmcc_pxo_pll8_pll2_map, 698 }, 699 .freq_tbl = clk_tbl_csiphytimer, 700 .clkr = { 701 .enable_reg = 0x0160, 702 .enable_mask = BIT(2), 703 .hw.init = &(struct clk_init_data){ 704 .name = "csiphytimer_src", 705 .parent_names = mmcc_pxo_pll8_pll2, 706 .num_parents = 3, 707 .ops = &clk_rcg_ops, 708 }, 709 }, 710 }; 711 712 static const char *csixphy_timer_src[] = { "csiphytimer_src" }; 713 714 static struct clk_branch csiphy0_timer_clk = { 715 .halt_reg = 0x01e8, 716 .halt_bit = 17, 717 .clkr = { 718 .enable_reg = 0x0160, 719 .enable_mask = BIT(0), 720 .hw.init = &(struct clk_init_data){ 721 .parent_names = csixphy_timer_src, 722 .num_parents = 1, 723 .name = "csiphy0_timer_clk", 724 .ops = &clk_branch_ops, 725 .flags = CLK_SET_RATE_PARENT, 726 }, 727 }, 728 }; 729 730 static struct clk_branch csiphy1_timer_clk = { 731 .halt_reg = 0x01e8, 732 .halt_bit = 18, 733 .clkr = { 734 .enable_reg = 0x0160, 735 .enable_mask = BIT(9), 736 .hw.init = &(struct clk_init_data){ 737 .parent_names = csixphy_timer_src, 738 .num_parents = 1, 739 .name = "csiphy1_timer_clk", 740 .ops = &clk_branch_ops, 741 .flags = CLK_SET_RATE_PARENT, 742 }, 743 }, 744 }; 745 746 static struct clk_branch csiphy2_timer_clk = { 747 .halt_reg = 0x01e8, 748 .halt_bit = 30, 749 .clkr = { 750 .enable_reg = 0x0160, 751 .enable_mask = BIT(11), 752 .hw.init = &(struct clk_init_data){ 753 .parent_names = csixphy_timer_src, 754 .num_parents = 1, 755 .name = "csiphy2_timer_clk", 756 .ops = &clk_branch_ops, 757 .flags = CLK_SET_RATE_PARENT, 758 }, 759 }, 760 }; 761 762 static struct freq_tbl clk_tbl_gfx2d[] = { 763 F_MN( 27000000, P_PXO, 1, 0), 764 F_MN( 48000000, P_PLL8, 1, 8), 765 F_MN( 54857000, P_PLL8, 1, 7), 766 F_MN( 64000000, P_PLL8, 1, 6), 767 F_MN( 76800000, P_PLL8, 1, 5), 768 F_MN( 96000000, P_PLL8, 1, 4), 769 F_MN(128000000, P_PLL8, 1, 3), 770 F_MN(145455000, P_PLL2, 2, 11), 771 F_MN(160000000, P_PLL2, 1, 5), 772 F_MN(177778000, P_PLL2, 2, 9), 773 F_MN(200000000, P_PLL2, 1, 4), 774 F_MN(228571000, P_PLL2, 2, 7), 775 { } 776 }; 777 778 static struct clk_dyn_rcg gfx2d0_src = { 779 .ns_reg[0] = 0x0070, 780 .ns_reg[1] = 0x0070, 781 .md_reg[0] = 0x0064, 782 .md_reg[1] = 0x0068, 783 .bank_reg = 0x0060, 784 .mn[0] = { 785 .mnctr_en_bit = 8, 786 .mnctr_reset_bit = 25, 787 .mnctr_mode_shift = 9, 788 .n_val_shift = 20, 789 .m_val_shift = 4, 790 .width = 4, 791 }, 792 .mn[1] = { 793 .mnctr_en_bit = 5, 794 .mnctr_reset_bit = 24, 795 .mnctr_mode_shift = 6, 796 .n_val_shift = 16, 797 .m_val_shift = 4, 798 .width = 4, 799 }, 800 .s[0] = { 801 .src_sel_shift = 3, 802 .parent_map = mmcc_pxo_pll8_pll2_map, 803 }, 804 .s[1] = { 805 .src_sel_shift = 0, 806 .parent_map = mmcc_pxo_pll8_pll2_map, 807 }, 808 .mux_sel_bit = 11, 809 .freq_tbl = clk_tbl_gfx2d, 810 .clkr = { 811 .enable_reg = 0x0060, 812 .enable_mask = BIT(2), 813 .hw.init = &(struct clk_init_data){ 814 .name = "gfx2d0_src", 815 .parent_names = mmcc_pxo_pll8_pll2, 816 .num_parents = 3, 817 .ops = &clk_dyn_rcg_ops, 818 }, 819 }, 820 }; 821 822 static struct clk_branch gfx2d0_clk = { 823 .halt_reg = 0x01c8, 824 .halt_bit = 9, 825 .clkr = { 826 .enable_reg = 0x0060, 827 .enable_mask = BIT(0), 828 .hw.init = &(struct clk_init_data){ 829 .name = "gfx2d0_clk", 830 .parent_names = (const char *[]){ "gfx2d0_src" }, 831 .num_parents = 1, 832 .ops = &clk_branch_ops, 833 .flags = CLK_SET_RATE_PARENT, 834 }, 835 }, 836 }; 837 838 static struct clk_dyn_rcg gfx2d1_src = { 839 .ns_reg[0] = 0x007c, 840 .ns_reg[1] = 0x007c, 841 .md_reg[0] = 0x0078, 842 .md_reg[1] = 0x006c, 843 .bank_reg = 0x0074, 844 .mn[0] = { 845 .mnctr_en_bit = 8, 846 .mnctr_reset_bit = 25, 847 .mnctr_mode_shift = 9, 848 .n_val_shift = 20, 849 .m_val_shift = 4, 850 .width = 4, 851 }, 852 .mn[1] = { 853 .mnctr_en_bit = 5, 854 .mnctr_reset_bit = 24, 855 .mnctr_mode_shift = 6, 856 .n_val_shift = 16, 857 .m_val_shift = 4, 858 .width = 4, 859 }, 860 .s[0] = { 861 .src_sel_shift = 3, 862 .parent_map = mmcc_pxo_pll8_pll2_map, 863 }, 864 .s[1] = { 865 .src_sel_shift = 0, 866 .parent_map = mmcc_pxo_pll8_pll2_map, 867 }, 868 .mux_sel_bit = 11, 869 .freq_tbl = clk_tbl_gfx2d, 870 .clkr = { 871 .enable_reg = 0x0074, 872 .enable_mask = BIT(2), 873 .hw.init = &(struct clk_init_data){ 874 .name = "gfx2d1_src", 875 .parent_names = mmcc_pxo_pll8_pll2, 876 .num_parents = 3, 877 .ops = &clk_dyn_rcg_ops, 878 }, 879 }, 880 }; 881 882 static struct clk_branch gfx2d1_clk = { 883 .halt_reg = 0x01c8, 884 .halt_bit = 14, 885 .clkr = { 886 .enable_reg = 0x0074, 887 .enable_mask = BIT(0), 888 .hw.init = &(struct clk_init_data){ 889 .name = "gfx2d1_clk", 890 .parent_names = (const char *[]){ "gfx2d1_src" }, 891 .num_parents = 1, 892 .ops = &clk_branch_ops, 893 .flags = CLK_SET_RATE_PARENT, 894 }, 895 }, 896 }; 897 898 static struct freq_tbl clk_tbl_gfx3d[] = { 899 F_MN( 27000000, P_PXO, 1, 0), 900 F_MN( 48000000, P_PLL8, 1, 8), 901 F_MN( 54857000, P_PLL8, 1, 7), 902 F_MN( 64000000, P_PLL8, 1, 6), 903 F_MN( 76800000, P_PLL8, 1, 5), 904 F_MN( 96000000, P_PLL8, 1, 4), 905 F_MN(128000000, P_PLL8, 1, 3), 906 F_MN(145455000, P_PLL2, 2, 11), 907 F_MN(160000000, P_PLL2, 1, 5), 908 F_MN(177778000, P_PLL2, 2, 9), 909 F_MN(200000000, P_PLL2, 1, 4), 910 F_MN(228571000, P_PLL2, 2, 7), 911 F_MN(266667000, P_PLL2, 1, 3), 912 F_MN(300000000, P_PLL3, 1, 4), 913 F_MN(320000000, P_PLL2, 2, 5), 914 F_MN(400000000, P_PLL2, 1, 2), 915 { } 916 }; 917 918 static struct freq_tbl clk_tbl_gfx3d_8064[] = { 919 F_MN( 27000000, P_PXO, 0, 0), 920 F_MN( 48000000, P_PLL8, 1, 8), 921 F_MN( 54857000, P_PLL8, 1, 7), 922 F_MN( 64000000, P_PLL8, 1, 6), 923 F_MN( 76800000, P_PLL8, 1, 5), 924 F_MN( 96000000, P_PLL8, 1, 4), 925 F_MN(128000000, P_PLL8, 1, 3), 926 F_MN(145455000, P_PLL2, 2, 11), 927 F_MN(160000000, P_PLL2, 1, 5), 928 F_MN(177778000, P_PLL2, 2, 9), 929 F_MN(192000000, P_PLL8, 1, 2), 930 F_MN(200000000, P_PLL2, 1, 4), 931 F_MN(228571000, P_PLL2, 2, 7), 932 F_MN(266667000, P_PLL2, 1, 3), 933 F_MN(320000000, P_PLL2, 2, 5), 934 F_MN(400000000, P_PLL2, 1, 2), 935 F_MN(450000000, P_PLL15, 1, 2), 936 { } 937 }; 938 939 static struct clk_dyn_rcg gfx3d_src = { 940 .ns_reg[0] = 0x008c, 941 .ns_reg[1] = 0x008c, 942 .md_reg[0] = 0x0084, 943 .md_reg[1] = 0x0088, 944 .bank_reg = 0x0080, 945 .mn[0] = { 946 .mnctr_en_bit = 8, 947 .mnctr_reset_bit = 25, 948 .mnctr_mode_shift = 9, 949 .n_val_shift = 18, 950 .m_val_shift = 4, 951 .width = 4, 952 }, 953 .mn[1] = { 954 .mnctr_en_bit = 5, 955 .mnctr_reset_bit = 24, 956 .mnctr_mode_shift = 6, 957 .n_val_shift = 14, 958 .m_val_shift = 4, 959 .width = 4, 960 }, 961 .s[0] = { 962 .src_sel_shift = 3, 963 .parent_map = mmcc_pxo_pll8_pll2_pll3_map, 964 }, 965 .s[1] = { 966 .src_sel_shift = 0, 967 .parent_map = mmcc_pxo_pll8_pll2_pll3_map, 968 }, 969 .mux_sel_bit = 11, 970 .freq_tbl = clk_tbl_gfx3d, 971 .clkr = { 972 .enable_reg = 0x0080, 973 .enable_mask = BIT(2), 974 .hw.init = &(struct clk_init_data){ 975 .name = "gfx3d_src", 976 .parent_names = mmcc_pxo_pll8_pll2_pll3, 977 .num_parents = 4, 978 .ops = &clk_dyn_rcg_ops, 979 }, 980 }, 981 }; 982 983 static const struct clk_init_data gfx3d_8064_init = { 984 .name = "gfx3d_src", 985 .parent_names = mmcc_pxo_pll8_pll2_pll15, 986 .num_parents = 4, 987 .ops = &clk_dyn_rcg_ops, 988 }; 989 990 static struct clk_branch gfx3d_clk = { 991 .halt_reg = 0x01c8, 992 .halt_bit = 4, 993 .clkr = { 994 .enable_reg = 0x0080, 995 .enable_mask = BIT(0), 996 .hw.init = &(struct clk_init_data){ 997 .name = "gfx3d_clk", 998 .parent_names = (const char *[]){ "gfx3d_src" }, 999 .num_parents = 1, 1000 .ops = &clk_branch_ops, 1001 .flags = CLK_SET_RATE_PARENT, 1002 }, 1003 }, 1004 }; 1005 1006 static struct freq_tbl clk_tbl_vcap[] = { 1007 F_MN( 27000000, P_PXO, 0, 0), 1008 F_MN( 54860000, P_PLL8, 1, 7), 1009 F_MN( 64000000, P_PLL8, 1, 6), 1010 F_MN( 76800000, P_PLL8, 1, 5), 1011 F_MN(128000000, P_PLL8, 1, 3), 1012 F_MN(160000000, P_PLL2, 1, 5), 1013 F_MN(200000000, P_PLL2, 1, 4), 1014 { } 1015 }; 1016 1017 static struct clk_dyn_rcg vcap_src = { 1018 .ns_reg[0] = 0x021c, 1019 .ns_reg[1] = 0x021c, 1020 .md_reg[0] = 0x01ec, 1021 .md_reg[1] = 0x0218, 1022 .bank_reg = 0x0178, 1023 .mn[0] = { 1024 .mnctr_en_bit = 8, 1025 .mnctr_reset_bit = 23, 1026 .mnctr_mode_shift = 9, 1027 .n_val_shift = 18, 1028 .m_val_shift = 4, 1029 .width = 4, 1030 }, 1031 .mn[1] = { 1032 .mnctr_en_bit = 5, 1033 .mnctr_reset_bit = 22, 1034 .mnctr_mode_shift = 6, 1035 .n_val_shift = 14, 1036 .m_val_shift = 4, 1037 .width = 4, 1038 }, 1039 .s[0] = { 1040 .src_sel_shift = 3, 1041 .parent_map = mmcc_pxo_pll8_pll2_map, 1042 }, 1043 .s[1] = { 1044 .src_sel_shift = 0, 1045 .parent_map = mmcc_pxo_pll8_pll2_map, 1046 }, 1047 .mux_sel_bit = 11, 1048 .freq_tbl = clk_tbl_vcap, 1049 .clkr = { 1050 .enable_reg = 0x0178, 1051 .enable_mask = BIT(2), 1052 .hw.init = &(struct clk_init_data){ 1053 .name = "vcap_src", 1054 .parent_names = mmcc_pxo_pll8_pll2, 1055 .num_parents = 3, 1056 .ops = &clk_dyn_rcg_ops, 1057 }, 1058 }, 1059 }; 1060 1061 static struct clk_branch vcap_clk = { 1062 .halt_reg = 0x0240, 1063 .halt_bit = 15, 1064 .clkr = { 1065 .enable_reg = 0x0178, 1066 .enable_mask = BIT(0), 1067 .hw.init = &(struct clk_init_data){ 1068 .name = "vcap_clk", 1069 .parent_names = (const char *[]){ "vcap_src" }, 1070 .num_parents = 1, 1071 .ops = &clk_branch_ops, 1072 .flags = CLK_SET_RATE_PARENT, 1073 }, 1074 }, 1075 }; 1076 1077 static struct clk_branch vcap_npl_clk = { 1078 .halt_reg = 0x0240, 1079 .halt_bit = 25, 1080 .clkr = { 1081 .enable_reg = 0x0178, 1082 .enable_mask = BIT(13), 1083 .hw.init = &(struct clk_init_data){ 1084 .name = "vcap_npl_clk", 1085 .parent_names = (const char *[]){ "vcap_src" }, 1086 .num_parents = 1, 1087 .ops = &clk_branch_ops, 1088 .flags = CLK_SET_RATE_PARENT, 1089 }, 1090 }, 1091 }; 1092 1093 static struct freq_tbl clk_tbl_ijpeg[] = { 1094 { 27000000, P_PXO, 1, 0, 0 }, 1095 { 36570000, P_PLL8, 1, 2, 21 }, 1096 { 54860000, P_PLL8, 7, 0, 0 }, 1097 { 96000000, P_PLL8, 4, 0, 0 }, 1098 { 109710000, P_PLL8, 1, 2, 7 }, 1099 { 128000000, P_PLL8, 3, 0, 0 }, 1100 { 153600000, P_PLL8, 1, 2, 5 }, 1101 { 200000000, P_PLL2, 4, 0, 0 }, 1102 { 228571000, P_PLL2, 1, 2, 7 }, 1103 { 266667000, P_PLL2, 1, 1, 3 }, 1104 { 320000000, P_PLL2, 1, 2, 5 }, 1105 { } 1106 }; 1107 1108 static struct clk_rcg ijpeg_src = { 1109 .ns_reg = 0x00a0, 1110 .md_reg = 0x009c, 1111 .mn = { 1112 .mnctr_en_bit = 5, 1113 .mnctr_reset_bit = 7, 1114 .mnctr_mode_shift = 6, 1115 .n_val_shift = 16, 1116 .m_val_shift = 8, 1117 .width = 8, 1118 }, 1119 .p = { 1120 .pre_div_shift = 12, 1121 .pre_div_width = 2, 1122 }, 1123 .s = { 1124 .src_sel_shift = 0, 1125 .parent_map = mmcc_pxo_pll8_pll2_map, 1126 }, 1127 .freq_tbl = clk_tbl_ijpeg, 1128 .clkr = { 1129 .enable_reg = 0x0098, 1130 .enable_mask = BIT(2), 1131 .hw.init = &(struct clk_init_data){ 1132 .name = "ijpeg_src", 1133 .parent_names = mmcc_pxo_pll8_pll2, 1134 .num_parents = 3, 1135 .ops = &clk_rcg_ops, 1136 }, 1137 }, 1138 }; 1139 1140 static struct clk_branch ijpeg_clk = { 1141 .halt_reg = 0x01c8, 1142 .halt_bit = 24, 1143 .clkr = { 1144 .enable_reg = 0x0098, 1145 .enable_mask = BIT(0), 1146 .hw.init = &(struct clk_init_data){ 1147 .name = "ijpeg_clk", 1148 .parent_names = (const char *[]){ "ijpeg_src" }, 1149 .num_parents = 1, 1150 .ops = &clk_branch_ops, 1151 .flags = CLK_SET_RATE_PARENT, 1152 }, 1153 }, 1154 }; 1155 1156 static struct freq_tbl clk_tbl_jpegd[] = { 1157 { 64000000, P_PLL8, 6 }, 1158 { 76800000, P_PLL8, 5 }, 1159 { 96000000, P_PLL8, 4 }, 1160 { 160000000, P_PLL2, 5 }, 1161 { 200000000, P_PLL2, 4 }, 1162 { } 1163 }; 1164 1165 static struct clk_rcg jpegd_src = { 1166 .ns_reg = 0x00ac, 1167 .p = { 1168 .pre_div_shift = 12, 1169 .pre_div_width = 4, 1170 }, 1171 .s = { 1172 .src_sel_shift = 0, 1173 .parent_map = mmcc_pxo_pll8_pll2_map, 1174 }, 1175 .freq_tbl = clk_tbl_jpegd, 1176 .clkr = { 1177 .enable_reg = 0x00a4, 1178 .enable_mask = BIT(2), 1179 .hw.init = &(struct clk_init_data){ 1180 .name = "jpegd_src", 1181 .parent_names = mmcc_pxo_pll8_pll2, 1182 .num_parents = 3, 1183 .ops = &clk_rcg_ops, 1184 }, 1185 }, 1186 }; 1187 1188 static struct clk_branch jpegd_clk = { 1189 .halt_reg = 0x01c8, 1190 .halt_bit = 19, 1191 .clkr = { 1192 .enable_reg = 0x00a4, 1193 .enable_mask = BIT(0), 1194 .hw.init = &(struct clk_init_data){ 1195 .name = "jpegd_clk", 1196 .parent_names = (const char *[]){ "jpegd_src" }, 1197 .num_parents = 1, 1198 .ops = &clk_branch_ops, 1199 .flags = CLK_SET_RATE_PARENT, 1200 }, 1201 }, 1202 }; 1203 1204 static struct freq_tbl clk_tbl_mdp[] = { 1205 { 9600000, P_PLL8, 1, 1, 40 }, 1206 { 13710000, P_PLL8, 1, 1, 28 }, 1207 { 27000000, P_PXO, 1, 0, 0 }, 1208 { 29540000, P_PLL8, 1, 1, 13 }, 1209 { 34910000, P_PLL8, 1, 1, 11 }, 1210 { 38400000, P_PLL8, 1, 1, 10 }, 1211 { 59080000, P_PLL8, 1, 2, 13 }, 1212 { 76800000, P_PLL8, 1, 1, 5 }, 1213 { 85330000, P_PLL8, 1, 2, 9 }, 1214 { 96000000, P_PLL8, 1, 1, 4 }, 1215 { 128000000, P_PLL8, 1, 1, 3 }, 1216 { 160000000, P_PLL2, 1, 1, 5 }, 1217 { 177780000, P_PLL2, 1, 2, 9 }, 1218 { 200000000, P_PLL2, 1, 1, 4 }, 1219 { 228571000, P_PLL2, 1, 2, 7 }, 1220 { 266667000, P_PLL2, 1, 1, 3 }, 1221 { } 1222 }; 1223 1224 static struct clk_dyn_rcg mdp_src = { 1225 .ns_reg[0] = 0x00d0, 1226 .ns_reg[1] = 0x00d0, 1227 .md_reg[0] = 0x00c4, 1228 .md_reg[1] = 0x00c8, 1229 .bank_reg = 0x00c0, 1230 .mn[0] = { 1231 .mnctr_en_bit = 8, 1232 .mnctr_reset_bit = 31, 1233 .mnctr_mode_shift = 9, 1234 .n_val_shift = 22, 1235 .m_val_shift = 8, 1236 .width = 8, 1237 }, 1238 .mn[1] = { 1239 .mnctr_en_bit = 5, 1240 .mnctr_reset_bit = 30, 1241 .mnctr_mode_shift = 6, 1242 .n_val_shift = 14, 1243 .m_val_shift = 8, 1244 .width = 8, 1245 }, 1246 .s[0] = { 1247 .src_sel_shift = 3, 1248 .parent_map = mmcc_pxo_pll8_pll2_map, 1249 }, 1250 .s[1] = { 1251 .src_sel_shift = 0, 1252 .parent_map = mmcc_pxo_pll8_pll2_map, 1253 }, 1254 .mux_sel_bit = 11, 1255 .freq_tbl = clk_tbl_mdp, 1256 .clkr = { 1257 .enable_reg = 0x00c0, 1258 .enable_mask = BIT(2), 1259 .hw.init = &(struct clk_init_data){ 1260 .name = "mdp_src", 1261 .parent_names = mmcc_pxo_pll8_pll2, 1262 .num_parents = 3, 1263 .ops = &clk_dyn_rcg_ops, 1264 }, 1265 }, 1266 }; 1267 1268 static struct clk_branch mdp_clk = { 1269 .halt_reg = 0x01d0, 1270 .halt_bit = 10, 1271 .clkr = { 1272 .enable_reg = 0x00c0, 1273 .enable_mask = BIT(0), 1274 .hw.init = &(struct clk_init_data){ 1275 .name = "mdp_clk", 1276 .parent_names = (const char *[]){ "mdp_src" }, 1277 .num_parents = 1, 1278 .ops = &clk_branch_ops, 1279 .flags = CLK_SET_RATE_PARENT, 1280 }, 1281 }, 1282 }; 1283 1284 static struct clk_branch mdp_lut_clk = { 1285 .halt_reg = 0x01e8, 1286 .halt_bit = 13, 1287 .clkr = { 1288 .enable_reg = 0x016c, 1289 .enable_mask = BIT(0), 1290 .hw.init = &(struct clk_init_data){ 1291 .parent_names = (const char *[]){ "mdp_src" }, 1292 .num_parents = 1, 1293 .name = "mdp_lut_clk", 1294 .ops = &clk_branch_ops, 1295 .flags = CLK_SET_RATE_PARENT, 1296 }, 1297 }, 1298 }; 1299 1300 static struct clk_branch mdp_vsync_clk = { 1301 .halt_reg = 0x01cc, 1302 .halt_bit = 22, 1303 .clkr = { 1304 .enable_reg = 0x0058, 1305 .enable_mask = BIT(6), 1306 .hw.init = &(struct clk_init_data){ 1307 .name = "mdp_vsync_clk", 1308 .parent_names = (const char *[]){ "pxo" }, 1309 .num_parents = 1, 1310 .ops = &clk_branch_ops 1311 }, 1312 }, 1313 }; 1314 1315 static struct freq_tbl clk_tbl_rot[] = { 1316 { 27000000, P_PXO, 1 }, 1317 { 29540000, P_PLL8, 13 }, 1318 { 32000000, P_PLL8, 12 }, 1319 { 38400000, P_PLL8, 10 }, 1320 { 48000000, P_PLL8, 8 }, 1321 { 54860000, P_PLL8, 7 }, 1322 { 64000000, P_PLL8, 6 }, 1323 { 76800000, P_PLL8, 5 }, 1324 { 96000000, P_PLL8, 4 }, 1325 { 100000000, P_PLL2, 8 }, 1326 { 114290000, P_PLL2, 7 }, 1327 { 133330000, P_PLL2, 6 }, 1328 { 160000000, P_PLL2, 5 }, 1329 { 200000000, P_PLL2, 4 }, 1330 { } 1331 }; 1332 1333 static struct clk_dyn_rcg rot_src = { 1334 .ns_reg[0] = 0x00e8, 1335 .ns_reg[1] = 0x00e8, 1336 .bank_reg = 0x00e8, 1337 .p[0] = { 1338 .pre_div_shift = 22, 1339 .pre_div_width = 4, 1340 }, 1341 .p[1] = { 1342 .pre_div_shift = 26, 1343 .pre_div_width = 4, 1344 }, 1345 .s[0] = { 1346 .src_sel_shift = 16, 1347 .parent_map = mmcc_pxo_pll8_pll2_map, 1348 }, 1349 .s[1] = { 1350 .src_sel_shift = 19, 1351 .parent_map = mmcc_pxo_pll8_pll2_map, 1352 }, 1353 .mux_sel_bit = 30, 1354 .freq_tbl = clk_tbl_rot, 1355 .clkr = { 1356 .enable_reg = 0x00e0, 1357 .enable_mask = BIT(2), 1358 .hw.init = &(struct clk_init_data){ 1359 .name = "rot_src", 1360 .parent_names = mmcc_pxo_pll8_pll2, 1361 .num_parents = 3, 1362 .ops = &clk_dyn_rcg_ops, 1363 }, 1364 }, 1365 }; 1366 1367 static struct clk_branch rot_clk = { 1368 .halt_reg = 0x01d0, 1369 .halt_bit = 15, 1370 .clkr = { 1371 .enable_reg = 0x00e0, 1372 .enable_mask = BIT(0), 1373 .hw.init = &(struct clk_init_data){ 1374 .name = "rot_clk", 1375 .parent_names = (const char *[]){ "rot_src" }, 1376 .num_parents = 1, 1377 .ops = &clk_branch_ops, 1378 .flags = CLK_SET_RATE_PARENT, 1379 }, 1380 }, 1381 }; 1382 1383 static const struct parent_map mmcc_pxo_hdmi_map[] = { 1384 { P_PXO, 0 }, 1385 { P_HDMI_PLL, 3 } 1386 }; 1387 1388 static const char *mmcc_pxo_hdmi[] = { 1389 "pxo", 1390 "hdmi_pll", 1391 }; 1392 1393 static struct freq_tbl clk_tbl_tv[] = { 1394 { .src = P_HDMI_PLL, .pre_div = 1 }, 1395 { } 1396 }; 1397 1398 static struct clk_rcg tv_src = { 1399 .ns_reg = 0x00f4, 1400 .md_reg = 0x00f0, 1401 .mn = { 1402 .mnctr_en_bit = 5, 1403 .mnctr_reset_bit = 7, 1404 .mnctr_mode_shift = 6, 1405 .n_val_shift = 16, 1406 .m_val_shift = 8, 1407 .width = 8, 1408 }, 1409 .p = { 1410 .pre_div_shift = 14, 1411 .pre_div_width = 2, 1412 }, 1413 .s = { 1414 .src_sel_shift = 0, 1415 .parent_map = mmcc_pxo_hdmi_map, 1416 }, 1417 .freq_tbl = clk_tbl_tv, 1418 .clkr = { 1419 .enable_reg = 0x00ec, 1420 .enable_mask = BIT(2), 1421 .hw.init = &(struct clk_init_data){ 1422 .name = "tv_src", 1423 .parent_names = mmcc_pxo_hdmi, 1424 .num_parents = 2, 1425 .ops = &clk_rcg_bypass_ops, 1426 .flags = CLK_SET_RATE_PARENT, 1427 }, 1428 }, 1429 }; 1430 1431 static const char *tv_src_name[] = { "tv_src" }; 1432 1433 static struct clk_branch tv_enc_clk = { 1434 .halt_reg = 0x01d4, 1435 .halt_bit = 9, 1436 .clkr = { 1437 .enable_reg = 0x00ec, 1438 .enable_mask = BIT(8), 1439 .hw.init = &(struct clk_init_data){ 1440 .parent_names = tv_src_name, 1441 .num_parents = 1, 1442 .name = "tv_enc_clk", 1443 .ops = &clk_branch_ops, 1444 .flags = CLK_SET_RATE_PARENT, 1445 }, 1446 }, 1447 }; 1448 1449 static struct clk_branch tv_dac_clk = { 1450 .halt_reg = 0x01d4, 1451 .halt_bit = 10, 1452 .clkr = { 1453 .enable_reg = 0x00ec, 1454 .enable_mask = BIT(10), 1455 .hw.init = &(struct clk_init_data){ 1456 .parent_names = tv_src_name, 1457 .num_parents = 1, 1458 .name = "tv_dac_clk", 1459 .ops = &clk_branch_ops, 1460 .flags = CLK_SET_RATE_PARENT, 1461 }, 1462 }, 1463 }; 1464 1465 static struct clk_branch mdp_tv_clk = { 1466 .halt_reg = 0x01d4, 1467 .halt_bit = 12, 1468 .clkr = { 1469 .enable_reg = 0x00ec, 1470 .enable_mask = BIT(0), 1471 .hw.init = &(struct clk_init_data){ 1472 .parent_names = tv_src_name, 1473 .num_parents = 1, 1474 .name = "mdp_tv_clk", 1475 .ops = &clk_branch_ops, 1476 .flags = CLK_SET_RATE_PARENT, 1477 }, 1478 }, 1479 }; 1480 1481 static struct clk_branch hdmi_tv_clk = { 1482 .halt_reg = 0x01d4, 1483 .halt_bit = 11, 1484 .clkr = { 1485 .enable_reg = 0x00ec, 1486 .enable_mask = BIT(12), 1487 .hw.init = &(struct clk_init_data){ 1488 .parent_names = tv_src_name, 1489 .num_parents = 1, 1490 .name = "hdmi_tv_clk", 1491 .ops = &clk_branch_ops, 1492 .flags = CLK_SET_RATE_PARENT, 1493 }, 1494 }, 1495 }; 1496 1497 static struct clk_branch rgb_tv_clk = { 1498 .halt_reg = 0x0240, 1499 .halt_bit = 27, 1500 .clkr = { 1501 .enable_reg = 0x0124, 1502 .enable_mask = BIT(14), 1503 .hw.init = &(struct clk_init_data){ 1504 .parent_names = tv_src_name, 1505 .num_parents = 1, 1506 .name = "rgb_tv_clk", 1507 .ops = &clk_branch_ops, 1508 .flags = CLK_SET_RATE_PARENT, 1509 }, 1510 }, 1511 }; 1512 1513 static struct clk_branch npl_tv_clk = { 1514 .halt_reg = 0x0240, 1515 .halt_bit = 26, 1516 .clkr = { 1517 .enable_reg = 0x0124, 1518 .enable_mask = BIT(16), 1519 .hw.init = &(struct clk_init_data){ 1520 .parent_names = tv_src_name, 1521 .num_parents = 1, 1522 .name = "npl_tv_clk", 1523 .ops = &clk_branch_ops, 1524 .flags = CLK_SET_RATE_PARENT, 1525 }, 1526 }, 1527 }; 1528 1529 static struct clk_branch hdmi_app_clk = { 1530 .halt_reg = 0x01cc, 1531 .halt_bit = 25, 1532 .clkr = { 1533 .enable_reg = 0x005c, 1534 .enable_mask = BIT(11), 1535 .hw.init = &(struct clk_init_data){ 1536 .parent_names = (const char *[]){ "pxo" }, 1537 .num_parents = 1, 1538 .name = "hdmi_app_clk", 1539 .ops = &clk_branch_ops, 1540 }, 1541 }, 1542 }; 1543 1544 static struct freq_tbl clk_tbl_vcodec[] = { 1545 F_MN( 27000000, P_PXO, 1, 0), 1546 F_MN( 32000000, P_PLL8, 1, 12), 1547 F_MN( 48000000, P_PLL8, 1, 8), 1548 F_MN( 54860000, P_PLL8, 1, 7), 1549 F_MN( 96000000, P_PLL8, 1, 4), 1550 F_MN(133330000, P_PLL2, 1, 6), 1551 F_MN(200000000, P_PLL2, 1, 4), 1552 F_MN(228570000, P_PLL2, 2, 7), 1553 F_MN(266670000, P_PLL2, 1, 3), 1554 { } 1555 }; 1556 1557 static struct clk_dyn_rcg vcodec_src = { 1558 .ns_reg[0] = 0x0100, 1559 .ns_reg[1] = 0x0100, 1560 .md_reg[0] = 0x00fc, 1561 .md_reg[1] = 0x0128, 1562 .bank_reg = 0x00f8, 1563 .mn[0] = { 1564 .mnctr_en_bit = 5, 1565 .mnctr_reset_bit = 31, 1566 .mnctr_mode_shift = 6, 1567 .n_val_shift = 11, 1568 .m_val_shift = 8, 1569 .width = 8, 1570 }, 1571 .mn[1] = { 1572 .mnctr_en_bit = 10, 1573 .mnctr_reset_bit = 30, 1574 .mnctr_mode_shift = 11, 1575 .n_val_shift = 19, 1576 .m_val_shift = 8, 1577 .width = 8, 1578 }, 1579 .s[0] = { 1580 .src_sel_shift = 27, 1581 .parent_map = mmcc_pxo_pll8_pll2_map, 1582 }, 1583 .s[1] = { 1584 .src_sel_shift = 0, 1585 .parent_map = mmcc_pxo_pll8_pll2_map, 1586 }, 1587 .mux_sel_bit = 13, 1588 .freq_tbl = clk_tbl_vcodec, 1589 .clkr = { 1590 .enable_reg = 0x00f8, 1591 .enable_mask = BIT(2), 1592 .hw.init = &(struct clk_init_data){ 1593 .name = "vcodec_src", 1594 .parent_names = mmcc_pxo_pll8_pll2, 1595 .num_parents = 3, 1596 .ops = &clk_dyn_rcg_ops, 1597 }, 1598 }, 1599 }; 1600 1601 static struct clk_branch vcodec_clk = { 1602 .halt_reg = 0x01d0, 1603 .halt_bit = 29, 1604 .clkr = { 1605 .enable_reg = 0x00f8, 1606 .enable_mask = BIT(0), 1607 .hw.init = &(struct clk_init_data){ 1608 .name = "vcodec_clk", 1609 .parent_names = (const char *[]){ "vcodec_src" }, 1610 .num_parents = 1, 1611 .ops = &clk_branch_ops, 1612 .flags = CLK_SET_RATE_PARENT, 1613 }, 1614 }, 1615 }; 1616 1617 static struct freq_tbl clk_tbl_vpe[] = { 1618 { 27000000, P_PXO, 1 }, 1619 { 34909000, P_PLL8, 11 }, 1620 { 38400000, P_PLL8, 10 }, 1621 { 64000000, P_PLL8, 6 }, 1622 { 76800000, P_PLL8, 5 }, 1623 { 96000000, P_PLL8, 4 }, 1624 { 100000000, P_PLL2, 8 }, 1625 { 160000000, P_PLL2, 5 }, 1626 { } 1627 }; 1628 1629 static struct clk_rcg vpe_src = { 1630 .ns_reg = 0x0118, 1631 .p = { 1632 .pre_div_shift = 12, 1633 .pre_div_width = 4, 1634 }, 1635 .s = { 1636 .src_sel_shift = 0, 1637 .parent_map = mmcc_pxo_pll8_pll2_map, 1638 }, 1639 .freq_tbl = clk_tbl_vpe, 1640 .clkr = { 1641 .enable_reg = 0x0110, 1642 .enable_mask = BIT(2), 1643 .hw.init = &(struct clk_init_data){ 1644 .name = "vpe_src", 1645 .parent_names = mmcc_pxo_pll8_pll2, 1646 .num_parents = 3, 1647 .ops = &clk_rcg_ops, 1648 }, 1649 }, 1650 }; 1651 1652 static struct clk_branch vpe_clk = { 1653 .halt_reg = 0x01c8, 1654 .halt_bit = 28, 1655 .clkr = { 1656 .enable_reg = 0x0110, 1657 .enable_mask = BIT(0), 1658 .hw.init = &(struct clk_init_data){ 1659 .name = "vpe_clk", 1660 .parent_names = (const char *[]){ "vpe_src" }, 1661 .num_parents = 1, 1662 .ops = &clk_branch_ops, 1663 .flags = CLK_SET_RATE_PARENT, 1664 }, 1665 }, 1666 }; 1667 1668 static struct freq_tbl clk_tbl_vfe[] = { 1669 { 13960000, P_PLL8, 1, 2, 55 }, 1670 { 27000000, P_PXO, 1, 0, 0 }, 1671 { 36570000, P_PLL8, 1, 2, 21 }, 1672 { 38400000, P_PLL8, 2, 1, 5 }, 1673 { 45180000, P_PLL8, 1, 2, 17 }, 1674 { 48000000, P_PLL8, 2, 1, 4 }, 1675 { 54860000, P_PLL8, 1, 1, 7 }, 1676 { 64000000, P_PLL8, 2, 1, 3 }, 1677 { 76800000, P_PLL8, 1, 1, 5 }, 1678 { 96000000, P_PLL8, 2, 1, 2 }, 1679 { 109710000, P_PLL8, 1, 2, 7 }, 1680 { 128000000, P_PLL8, 1, 1, 3 }, 1681 { 153600000, P_PLL8, 1, 2, 5 }, 1682 { 200000000, P_PLL2, 2, 1, 2 }, 1683 { 228570000, P_PLL2, 1, 2, 7 }, 1684 { 266667000, P_PLL2, 1, 1, 3 }, 1685 { 320000000, P_PLL2, 1, 2, 5 }, 1686 { } 1687 }; 1688 1689 static struct clk_rcg vfe_src = { 1690 .ns_reg = 0x0108, 1691 .mn = { 1692 .mnctr_en_bit = 5, 1693 .mnctr_reset_bit = 7, 1694 .mnctr_mode_shift = 6, 1695 .n_val_shift = 16, 1696 .m_val_shift = 8, 1697 .width = 8, 1698 }, 1699 .p = { 1700 .pre_div_shift = 10, 1701 .pre_div_width = 1, 1702 }, 1703 .s = { 1704 .src_sel_shift = 0, 1705 .parent_map = mmcc_pxo_pll8_pll2_map, 1706 }, 1707 .freq_tbl = clk_tbl_vfe, 1708 .clkr = { 1709 .enable_reg = 0x0104, 1710 .enable_mask = BIT(2), 1711 .hw.init = &(struct clk_init_data){ 1712 .name = "vfe_src", 1713 .parent_names = mmcc_pxo_pll8_pll2, 1714 .num_parents = 3, 1715 .ops = &clk_rcg_ops, 1716 }, 1717 }, 1718 }; 1719 1720 static struct clk_branch vfe_clk = { 1721 .halt_reg = 0x01cc, 1722 .halt_bit = 6, 1723 .clkr = { 1724 .enable_reg = 0x0104, 1725 .enable_mask = BIT(0), 1726 .hw.init = &(struct clk_init_data){ 1727 .name = "vfe_clk", 1728 .parent_names = (const char *[]){ "vfe_src" }, 1729 .num_parents = 1, 1730 .ops = &clk_branch_ops, 1731 .flags = CLK_SET_RATE_PARENT, 1732 }, 1733 }, 1734 }; 1735 1736 static struct clk_branch vfe_csi_clk = { 1737 .halt_reg = 0x01cc, 1738 .halt_bit = 8, 1739 .clkr = { 1740 .enable_reg = 0x0104, 1741 .enable_mask = BIT(12), 1742 .hw.init = &(struct clk_init_data){ 1743 .parent_names = (const char *[]){ "vfe_src" }, 1744 .num_parents = 1, 1745 .name = "vfe_csi_clk", 1746 .ops = &clk_branch_ops, 1747 .flags = CLK_SET_RATE_PARENT, 1748 }, 1749 }, 1750 }; 1751 1752 static struct clk_branch gmem_axi_clk = { 1753 .halt_reg = 0x01d8, 1754 .halt_bit = 6, 1755 .clkr = { 1756 .enable_reg = 0x0018, 1757 .enable_mask = BIT(24), 1758 .hw.init = &(struct clk_init_data){ 1759 .name = "gmem_axi_clk", 1760 .ops = &clk_branch_ops, 1761 .flags = CLK_IS_ROOT, 1762 }, 1763 }, 1764 }; 1765 1766 static struct clk_branch ijpeg_axi_clk = { 1767 .hwcg_reg = 0x0018, 1768 .hwcg_bit = 11, 1769 .halt_reg = 0x01d8, 1770 .halt_bit = 4, 1771 .clkr = { 1772 .enable_reg = 0x0018, 1773 .enable_mask = BIT(21), 1774 .hw.init = &(struct clk_init_data){ 1775 .name = "ijpeg_axi_clk", 1776 .ops = &clk_branch_ops, 1777 .flags = CLK_IS_ROOT, 1778 }, 1779 }, 1780 }; 1781 1782 static struct clk_branch mmss_imem_axi_clk = { 1783 .hwcg_reg = 0x0018, 1784 .hwcg_bit = 15, 1785 .halt_reg = 0x01d8, 1786 .halt_bit = 7, 1787 .clkr = { 1788 .enable_reg = 0x0018, 1789 .enable_mask = BIT(22), 1790 .hw.init = &(struct clk_init_data){ 1791 .name = "mmss_imem_axi_clk", 1792 .ops = &clk_branch_ops, 1793 .flags = CLK_IS_ROOT, 1794 }, 1795 }, 1796 }; 1797 1798 static struct clk_branch jpegd_axi_clk = { 1799 .halt_reg = 0x01d8, 1800 .halt_bit = 5, 1801 .clkr = { 1802 .enable_reg = 0x0018, 1803 .enable_mask = BIT(25), 1804 .hw.init = &(struct clk_init_data){ 1805 .name = "jpegd_axi_clk", 1806 .ops = &clk_branch_ops, 1807 .flags = CLK_IS_ROOT, 1808 }, 1809 }, 1810 }; 1811 1812 static struct clk_branch vcodec_axi_b_clk = { 1813 .hwcg_reg = 0x0114, 1814 .hwcg_bit = 22, 1815 .halt_reg = 0x01e8, 1816 .halt_bit = 25, 1817 .clkr = { 1818 .enable_reg = 0x0114, 1819 .enable_mask = BIT(23), 1820 .hw.init = &(struct clk_init_data){ 1821 .name = "vcodec_axi_b_clk", 1822 .ops = &clk_branch_ops, 1823 .flags = CLK_IS_ROOT, 1824 }, 1825 }, 1826 }; 1827 1828 static struct clk_branch vcodec_axi_a_clk = { 1829 .hwcg_reg = 0x0114, 1830 .hwcg_bit = 24, 1831 .halt_reg = 0x01e8, 1832 .halt_bit = 26, 1833 .clkr = { 1834 .enable_reg = 0x0114, 1835 .enable_mask = BIT(25), 1836 .hw.init = &(struct clk_init_data){ 1837 .name = "vcodec_axi_a_clk", 1838 .ops = &clk_branch_ops, 1839 .flags = CLK_IS_ROOT, 1840 }, 1841 }, 1842 }; 1843 1844 static struct clk_branch vcodec_axi_clk = { 1845 .hwcg_reg = 0x0018, 1846 .hwcg_bit = 13, 1847 .halt_reg = 0x01d8, 1848 .halt_bit = 3, 1849 .clkr = { 1850 .enable_reg = 0x0018, 1851 .enable_mask = BIT(19), 1852 .hw.init = &(struct clk_init_data){ 1853 .name = "vcodec_axi_clk", 1854 .ops = &clk_branch_ops, 1855 .flags = CLK_IS_ROOT, 1856 }, 1857 }, 1858 }; 1859 1860 static struct clk_branch vfe_axi_clk = { 1861 .halt_reg = 0x01d8, 1862 .halt_bit = 0, 1863 .clkr = { 1864 .enable_reg = 0x0018, 1865 .enable_mask = BIT(18), 1866 .hw.init = &(struct clk_init_data){ 1867 .name = "vfe_axi_clk", 1868 .ops = &clk_branch_ops, 1869 .flags = CLK_IS_ROOT, 1870 }, 1871 }, 1872 }; 1873 1874 static struct clk_branch mdp_axi_clk = { 1875 .hwcg_reg = 0x0018, 1876 .hwcg_bit = 16, 1877 .halt_reg = 0x01d8, 1878 .halt_bit = 8, 1879 .clkr = { 1880 .enable_reg = 0x0018, 1881 .enable_mask = BIT(23), 1882 .hw.init = &(struct clk_init_data){ 1883 .name = "mdp_axi_clk", 1884 .ops = &clk_branch_ops, 1885 .flags = CLK_IS_ROOT, 1886 }, 1887 }, 1888 }; 1889 1890 static struct clk_branch rot_axi_clk = { 1891 .hwcg_reg = 0x0020, 1892 .hwcg_bit = 25, 1893 .halt_reg = 0x01d8, 1894 .halt_bit = 2, 1895 .clkr = { 1896 .enable_reg = 0x0020, 1897 .enable_mask = BIT(24), 1898 .hw.init = &(struct clk_init_data){ 1899 .name = "rot_axi_clk", 1900 .ops = &clk_branch_ops, 1901 .flags = CLK_IS_ROOT, 1902 }, 1903 }, 1904 }; 1905 1906 static struct clk_branch vcap_axi_clk = { 1907 .halt_reg = 0x0240, 1908 .halt_bit = 20, 1909 .hwcg_reg = 0x0244, 1910 .hwcg_bit = 11, 1911 .clkr = { 1912 .enable_reg = 0x0244, 1913 .enable_mask = BIT(12), 1914 .hw.init = &(struct clk_init_data){ 1915 .name = "vcap_axi_clk", 1916 .ops = &clk_branch_ops, 1917 .flags = CLK_IS_ROOT, 1918 }, 1919 }, 1920 }; 1921 1922 static struct clk_branch vpe_axi_clk = { 1923 .hwcg_reg = 0x0020, 1924 .hwcg_bit = 27, 1925 .halt_reg = 0x01d8, 1926 .halt_bit = 1, 1927 .clkr = { 1928 .enable_reg = 0x0020, 1929 .enable_mask = BIT(26), 1930 .hw.init = &(struct clk_init_data){ 1931 .name = "vpe_axi_clk", 1932 .ops = &clk_branch_ops, 1933 .flags = CLK_IS_ROOT, 1934 }, 1935 }, 1936 }; 1937 1938 static struct clk_branch gfx3d_axi_clk = { 1939 .hwcg_reg = 0x0244, 1940 .hwcg_bit = 24, 1941 .halt_reg = 0x0240, 1942 .halt_bit = 30, 1943 .clkr = { 1944 .enable_reg = 0x0244, 1945 .enable_mask = BIT(25), 1946 .hw.init = &(struct clk_init_data){ 1947 .name = "gfx3d_axi_clk", 1948 .ops = &clk_branch_ops, 1949 .flags = CLK_IS_ROOT, 1950 }, 1951 }, 1952 }; 1953 1954 static struct clk_branch amp_ahb_clk = { 1955 .halt_reg = 0x01dc, 1956 .halt_bit = 18, 1957 .clkr = { 1958 .enable_reg = 0x0008, 1959 .enable_mask = BIT(24), 1960 .hw.init = &(struct clk_init_data){ 1961 .name = "amp_ahb_clk", 1962 .ops = &clk_branch_ops, 1963 .flags = CLK_IS_ROOT, 1964 }, 1965 }, 1966 }; 1967 1968 static struct clk_branch csi_ahb_clk = { 1969 .halt_reg = 0x01dc, 1970 .halt_bit = 16, 1971 .clkr = { 1972 .enable_reg = 0x0008, 1973 .enable_mask = BIT(7), 1974 .hw.init = &(struct clk_init_data){ 1975 .name = "csi_ahb_clk", 1976 .ops = &clk_branch_ops, 1977 .flags = CLK_IS_ROOT 1978 }, 1979 }, 1980 }; 1981 1982 static struct clk_branch dsi_m_ahb_clk = { 1983 .halt_reg = 0x01dc, 1984 .halt_bit = 19, 1985 .clkr = { 1986 .enable_reg = 0x0008, 1987 .enable_mask = BIT(9), 1988 .hw.init = &(struct clk_init_data){ 1989 .name = "dsi_m_ahb_clk", 1990 .ops = &clk_branch_ops, 1991 .flags = CLK_IS_ROOT, 1992 }, 1993 }, 1994 }; 1995 1996 static struct clk_branch dsi_s_ahb_clk = { 1997 .hwcg_reg = 0x0038, 1998 .hwcg_bit = 20, 1999 .halt_reg = 0x01dc, 2000 .halt_bit = 21, 2001 .clkr = { 2002 .enable_reg = 0x0008, 2003 .enable_mask = BIT(18), 2004 .hw.init = &(struct clk_init_data){ 2005 .name = "dsi_s_ahb_clk", 2006 .ops = &clk_branch_ops, 2007 .flags = CLK_IS_ROOT, 2008 }, 2009 }, 2010 }; 2011 2012 static struct clk_branch dsi2_m_ahb_clk = { 2013 .halt_reg = 0x01d8, 2014 .halt_bit = 18, 2015 .clkr = { 2016 .enable_reg = 0x0008, 2017 .enable_mask = BIT(17), 2018 .hw.init = &(struct clk_init_data){ 2019 .name = "dsi2_m_ahb_clk", 2020 .ops = &clk_branch_ops, 2021 .flags = CLK_IS_ROOT 2022 }, 2023 }, 2024 }; 2025 2026 static struct clk_branch dsi2_s_ahb_clk = { 2027 .hwcg_reg = 0x0038, 2028 .hwcg_bit = 15, 2029 .halt_reg = 0x01dc, 2030 .halt_bit = 20, 2031 .clkr = { 2032 .enable_reg = 0x0008, 2033 .enable_mask = BIT(22), 2034 .hw.init = &(struct clk_init_data){ 2035 .name = "dsi2_s_ahb_clk", 2036 .ops = &clk_branch_ops, 2037 .flags = CLK_IS_ROOT, 2038 }, 2039 }, 2040 }; 2041 2042 static struct clk_branch gfx2d0_ahb_clk = { 2043 .hwcg_reg = 0x0038, 2044 .hwcg_bit = 28, 2045 .halt_reg = 0x01dc, 2046 .halt_bit = 2, 2047 .clkr = { 2048 .enable_reg = 0x0008, 2049 .enable_mask = BIT(19), 2050 .hw.init = &(struct clk_init_data){ 2051 .name = "gfx2d0_ahb_clk", 2052 .ops = &clk_branch_ops, 2053 .flags = CLK_IS_ROOT, 2054 }, 2055 }, 2056 }; 2057 2058 static struct clk_branch gfx2d1_ahb_clk = { 2059 .hwcg_reg = 0x0038, 2060 .hwcg_bit = 29, 2061 .halt_reg = 0x01dc, 2062 .halt_bit = 3, 2063 .clkr = { 2064 .enable_reg = 0x0008, 2065 .enable_mask = BIT(2), 2066 .hw.init = &(struct clk_init_data){ 2067 .name = "gfx2d1_ahb_clk", 2068 .ops = &clk_branch_ops, 2069 .flags = CLK_IS_ROOT, 2070 }, 2071 }, 2072 }; 2073 2074 static struct clk_branch gfx3d_ahb_clk = { 2075 .hwcg_reg = 0x0038, 2076 .hwcg_bit = 27, 2077 .halt_reg = 0x01dc, 2078 .halt_bit = 4, 2079 .clkr = { 2080 .enable_reg = 0x0008, 2081 .enable_mask = BIT(3), 2082 .hw.init = &(struct clk_init_data){ 2083 .name = "gfx3d_ahb_clk", 2084 .ops = &clk_branch_ops, 2085 .flags = CLK_IS_ROOT, 2086 }, 2087 }, 2088 }; 2089 2090 static struct clk_branch hdmi_m_ahb_clk = { 2091 .hwcg_reg = 0x0038, 2092 .hwcg_bit = 21, 2093 .halt_reg = 0x01dc, 2094 .halt_bit = 5, 2095 .clkr = { 2096 .enable_reg = 0x0008, 2097 .enable_mask = BIT(14), 2098 .hw.init = &(struct clk_init_data){ 2099 .name = "hdmi_m_ahb_clk", 2100 .ops = &clk_branch_ops, 2101 .flags = CLK_IS_ROOT, 2102 }, 2103 }, 2104 }; 2105 2106 static struct clk_branch hdmi_s_ahb_clk = { 2107 .hwcg_reg = 0x0038, 2108 .hwcg_bit = 22, 2109 .halt_reg = 0x01dc, 2110 .halt_bit = 6, 2111 .clkr = { 2112 .enable_reg = 0x0008, 2113 .enable_mask = BIT(4), 2114 .hw.init = &(struct clk_init_data){ 2115 .name = "hdmi_s_ahb_clk", 2116 .ops = &clk_branch_ops, 2117 .flags = CLK_IS_ROOT, 2118 }, 2119 }, 2120 }; 2121 2122 static struct clk_branch ijpeg_ahb_clk = { 2123 .halt_reg = 0x01dc, 2124 .halt_bit = 9, 2125 .clkr = { 2126 .enable_reg = 0x0008, 2127 .enable_mask = BIT(5), 2128 .hw.init = &(struct clk_init_data){ 2129 .name = "ijpeg_ahb_clk", 2130 .ops = &clk_branch_ops, 2131 .flags = CLK_IS_ROOT 2132 }, 2133 }, 2134 }; 2135 2136 static struct clk_branch mmss_imem_ahb_clk = { 2137 .hwcg_reg = 0x0038, 2138 .hwcg_bit = 12, 2139 .halt_reg = 0x01dc, 2140 .halt_bit = 10, 2141 .clkr = { 2142 .enable_reg = 0x0008, 2143 .enable_mask = BIT(6), 2144 .hw.init = &(struct clk_init_data){ 2145 .name = "mmss_imem_ahb_clk", 2146 .ops = &clk_branch_ops, 2147 .flags = CLK_IS_ROOT 2148 }, 2149 }, 2150 }; 2151 2152 static struct clk_branch jpegd_ahb_clk = { 2153 .halt_reg = 0x01dc, 2154 .halt_bit = 7, 2155 .clkr = { 2156 .enable_reg = 0x0008, 2157 .enable_mask = BIT(21), 2158 .hw.init = &(struct clk_init_data){ 2159 .name = "jpegd_ahb_clk", 2160 .ops = &clk_branch_ops, 2161 .flags = CLK_IS_ROOT, 2162 }, 2163 }, 2164 }; 2165 2166 static struct clk_branch mdp_ahb_clk = { 2167 .halt_reg = 0x01dc, 2168 .halt_bit = 11, 2169 .clkr = { 2170 .enable_reg = 0x0008, 2171 .enable_mask = BIT(10), 2172 .hw.init = &(struct clk_init_data){ 2173 .name = "mdp_ahb_clk", 2174 .ops = &clk_branch_ops, 2175 .flags = CLK_IS_ROOT, 2176 }, 2177 }, 2178 }; 2179 2180 static struct clk_branch rot_ahb_clk = { 2181 .halt_reg = 0x01dc, 2182 .halt_bit = 13, 2183 .clkr = { 2184 .enable_reg = 0x0008, 2185 .enable_mask = BIT(12), 2186 .hw.init = &(struct clk_init_data){ 2187 .name = "rot_ahb_clk", 2188 .ops = &clk_branch_ops, 2189 .flags = CLK_IS_ROOT 2190 }, 2191 }, 2192 }; 2193 2194 static struct clk_branch smmu_ahb_clk = { 2195 .hwcg_reg = 0x0008, 2196 .hwcg_bit = 26, 2197 .halt_reg = 0x01dc, 2198 .halt_bit = 22, 2199 .clkr = { 2200 .enable_reg = 0x0008, 2201 .enable_mask = BIT(15), 2202 .hw.init = &(struct clk_init_data){ 2203 .name = "smmu_ahb_clk", 2204 .ops = &clk_branch_ops, 2205 .flags = CLK_IS_ROOT, 2206 }, 2207 }, 2208 }; 2209 2210 static struct clk_branch tv_enc_ahb_clk = { 2211 .halt_reg = 0x01dc, 2212 .halt_bit = 23, 2213 .clkr = { 2214 .enable_reg = 0x0008, 2215 .enable_mask = BIT(25), 2216 .hw.init = &(struct clk_init_data){ 2217 .name = "tv_enc_ahb_clk", 2218 .ops = &clk_branch_ops, 2219 .flags = CLK_IS_ROOT, 2220 }, 2221 }, 2222 }; 2223 2224 static struct clk_branch vcap_ahb_clk = { 2225 .halt_reg = 0x0240, 2226 .halt_bit = 23, 2227 .clkr = { 2228 .enable_reg = 0x0248, 2229 .enable_mask = BIT(1), 2230 .hw.init = &(struct clk_init_data){ 2231 .name = "vcap_ahb_clk", 2232 .ops = &clk_branch_ops, 2233 .flags = CLK_IS_ROOT, 2234 }, 2235 }, 2236 }; 2237 2238 static struct clk_branch vcodec_ahb_clk = { 2239 .hwcg_reg = 0x0038, 2240 .hwcg_bit = 26, 2241 .halt_reg = 0x01dc, 2242 .halt_bit = 12, 2243 .clkr = { 2244 .enable_reg = 0x0008, 2245 .enable_mask = BIT(11), 2246 .hw.init = &(struct clk_init_data){ 2247 .name = "vcodec_ahb_clk", 2248 .ops = &clk_branch_ops, 2249 .flags = CLK_IS_ROOT, 2250 }, 2251 }, 2252 }; 2253 2254 static struct clk_branch vfe_ahb_clk = { 2255 .halt_reg = 0x01dc, 2256 .halt_bit = 14, 2257 .clkr = { 2258 .enable_reg = 0x0008, 2259 .enable_mask = BIT(13), 2260 .hw.init = &(struct clk_init_data){ 2261 .name = "vfe_ahb_clk", 2262 .ops = &clk_branch_ops, 2263 .flags = CLK_IS_ROOT, 2264 }, 2265 }, 2266 }; 2267 2268 static struct clk_branch vpe_ahb_clk = { 2269 .halt_reg = 0x01dc, 2270 .halt_bit = 15, 2271 .clkr = { 2272 .enable_reg = 0x0008, 2273 .enable_mask = BIT(16), 2274 .hw.init = &(struct clk_init_data){ 2275 .name = "vpe_ahb_clk", 2276 .ops = &clk_branch_ops, 2277 .flags = CLK_IS_ROOT, 2278 }, 2279 }, 2280 }; 2281 2282 static struct clk_regmap *mmcc_msm8960_clks[] = { 2283 [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr, 2284 [AMP_AHB_CLK] = &_ahb_clk.clkr, 2285 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr, 2286 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr, 2287 [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr, 2288 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr, 2289 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr, 2290 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr, 2291 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr, 2292 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr, 2293 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr, 2294 [ROT_AHB_CLK] = &rot_ahb_clk.clkr, 2295 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr, 2296 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr, 2297 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr, 2298 [CSI_AHB_CLK] = &csi_ahb_clk.clkr, 2299 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr, 2300 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr, 2301 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr, 2302 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr, 2303 [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr, 2304 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr, 2305 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr, 2306 [MDP_AXI_CLK] = &mdp_axi_clk.clkr, 2307 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr, 2308 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr, 2309 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr, 2310 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr, 2311 [VFE_AXI_CLK] = &vfe_axi_clk.clkr, 2312 [VPE_AXI_CLK] = &vpe_axi_clk.clkr, 2313 [ROT_AXI_CLK] = &rot_axi_clk.clkr, 2314 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr, 2315 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr, 2316 [CSI0_SRC] = &csi0_src.clkr, 2317 [CSI0_CLK] = &csi0_clk.clkr, 2318 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr, 2319 [CSI1_SRC] = &csi1_src.clkr, 2320 [CSI1_CLK] = &csi1_clk.clkr, 2321 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr, 2322 [CSI2_SRC] = &csi2_src.clkr, 2323 [CSI2_CLK] = &csi2_clk.clkr, 2324 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr, 2325 [CSI_PIX_CLK] = &csi_pix_clk.clkr, 2326 [CSI_RDI_CLK] = &csi_rdi_clk.clkr, 2327 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr, 2328 [HDMI_APP_CLK] = &hdmi_app_clk.clkr, 2329 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr, 2330 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr, 2331 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr, 2332 [GFX2D0_SRC] = &gfx2d0_src.clkr, 2333 [GFX2D0_CLK] = &gfx2d0_clk.clkr, 2334 [GFX2D1_SRC] = &gfx2d1_src.clkr, 2335 [GFX2D1_CLK] = &gfx2d1_clk.clkr, 2336 [GFX3D_SRC] = &gfx3d_src.clkr, 2337 [GFX3D_CLK] = &gfx3d_clk.clkr, 2338 [IJPEG_SRC] = &ijpeg_src.clkr, 2339 [IJPEG_CLK] = &ijpeg_clk.clkr, 2340 [JPEGD_SRC] = &jpegd_src.clkr, 2341 [JPEGD_CLK] = &jpegd_clk.clkr, 2342 [MDP_SRC] = &mdp_src.clkr, 2343 [MDP_CLK] = &mdp_clk.clkr, 2344 [MDP_LUT_CLK] = &mdp_lut_clk.clkr, 2345 [ROT_SRC] = &rot_src.clkr, 2346 [ROT_CLK] = &rot_clk.clkr, 2347 [TV_ENC_CLK] = &tv_enc_clk.clkr, 2348 [TV_DAC_CLK] = &tv_dac_clk.clkr, 2349 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr, 2350 [MDP_TV_CLK] = &mdp_tv_clk.clkr, 2351 [TV_SRC] = &tv_src.clkr, 2352 [VCODEC_SRC] = &vcodec_src.clkr, 2353 [VCODEC_CLK] = &vcodec_clk.clkr, 2354 [VFE_SRC] = &vfe_src.clkr, 2355 [VFE_CLK] = &vfe_clk.clkr, 2356 [VFE_CSI_CLK] = &vfe_csi_clk.clkr, 2357 [VPE_SRC] = &vpe_src.clkr, 2358 [VPE_CLK] = &vpe_clk.clkr, 2359 [CAMCLK0_SRC] = &camclk0_src.clkr, 2360 [CAMCLK0_CLK] = &camclk0_clk.clkr, 2361 [CAMCLK1_SRC] = &camclk1_src.clkr, 2362 [CAMCLK1_CLK] = &camclk1_clk.clkr, 2363 [CAMCLK2_SRC] = &camclk2_src.clkr, 2364 [CAMCLK2_CLK] = &camclk2_clk.clkr, 2365 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr, 2366 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr, 2367 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr, 2368 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr, 2369 [PLL2] = &pll2.clkr, 2370 }; 2371 2372 static const struct qcom_reset_map mmcc_msm8960_resets[] = { 2373 [VPE_AXI_RESET] = { 0x0208, 15 }, 2374 [IJPEG_AXI_RESET] = { 0x0208, 14 }, 2375 [MPD_AXI_RESET] = { 0x0208, 13 }, 2376 [VFE_AXI_RESET] = { 0x0208, 9 }, 2377 [SP_AXI_RESET] = { 0x0208, 8 }, 2378 [VCODEC_AXI_RESET] = { 0x0208, 7 }, 2379 [ROT_AXI_RESET] = { 0x0208, 6 }, 2380 [VCODEC_AXI_A_RESET] = { 0x0208, 5 }, 2381 [VCODEC_AXI_B_RESET] = { 0x0208, 4 }, 2382 [FAB_S3_AXI_RESET] = { 0x0208, 3 }, 2383 [FAB_S2_AXI_RESET] = { 0x0208, 2 }, 2384 [FAB_S1_AXI_RESET] = { 0x0208, 1 }, 2385 [FAB_S0_AXI_RESET] = { 0x0208 }, 2386 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 }, 2387 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 }, 2388 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 }, 2389 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 }, 2390 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 }, 2391 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 }, 2392 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 }, 2393 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 }, 2394 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 }, 2395 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 }, 2396 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 }, 2397 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 }, 2398 [APU_AHB_RESET] = { 0x020c, 18 }, 2399 [CSI_AHB_RESET] = { 0x020c, 17 }, 2400 [TV_ENC_AHB_RESET] = { 0x020c, 15 }, 2401 [VPE_AHB_RESET] = { 0x020c, 14 }, 2402 [FABRIC_AHB_RESET] = { 0x020c, 13 }, 2403 [GFX2D0_AHB_RESET] = { 0x020c, 12 }, 2404 [GFX2D1_AHB_RESET] = { 0x020c, 11 }, 2405 [GFX3D_AHB_RESET] = { 0x020c, 10 }, 2406 [HDMI_AHB_RESET] = { 0x020c, 9 }, 2407 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 }, 2408 [IJPEG_AHB_RESET] = { 0x020c, 7 }, 2409 [DSI_M_AHB_RESET] = { 0x020c, 6 }, 2410 [DSI_S_AHB_RESET] = { 0x020c, 5 }, 2411 [JPEGD_AHB_RESET] = { 0x020c, 4 }, 2412 [MDP_AHB_RESET] = { 0x020c, 3 }, 2413 [ROT_AHB_RESET] = { 0x020c, 2 }, 2414 [VCODEC_AHB_RESET] = { 0x020c, 1 }, 2415 [VFE_AHB_RESET] = { 0x020c, 0 }, 2416 [DSI2_M_AHB_RESET] = { 0x0210, 31 }, 2417 [DSI2_S_AHB_RESET] = { 0x0210, 30 }, 2418 [CSIPHY2_RESET] = { 0x0210, 29 }, 2419 [CSI_PIX1_RESET] = { 0x0210, 28 }, 2420 [CSIPHY0_RESET] = { 0x0210, 27 }, 2421 [CSIPHY1_RESET] = { 0x0210, 26 }, 2422 [DSI2_RESET] = { 0x0210, 25 }, 2423 [VFE_CSI_RESET] = { 0x0210, 24 }, 2424 [MDP_RESET] = { 0x0210, 21 }, 2425 [AMP_RESET] = { 0x0210, 20 }, 2426 [JPEGD_RESET] = { 0x0210, 19 }, 2427 [CSI1_RESET] = { 0x0210, 18 }, 2428 [VPE_RESET] = { 0x0210, 17 }, 2429 [MMSS_FABRIC_RESET] = { 0x0210, 16 }, 2430 [VFE_RESET] = { 0x0210, 15 }, 2431 [GFX2D0_RESET] = { 0x0210, 14 }, 2432 [GFX2D1_RESET] = { 0x0210, 13 }, 2433 [GFX3D_RESET] = { 0x0210, 12 }, 2434 [HDMI_RESET] = { 0x0210, 11 }, 2435 [MMSS_IMEM_RESET] = { 0x0210, 10 }, 2436 [IJPEG_RESET] = { 0x0210, 9 }, 2437 [CSI0_RESET] = { 0x0210, 8 }, 2438 [DSI_RESET] = { 0x0210, 7 }, 2439 [VCODEC_RESET] = { 0x0210, 6 }, 2440 [MDP_TV_RESET] = { 0x0210, 4 }, 2441 [MDP_VSYNC_RESET] = { 0x0210, 3 }, 2442 [ROT_RESET] = { 0x0210, 2 }, 2443 [TV_HDMI_RESET] = { 0x0210, 1 }, 2444 [TV_ENC_RESET] = { 0x0210 }, 2445 [CSI2_RESET] = { 0x0214, 2 }, 2446 [CSI_RDI1_RESET] = { 0x0214, 1 }, 2447 [CSI_RDI2_RESET] = { 0x0214 }, 2448 }; 2449 2450 static struct clk_regmap *mmcc_apq8064_clks[] = { 2451 [AMP_AHB_CLK] = &_ahb_clk.clkr, 2452 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr, 2453 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr, 2454 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr, 2455 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr, 2456 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr, 2457 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr, 2458 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr, 2459 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr, 2460 [ROT_AHB_CLK] = &rot_ahb_clk.clkr, 2461 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr, 2462 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr, 2463 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr, 2464 [CSI_AHB_CLK] = &csi_ahb_clk.clkr, 2465 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr, 2466 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr, 2467 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr, 2468 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr, 2469 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr, 2470 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr, 2471 [MDP_AXI_CLK] = &mdp_axi_clk.clkr, 2472 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr, 2473 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr, 2474 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr, 2475 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr, 2476 [VFE_AXI_CLK] = &vfe_axi_clk.clkr, 2477 [VPE_AXI_CLK] = &vpe_axi_clk.clkr, 2478 [ROT_AXI_CLK] = &rot_axi_clk.clkr, 2479 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr, 2480 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr, 2481 [CSI0_SRC] = &csi0_src.clkr, 2482 [CSI0_CLK] = &csi0_clk.clkr, 2483 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr, 2484 [CSI1_SRC] = &csi1_src.clkr, 2485 [CSI1_CLK] = &csi1_clk.clkr, 2486 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr, 2487 [CSI2_SRC] = &csi2_src.clkr, 2488 [CSI2_CLK] = &csi2_clk.clkr, 2489 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr, 2490 [CSI_PIX_CLK] = &csi_pix_clk.clkr, 2491 [CSI_RDI_CLK] = &csi_rdi_clk.clkr, 2492 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr, 2493 [HDMI_APP_CLK] = &hdmi_app_clk.clkr, 2494 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr, 2495 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr, 2496 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr, 2497 [GFX3D_SRC] = &gfx3d_src.clkr, 2498 [GFX3D_CLK] = &gfx3d_clk.clkr, 2499 [IJPEG_SRC] = &ijpeg_src.clkr, 2500 [IJPEG_CLK] = &ijpeg_clk.clkr, 2501 [JPEGD_SRC] = &jpegd_src.clkr, 2502 [JPEGD_CLK] = &jpegd_clk.clkr, 2503 [MDP_SRC] = &mdp_src.clkr, 2504 [MDP_CLK] = &mdp_clk.clkr, 2505 [MDP_LUT_CLK] = &mdp_lut_clk.clkr, 2506 [ROT_SRC] = &rot_src.clkr, 2507 [ROT_CLK] = &rot_clk.clkr, 2508 [TV_DAC_CLK] = &tv_dac_clk.clkr, 2509 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr, 2510 [MDP_TV_CLK] = &mdp_tv_clk.clkr, 2511 [TV_SRC] = &tv_src.clkr, 2512 [VCODEC_SRC] = &vcodec_src.clkr, 2513 [VCODEC_CLK] = &vcodec_clk.clkr, 2514 [VFE_SRC] = &vfe_src.clkr, 2515 [VFE_CLK] = &vfe_clk.clkr, 2516 [VFE_CSI_CLK] = &vfe_csi_clk.clkr, 2517 [VPE_SRC] = &vpe_src.clkr, 2518 [VPE_CLK] = &vpe_clk.clkr, 2519 [CAMCLK0_SRC] = &camclk0_src.clkr, 2520 [CAMCLK0_CLK] = &camclk0_clk.clkr, 2521 [CAMCLK1_SRC] = &camclk1_src.clkr, 2522 [CAMCLK1_CLK] = &camclk1_clk.clkr, 2523 [CAMCLK2_SRC] = &camclk2_src.clkr, 2524 [CAMCLK2_CLK] = &camclk2_clk.clkr, 2525 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr, 2526 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr, 2527 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr, 2528 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr, 2529 [PLL2] = &pll2.clkr, 2530 [RGB_TV_CLK] = &rgb_tv_clk.clkr, 2531 [NPL_TV_CLK] = &npl_tv_clk.clkr, 2532 [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr, 2533 [VCAP_AXI_CLK] = &vcap_axi_clk.clkr, 2534 [VCAP_SRC] = &vcap_src.clkr, 2535 [VCAP_CLK] = &vcap_clk.clkr, 2536 [VCAP_NPL_CLK] = &vcap_npl_clk.clkr, 2537 [PLL15] = &pll15.clkr, 2538 }; 2539 2540 static const struct qcom_reset_map mmcc_apq8064_resets[] = { 2541 [GFX3D_AXI_RESET] = { 0x0208, 17 }, 2542 [VCAP_AXI_RESET] = { 0x0208, 16 }, 2543 [VPE_AXI_RESET] = { 0x0208, 15 }, 2544 [IJPEG_AXI_RESET] = { 0x0208, 14 }, 2545 [MPD_AXI_RESET] = { 0x0208, 13 }, 2546 [VFE_AXI_RESET] = { 0x0208, 9 }, 2547 [SP_AXI_RESET] = { 0x0208, 8 }, 2548 [VCODEC_AXI_RESET] = { 0x0208, 7 }, 2549 [ROT_AXI_RESET] = { 0x0208, 6 }, 2550 [VCODEC_AXI_A_RESET] = { 0x0208, 5 }, 2551 [VCODEC_AXI_B_RESET] = { 0x0208, 4 }, 2552 [FAB_S3_AXI_RESET] = { 0x0208, 3 }, 2553 [FAB_S2_AXI_RESET] = { 0x0208, 2 }, 2554 [FAB_S1_AXI_RESET] = { 0x0208, 1 }, 2555 [FAB_S0_AXI_RESET] = { 0x0208 }, 2556 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 }, 2557 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 }, 2558 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 }, 2559 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 }, 2560 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 }, 2561 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 }, 2562 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 }, 2563 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 }, 2564 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 }, 2565 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 }, 2566 [APU_AHB_RESET] = { 0x020c, 18 }, 2567 [CSI_AHB_RESET] = { 0x020c, 17 }, 2568 [TV_ENC_AHB_RESET] = { 0x020c, 15 }, 2569 [VPE_AHB_RESET] = { 0x020c, 14 }, 2570 [FABRIC_AHB_RESET] = { 0x020c, 13 }, 2571 [GFX3D_AHB_RESET] = { 0x020c, 10 }, 2572 [HDMI_AHB_RESET] = { 0x020c, 9 }, 2573 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 }, 2574 [IJPEG_AHB_RESET] = { 0x020c, 7 }, 2575 [DSI_M_AHB_RESET] = { 0x020c, 6 }, 2576 [DSI_S_AHB_RESET] = { 0x020c, 5 }, 2577 [JPEGD_AHB_RESET] = { 0x020c, 4 }, 2578 [MDP_AHB_RESET] = { 0x020c, 3 }, 2579 [ROT_AHB_RESET] = { 0x020c, 2 }, 2580 [VCODEC_AHB_RESET] = { 0x020c, 1 }, 2581 [VFE_AHB_RESET] = { 0x020c, 0 }, 2582 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 }, 2583 [VCAP_AHB_RESET] = { 0x0200, 2 }, 2584 [DSI2_M_AHB_RESET] = { 0x0200, 1 }, 2585 [DSI2_S_AHB_RESET] = { 0x0200, 0 }, 2586 [CSIPHY2_RESET] = { 0x0210, 31 }, 2587 [CSI_PIX1_RESET] = { 0x0210, 30 }, 2588 [CSIPHY0_RESET] = { 0x0210, 29 }, 2589 [CSIPHY1_RESET] = { 0x0210, 28 }, 2590 [CSI_RDI_RESET] = { 0x0210, 27 }, 2591 [CSI_PIX_RESET] = { 0x0210, 26 }, 2592 [DSI2_RESET] = { 0x0210, 25 }, 2593 [VFE_CSI_RESET] = { 0x0210, 24 }, 2594 [MDP_RESET] = { 0x0210, 21 }, 2595 [AMP_RESET] = { 0x0210, 20 }, 2596 [JPEGD_RESET] = { 0x0210, 19 }, 2597 [CSI1_RESET] = { 0x0210, 18 }, 2598 [VPE_RESET] = { 0x0210, 17 }, 2599 [MMSS_FABRIC_RESET] = { 0x0210, 16 }, 2600 [VFE_RESET] = { 0x0210, 15 }, 2601 [GFX3D_RESET] = { 0x0210, 12 }, 2602 [HDMI_RESET] = { 0x0210, 11 }, 2603 [MMSS_IMEM_RESET] = { 0x0210, 10 }, 2604 [IJPEG_RESET] = { 0x0210, 9 }, 2605 [CSI0_RESET] = { 0x0210, 8 }, 2606 [DSI_RESET] = { 0x0210, 7 }, 2607 [VCODEC_RESET] = { 0x0210, 6 }, 2608 [MDP_TV_RESET] = { 0x0210, 4 }, 2609 [MDP_VSYNC_RESET] = { 0x0210, 3 }, 2610 [ROT_RESET] = { 0x0210, 2 }, 2611 [TV_HDMI_RESET] = { 0x0210, 1 }, 2612 [VCAP_NPL_RESET] = { 0x0214, 4 }, 2613 [VCAP_RESET] = { 0x0214, 3 }, 2614 [CSI2_RESET] = { 0x0214, 2 }, 2615 [CSI_RDI1_RESET] = { 0x0214, 1 }, 2616 [CSI_RDI2_RESET] = { 0x0214 }, 2617 }; 2618 2619 static const struct regmap_config mmcc_msm8960_regmap_config = { 2620 .reg_bits = 32, 2621 .reg_stride = 4, 2622 .val_bits = 32, 2623 .max_register = 0x334, 2624 .fast_io = true, 2625 }; 2626 2627 static const struct regmap_config mmcc_apq8064_regmap_config = { 2628 .reg_bits = 32, 2629 .reg_stride = 4, 2630 .val_bits = 32, 2631 .max_register = 0x350, 2632 .fast_io = true, 2633 }; 2634 2635 static const struct qcom_cc_desc mmcc_msm8960_desc = { 2636 .config = &mmcc_msm8960_regmap_config, 2637 .clks = mmcc_msm8960_clks, 2638 .num_clks = ARRAY_SIZE(mmcc_msm8960_clks), 2639 .resets = mmcc_msm8960_resets, 2640 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets), 2641 }; 2642 2643 static const struct qcom_cc_desc mmcc_apq8064_desc = { 2644 .config = &mmcc_apq8064_regmap_config, 2645 .clks = mmcc_apq8064_clks, 2646 .num_clks = ARRAY_SIZE(mmcc_apq8064_clks), 2647 .resets = mmcc_apq8064_resets, 2648 .num_resets = ARRAY_SIZE(mmcc_apq8064_resets), 2649 }; 2650 2651 static const struct of_device_id mmcc_msm8960_match_table[] = { 2652 { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc }, 2653 { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc }, 2654 { } 2655 }; 2656 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table); 2657 2658 static int mmcc_msm8960_probe(struct platform_device *pdev) 2659 { 2660 const struct of_device_id *match; 2661 struct regmap *regmap; 2662 bool is_8064; 2663 struct device *dev = &pdev->dev; 2664 2665 match = of_match_device(mmcc_msm8960_match_table, dev); 2666 if (!match) 2667 return -EINVAL; 2668 2669 is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064"); 2670 if (is_8064) { 2671 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064; 2672 gfx3d_src.clkr.hw.init = &gfx3d_8064_init; 2673 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map; 2674 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map; 2675 } 2676 2677 regmap = qcom_cc_map(pdev, match->data); 2678 if (IS_ERR(regmap)) 2679 return PTR_ERR(regmap); 2680 2681 clk_pll_configure_sr(&pll15, regmap, &pll15_config, false); 2682 2683 return qcom_cc_really_probe(pdev, match->data, regmap); 2684 } 2685 2686 static int mmcc_msm8960_remove(struct platform_device *pdev) 2687 { 2688 qcom_cc_remove(pdev); 2689 return 0; 2690 } 2691 2692 static struct platform_driver mmcc_msm8960_driver = { 2693 .probe = mmcc_msm8960_probe, 2694 .remove = mmcc_msm8960_remove, 2695 .driver = { 2696 .name = "mmcc-msm8960", 2697 .of_match_table = mmcc_msm8960_match_table, 2698 }, 2699 }; 2700 2701 module_platform_driver(mmcc_msm8960_driver); 2702 2703 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver"); 2704 MODULE_LICENSE("GPL v2"); 2705 MODULE_ALIAS("platform:mmcc-msm8960"); 2706