1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/platform_device.h>
7 #include <linux/pm_clock.h>
8 #include <linux/pm_runtime.h>
9 #include <linux/module.h>
10 #include <linux/of_address.h>
11 #include <linux/regmap.h>
12 
13 #include <dt-bindings/clock/qcom,lpass-sc7280.h>
14 
15 #include "clk-regmap.h"
16 #include "clk-branch.h"
17 #include "common.h"
18 
19 static struct clk_branch lpass_q6ss_ahbm_clk = {
20 	.halt_reg = 0x1c,
21 	.halt_check = BRANCH_HALT,
22 	.clkr = {
23 		.enable_reg = 0x1c,
24 		.enable_mask = BIT(0),
25 		.hw.init = &(struct clk_init_data){
26 			.name = "lpass_q6ss_ahbm_clk",
27 			.ops = &clk_branch2_ops,
28 		},
29 	},
30 };
31 
32 static struct clk_branch lpass_q6ss_ahbs_clk = {
33 	.halt_reg = 0x20,
34 	.halt_check = BRANCH_HALT_VOTED,
35 	.clkr = {
36 		.enable_reg = 0x20,
37 		.enable_mask = BIT(0),
38 		.hw.init = &(struct clk_init_data){
39 			.name = "lpass_q6ss_ahbs_clk",
40 			.ops = &clk_branch2_ops,
41 		},
42 	},
43 };
44 
45 static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
46 	.halt_reg = 0x0,
47 	.halt_check = BRANCH_HALT,
48 	.clkr = {
49 		.enable_reg = 0x0,
50 		.enable_mask = BIT(0),
51 		.hw.init = &(struct clk_init_data){
52 			.name = "lpass_top_cc_lpi_q6_axim_hs_clk",
53 			.ops = &clk_branch2_ops,
54 		},
55 	},
56 };
57 
58 static struct clk_branch lpass_qdsp6ss_core_clk = {
59 	.halt_reg = 0x20,
60 	/* CLK_OFF would not toggle until LPASS is out of reset */
61 	.halt_check = BRANCH_HALT_SKIP,
62 	.clkr = {
63 		.enable_reg = 0x20,
64 		.enable_mask = BIT(0),
65 		.hw.init = &(struct clk_init_data){
66 			.name = "lpass_qdsp6ss_core_clk",
67 			.ops = &clk_branch2_ops,
68 		},
69 	},
70 };
71 
72 static struct clk_branch lpass_qdsp6ss_xo_clk = {
73 	.halt_reg = 0x38,
74 	/* CLK_OFF would not toggle until LPASS is out of reset */
75 	.halt_check = BRANCH_HALT_SKIP,
76 	.clkr = {
77 		.enable_reg = 0x38,
78 		.enable_mask = BIT(0),
79 		.hw.init = &(struct clk_init_data){
80 			.name = "lpass_qdsp6ss_xo_clk",
81 			.ops = &clk_branch2_ops,
82 		},
83 	},
84 };
85 
86 static struct clk_branch lpass_qdsp6ss_sleep_clk = {
87 	.halt_reg = 0x3c,
88 	/* CLK_OFF would not toggle until LPASS is out of reset */
89 	.halt_check = BRANCH_HALT_SKIP,
90 	.clkr = {
91 		.enable_reg = 0x3c,
92 		.enable_mask = BIT(0),
93 		.hw.init = &(struct clk_init_data){
94 			.name = "lpass_qdsp6ss_sleep_clk",
95 			.ops = &clk_branch2_ops,
96 		},
97 	},
98 };
99 
100 static struct regmap_config lpass_regmap_config = {
101 	.reg_bits	= 32,
102 	.reg_stride	= 4,
103 	.val_bits	= 32,
104 	.fast_io	= true,
105 };
106 
107 static struct clk_regmap *lpass_cc_sc7280_clocks[] = {
108 	[LPASS_Q6SS_AHBM_CLK] = &lpass_q6ss_ahbm_clk.clkr,
109 	[LPASS_Q6SS_AHBS_CLK] = &lpass_q6ss_ahbs_clk.clkr,
110 };
111 
112 static const struct qcom_cc_desc lpass_cc_sc7280_desc = {
113 	.config = &lpass_regmap_config,
114 	.clks = lpass_cc_sc7280_clocks,
115 	.num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks),
116 };
117 
118 static struct clk_regmap *lpass_cc_top_sc7280_clocks[] = {
119 	[LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] =
120 				&lpass_top_cc_lpi_q6_axim_hs_clk.clkr,
121 };
122 
123 static const struct qcom_cc_desc lpass_cc_top_sc7280_desc = {
124 	.config = &lpass_regmap_config,
125 	.clks = lpass_cc_top_sc7280_clocks,
126 	.num_clks = ARRAY_SIZE(lpass_cc_top_sc7280_clocks),
127 };
128 
129 static struct clk_regmap *lpass_qdsp6ss_sc7280_clocks[] = {
130 	[LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
131 	[LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
132 	[LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
133 };
134 
135 static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = {
136 	.config = &lpass_regmap_config,
137 	.clks = lpass_qdsp6ss_sc7280_clocks,
138 	.num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks),
139 };
140 
141 static int lpass_cc_sc7280_probe(struct platform_device *pdev)
142 {
143 	const struct qcom_cc_desc *desc;
144 	int ret;
145 
146 	pm_runtime_enable(&pdev->dev);
147 	ret = pm_clk_create(&pdev->dev);
148 	if (ret)
149 		goto disable_pm_runtime;
150 
151 	ret = pm_clk_add(&pdev->dev, "iface");
152 	if (ret < 0) {
153 		dev_err(&pdev->dev, "failed to acquire iface clock\n");
154 		goto destroy_pm_clk;
155 	}
156 
157 	lpass_regmap_config.name = "qdsp6ss";
158 	desc = &lpass_qdsp6ss_sc7280_desc;
159 
160 	ret = qcom_cc_probe_by_index(pdev, 0, desc);
161 	if (ret)
162 		goto destroy_pm_clk;
163 
164 	lpass_regmap_config.name = "top_cc";
165 	desc = &lpass_cc_top_sc7280_desc;
166 
167 	ret = qcom_cc_probe_by_index(pdev, 1, desc);
168 	if (ret)
169 		goto destroy_pm_clk;
170 
171 	lpass_regmap_config.name = "cc";
172 	desc = &lpass_cc_sc7280_desc;
173 
174 	ret = qcom_cc_probe_by_index(pdev, 2, desc);
175 	if (ret)
176 		goto destroy_pm_clk;
177 
178 	return 0;
179 
180 destroy_pm_clk:
181 	pm_clk_destroy(&pdev->dev);
182 
183 disable_pm_runtime:
184 	pm_runtime_disable(&pdev->dev);
185 
186 	return ret;
187 }
188 
189 static const struct of_device_id lpass_cc_sc7280_match_table[] = {
190 	{ .compatible = "qcom,sc7280-lpasscc" },
191 	{ }
192 };
193 MODULE_DEVICE_TABLE(of, lpass_cc_sc7280_match_table);
194 
195 static struct platform_driver lpass_cc_sc7280_driver = {
196 	.probe		= lpass_cc_sc7280_probe,
197 	.driver		= {
198 		.name	= "sc7280-lpasscc",
199 		.of_match_table = lpass_cc_sc7280_match_table,
200 	},
201 };
202 
203 static int __init lpass_cc_sc7280_init(void)
204 {
205 	return platform_driver_register(&lpass_cc_sc7280_driver);
206 }
207 subsys_initcall(lpass_cc_sc7280_init);
208 
209 static void __exit lpass_cc_sc7280_exit(void)
210 {
211 	platform_driver_unregister(&lpass_cc_sc7280_driver);
212 }
213 module_exit(lpass_cc_sc7280_exit);
214 
215 MODULE_DESCRIPTION("QTI LPASS_CC SC7280 Driver");
216 MODULE_LICENSE("GPL v2");
217