1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,sm8550-gpucc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "clk-regmap-divider.h" 18 #include "common.h" 19 #include "gdsc.h" 20 #include "reset.h" 21 22 enum { 23 DT_BI_TCXO, 24 DT_GPLL0_OUT_MAIN, 25 DT_GPLL0_OUT_MAIN_DIV, 26 }; 27 28 enum { 29 P_BI_TCXO, 30 P_GPLL0_OUT_MAIN, 31 P_GPLL0_OUT_MAIN_DIV, 32 P_GPU_CC_PLL0_OUT_MAIN, 33 P_GPU_CC_PLL1_OUT_MAIN, 34 }; 35 36 static const struct pll_vco lucid_ole_vco[] = { 37 { 249600000, 2300000000, 0 }, 38 }; 39 40 static const struct alpha_pll_config gpu_cc_pll0_config = { 41 /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */ 42 .l = 0x4444000d, 43 .alpha = 0x0, 44 .config_ctl_val = 0x20485699, 45 .config_ctl_hi_val = 0x00182261, 46 .config_ctl_hi1_val = 0x82aa299c, 47 .test_ctl_val = 0x00000000, 48 .test_ctl_hi_val = 0x00000003, 49 .test_ctl_hi1_val = 0x00009000, 50 .test_ctl_hi2_val = 0x00000034, 51 .user_ctl_val = 0x00000000, 52 .user_ctl_hi_val = 0x00000005, 53 }; 54 55 static struct clk_alpha_pll gpu_cc_pll0 = { 56 .offset = 0x0, 57 .vco_table = lucid_ole_vco, 58 .num_vco = ARRAY_SIZE(lucid_ole_vco), 59 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 60 .clkr = { 61 .hw.init = &(const struct clk_init_data) { 62 .name = "gpu_cc_pll0", 63 .parent_data = &(const struct clk_parent_data) { 64 .index = DT_BI_TCXO, 65 }, 66 .num_parents = 1, 67 .ops = &clk_alpha_pll_lucid_evo_ops, 68 }, 69 }, 70 }; 71 72 static const struct alpha_pll_config gpu_cc_pll1_config = { 73 /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */ 74 .l = 0x44440016, 75 .alpha = 0xeaaa, 76 .config_ctl_val = 0x20485699, 77 .config_ctl_hi_val = 0x00182261, 78 .config_ctl_hi1_val = 0x82aa299c, 79 .test_ctl_val = 0x00000000, 80 .test_ctl_hi_val = 0x00000003, 81 .test_ctl_hi1_val = 0x00009000, 82 .test_ctl_hi2_val = 0x00000034, 83 .user_ctl_val = 0x00000000, 84 .user_ctl_hi_val = 0x00000005, 85 }; 86 87 static struct clk_alpha_pll gpu_cc_pll1 = { 88 .offset = 0x1000, 89 .vco_table = lucid_ole_vco, 90 .num_vco = ARRAY_SIZE(lucid_ole_vco), 91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 92 .clkr = { 93 .hw.init = &(const struct clk_init_data) { 94 .name = "gpu_cc_pll1", 95 .parent_data = &(const struct clk_parent_data) { 96 .index = DT_BI_TCXO, 97 }, 98 .num_parents = 1, 99 .ops = &clk_alpha_pll_lucid_evo_ops, 100 }, 101 }, 102 }; 103 104 static const struct parent_map gpu_cc_parent_map_0[] = { 105 { P_BI_TCXO, 0 }, 106 { P_GPLL0_OUT_MAIN, 5 }, 107 { P_GPLL0_OUT_MAIN_DIV, 6 }, 108 }; 109 110 static const struct clk_parent_data gpu_cc_parent_data_0[] = { 111 { .index = DT_BI_TCXO }, 112 { .index = DT_GPLL0_OUT_MAIN }, 113 { .index = DT_GPLL0_OUT_MAIN_DIV }, 114 }; 115 116 static const struct parent_map gpu_cc_parent_map_1[] = { 117 { P_BI_TCXO, 0 }, 118 { P_GPU_CC_PLL0_OUT_MAIN, 1 }, 119 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 120 { P_GPLL0_OUT_MAIN, 5 }, 121 { P_GPLL0_OUT_MAIN_DIV, 6 }, 122 }; 123 124 static const struct clk_parent_data gpu_cc_parent_data_1[] = { 125 { .index = DT_BI_TCXO }, 126 { .hw = &gpu_cc_pll0.clkr.hw }, 127 { .hw = &gpu_cc_pll1.clkr.hw }, 128 { .index = DT_GPLL0_OUT_MAIN }, 129 { .index = DT_GPLL0_OUT_MAIN_DIV }, 130 }; 131 132 static const struct parent_map gpu_cc_parent_map_2[] = { 133 { P_BI_TCXO, 0 }, 134 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 135 { P_GPLL0_OUT_MAIN, 5 }, 136 { P_GPLL0_OUT_MAIN_DIV, 6 }, 137 }; 138 139 static const struct clk_parent_data gpu_cc_parent_data_2[] = { 140 { .index = DT_BI_TCXO }, 141 { .hw = &gpu_cc_pll1.clkr.hw }, 142 { .index = DT_GPLL0_OUT_MAIN }, 143 { .index = DT_GPLL0_OUT_MAIN_DIV }, 144 }; 145 146 static const struct parent_map gpu_cc_parent_map_3[] = { 147 { P_BI_TCXO, 0 }, 148 }; 149 150 static const struct clk_parent_data gpu_cc_parent_data_3[] = { 151 { .index = DT_BI_TCXO }, 152 }; 153 154 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { 155 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 156 { } 157 }; 158 159 static struct clk_rcg2 gpu_cc_ff_clk_src = { 160 .cmd_rcgr = 0x9474, 161 .mnd_width = 0, 162 .hid_width = 5, 163 .parent_map = gpu_cc_parent_map_0, 164 .freq_tbl = ftbl_gpu_cc_ff_clk_src, 165 .clkr.hw.init = &(const struct clk_init_data) { 166 .name = "gpu_cc_ff_clk_src", 167 .parent_data = gpu_cc_parent_data_0, 168 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 169 .flags = CLK_SET_RATE_PARENT, 170 .ops = &clk_rcg2_shared_ops, 171 }, 172 }; 173 174 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 175 F(19200000, P_BI_TCXO, 1, 0, 0), 176 F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), 177 F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), 178 { } 179 }; 180 181 static struct clk_rcg2 gpu_cc_gmu_clk_src = { 182 .cmd_rcgr = 0x9318, 183 .mnd_width = 0, 184 .hid_width = 5, 185 .parent_map = gpu_cc_parent_map_1, 186 .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 187 .clkr.hw.init = &(const struct clk_init_data) { 188 .name = "gpu_cc_gmu_clk_src", 189 .parent_data = gpu_cc_parent_data_1, 190 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), 191 .flags = CLK_SET_RATE_PARENT, 192 .ops = &clk_rcg2_shared_ops, 193 }, 194 }; 195 196 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { 197 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 198 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 199 F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), 200 { } 201 }; 202 203 static struct clk_rcg2 gpu_cc_hub_clk_src = { 204 .cmd_rcgr = 0x93ec, 205 .mnd_width = 0, 206 .hid_width = 5, 207 .parent_map = gpu_cc_parent_map_2, 208 .freq_tbl = ftbl_gpu_cc_hub_clk_src, 209 .clkr.hw.init = &(const struct clk_init_data) { 210 .name = "gpu_cc_hub_clk_src", 211 .parent_data = gpu_cc_parent_data_2, 212 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), 213 .flags = CLK_SET_RATE_PARENT, 214 .ops = &clk_rcg2_shared_ops, 215 }, 216 }; 217 218 static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = { 219 F(19200000, P_BI_TCXO, 1, 0, 0), 220 { } 221 }; 222 223 static struct clk_rcg2 gpu_cc_xo_clk_src = { 224 .cmd_rcgr = 0x9010, 225 .mnd_width = 0, 226 .hid_width = 5, 227 .parent_map = gpu_cc_parent_map_3, 228 .freq_tbl = ftbl_gpu_cc_xo_clk_src, 229 .clkr.hw.init = &(const struct clk_init_data) { 230 .name = "gpu_cc_xo_clk_src", 231 .parent_data = gpu_cc_parent_data_3, 232 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3), 233 .flags = CLK_SET_RATE_PARENT, 234 .ops = &clk_rcg2_shared_ops, 235 }, 236 }; 237 238 static struct clk_regmap_div gpu_cc_demet_div_clk_src = { 239 .reg = 0x9054, 240 .shift = 0, 241 .width = 4, 242 .clkr.hw.init = &(const struct clk_init_data) { 243 .name = "gpu_cc_demet_div_clk_src", 244 .parent_hws = (const struct clk_hw*[]) { 245 &gpu_cc_xo_clk_src.clkr.hw, 246 }, 247 .num_parents = 1, 248 .flags = CLK_SET_RATE_PARENT, 249 .ops = &clk_regmap_div_ro_ops, 250 }, 251 }; 252 253 static struct clk_regmap_div gpu_cc_xo_div_clk_src = { 254 .reg = 0x9050, 255 .shift = 0, 256 .width = 4, 257 .clkr.hw.init = &(const struct clk_init_data) { 258 .name = "gpu_cc_xo_div_clk_src", 259 .parent_hws = (const struct clk_hw*[]) { 260 &gpu_cc_xo_clk_src.clkr.hw, 261 }, 262 .num_parents = 1, 263 .flags = CLK_SET_RATE_PARENT, 264 .ops = &clk_regmap_div_ro_ops, 265 }, 266 }; 267 268 static struct clk_branch gpu_cc_ahb_clk = { 269 .halt_reg = 0x911c, 270 .halt_check = BRANCH_HALT_DELAY, 271 .clkr = { 272 .enable_reg = 0x911c, 273 .enable_mask = BIT(0), 274 .hw.init = &(const struct clk_init_data) { 275 .name = "gpu_cc_ahb_clk", 276 .parent_hws = (const struct clk_hw*[]) { 277 &gpu_cc_hub_clk_src.clkr.hw, 278 }, 279 .num_parents = 1, 280 .flags = CLK_SET_RATE_PARENT, 281 .ops = &clk_branch2_ops, 282 }, 283 }, 284 }; 285 286 static struct clk_branch gpu_cc_crc_ahb_clk = { 287 .halt_reg = 0x9120, 288 .halt_check = BRANCH_HALT_VOTED, 289 .clkr = { 290 .enable_reg = 0x9120, 291 .enable_mask = BIT(0), 292 .hw.init = &(const struct clk_init_data) { 293 .name = "gpu_cc_crc_ahb_clk", 294 .parent_hws = (const struct clk_hw*[]) { 295 &gpu_cc_hub_clk_src.clkr.hw, 296 }, 297 .num_parents = 1, 298 .flags = CLK_SET_RATE_PARENT, 299 .ops = &clk_branch2_ops, 300 }, 301 }, 302 }; 303 304 static struct clk_branch gpu_cc_cx_ff_clk = { 305 .halt_reg = 0x914c, 306 .halt_check = BRANCH_HALT, 307 .clkr = { 308 .enable_reg = 0x914c, 309 .enable_mask = BIT(0), 310 .hw.init = &(const struct clk_init_data) { 311 .name = "gpu_cc_cx_ff_clk", 312 .parent_hws = (const struct clk_hw*[]) { 313 &gpu_cc_ff_clk_src.clkr.hw, 314 }, 315 .num_parents = 1, 316 .flags = CLK_SET_RATE_PARENT, 317 .ops = &clk_branch2_ops, 318 }, 319 }, 320 }; 321 322 static struct clk_branch gpu_cc_cx_gmu_clk = { 323 .halt_reg = 0x913c, 324 .halt_check = BRANCH_HALT_VOTED, 325 .clkr = { 326 .enable_reg = 0x913c, 327 .enable_mask = BIT(0), 328 .hw.init = &(const struct clk_init_data) { 329 .name = "gpu_cc_cx_gmu_clk", 330 .parent_hws = (const struct clk_hw*[]) { 331 &gpu_cc_gmu_clk_src.clkr.hw, 332 }, 333 .num_parents = 1, 334 .flags = CLK_SET_RATE_PARENT, 335 .ops = &clk_branch2_aon_ops, 336 }, 337 }, 338 }; 339 340 static struct clk_branch gpu_cc_cxo_clk = { 341 .halt_reg = 0x9144, 342 .halt_check = BRANCH_HALT, 343 .clkr = { 344 .enable_reg = 0x9144, 345 .enable_mask = BIT(0), 346 .hw.init = &(const struct clk_init_data) { 347 .name = "gpu_cc_cxo_clk", 348 .parent_hws = (const struct clk_hw*[]) { 349 &gpu_cc_xo_clk_src.clkr.hw, 350 }, 351 .num_parents = 1, 352 .flags = CLK_SET_RATE_PARENT, 353 .ops = &clk_branch2_ops, 354 }, 355 }, 356 }; 357 358 static struct clk_branch gpu_cc_freq_measure_clk = { 359 .halt_reg = 0x9008, 360 .halt_check = BRANCH_HALT, 361 .clkr = { 362 .enable_reg = 0x9008, 363 .enable_mask = BIT(0), 364 .hw.init = &(const struct clk_init_data) { 365 .name = "gpu_cc_freq_measure_clk", 366 .parent_hws = (const struct clk_hw*[]) { 367 &gpu_cc_xo_div_clk_src.clkr.hw, 368 }, 369 .num_parents = 1, 370 .flags = CLK_SET_RATE_PARENT, 371 .ops = &clk_branch2_ops, 372 }, 373 }, 374 }; 375 376 static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { 377 .halt_reg = 0x7000, 378 .halt_check = BRANCH_HALT_VOTED, 379 .clkr = { 380 .enable_reg = 0x7000, 381 .enable_mask = BIT(0), 382 .hw.init = &(const struct clk_init_data) { 383 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", 384 .ops = &clk_branch2_ops, 385 }, 386 }, 387 }; 388 389 static struct clk_branch gpu_cc_hub_aon_clk = { 390 .halt_reg = 0x93e8, 391 .halt_check = BRANCH_HALT, 392 .clkr = { 393 .enable_reg = 0x93e8, 394 .enable_mask = BIT(0), 395 .hw.init = &(const struct clk_init_data) { 396 .name = "gpu_cc_hub_aon_clk", 397 .parent_hws = (const struct clk_hw*[]) { 398 &gpu_cc_hub_clk_src.clkr.hw, 399 }, 400 .num_parents = 1, 401 .flags = CLK_SET_RATE_PARENT, 402 .ops = &clk_branch2_aon_ops, 403 }, 404 }, 405 }; 406 407 static struct clk_branch gpu_cc_hub_cx_int_clk = { 408 .halt_reg = 0x9148, 409 .halt_check = BRANCH_HALT_VOTED, 410 .clkr = { 411 .enable_reg = 0x9148, 412 .enable_mask = BIT(0), 413 .hw.init = &(const struct clk_init_data) { 414 .name = "gpu_cc_hub_cx_int_clk", 415 .parent_hws = (const struct clk_hw*[]) { 416 &gpu_cc_hub_clk_src.clkr.hw, 417 }, 418 .num_parents = 1, 419 .flags = CLK_SET_RATE_PARENT, 420 .ops = &clk_branch2_aon_ops, 421 }, 422 }, 423 }; 424 425 static struct clk_branch gpu_cc_memnoc_gfx_clk = { 426 .halt_reg = 0x9150, 427 .halt_check = BRANCH_HALT_VOTED, 428 .clkr = { 429 .enable_reg = 0x9150, 430 .enable_mask = BIT(0), 431 .hw.init = &(const struct clk_init_data) { 432 .name = "gpu_cc_memnoc_gfx_clk", 433 .ops = &clk_branch2_ops, 434 }, 435 }, 436 }; 437 438 static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { 439 .halt_reg = 0x9288, 440 .halt_check = BRANCH_HALT, 441 .clkr = { 442 .enable_reg = 0x9288, 443 .enable_mask = BIT(0), 444 .hw.init = &(const struct clk_init_data) { 445 .name = "gpu_cc_mnd1x_0_gfx3d_clk", 446 .ops = &clk_branch2_ops, 447 }, 448 }, 449 }; 450 451 static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { 452 .halt_reg = 0x928c, 453 .halt_check = BRANCH_HALT, 454 .clkr = { 455 .enable_reg = 0x928c, 456 .enable_mask = BIT(0), 457 .hw.init = &(const struct clk_init_data) { 458 .name = "gpu_cc_mnd1x_1_gfx3d_clk", 459 .ops = &clk_branch2_ops, 460 }, 461 }, 462 }; 463 464 static struct clk_branch gpu_cc_sleep_clk = { 465 .halt_reg = 0x9134, 466 .halt_check = BRANCH_HALT_VOTED, 467 .clkr = { 468 .enable_reg = 0x9134, 469 .enable_mask = BIT(0), 470 .hw.init = &(const struct clk_init_data) { 471 .name = "gpu_cc_sleep_clk", 472 .ops = &clk_branch2_ops, 473 }, 474 }, 475 }; 476 477 static struct gdsc gpu_cc_cx_gdsc = { 478 .gdscr = 0x9108, 479 .gds_hw_ctrl = 0x953c, 480 .en_rest_wait_val = 0x2, 481 .en_few_wait_val = 0x2, 482 .clk_dis_wait_val = 0xf, 483 .pd = { 484 .name = "gpu_cc_cx_gdsc", 485 }, 486 .pwrsts = PWRSTS_OFF_ON, 487 .flags = RETAIN_FF_ENABLE | VOTABLE, 488 }; 489 490 static struct gdsc gpu_cc_gx_gdsc = { 491 .gdscr = 0x905c, 492 .clamp_io_ctrl = 0x9504, 493 .en_rest_wait_val = 0x2, 494 .en_few_wait_val = 0x2, 495 .clk_dis_wait_val = 0xf, 496 .pd = { 497 .name = "gpu_cc_gx_gdsc", 498 .power_on = gdsc_gx_do_nothing_enable, 499 }, 500 .pwrsts = PWRSTS_OFF_ON, 501 .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 502 }; 503 504 static struct clk_regmap *gpu_cc_sm8550_clocks[] = { 505 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, 506 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, 507 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, 508 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 509 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 510 [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr, 511 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, 512 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, 513 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 514 [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, 515 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, 516 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, 517 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, 518 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, 519 [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, 520 [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, 521 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, 522 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 523 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, 524 [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr, 525 [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr, 526 }; 527 528 static struct gdsc *gpu_cc_sm8550_gdscs[] = { 529 [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc, 530 [GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc, 531 }; 532 533 static const struct qcom_reset_map gpu_cc_sm8550_resets[] = { 534 [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, 535 [GPUCC_GPU_CC_CX_BCR] = { 0x9104 }, 536 [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, 537 [GPUCC_GPU_CC_FF_BCR] = { 0x9470 }, 538 [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, 539 [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 }, 540 [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, 541 [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, 542 }; 543 544 static const struct regmap_config gpu_cc_sm8550_regmap_config = { 545 .reg_bits = 32, 546 .reg_stride = 4, 547 .val_bits = 32, 548 .max_register = 0x9988, 549 .fast_io = true, 550 }; 551 552 static const struct qcom_cc_desc gpu_cc_sm8550_desc = { 553 .config = &gpu_cc_sm8550_regmap_config, 554 .clks = gpu_cc_sm8550_clocks, 555 .num_clks = ARRAY_SIZE(gpu_cc_sm8550_clocks), 556 .resets = gpu_cc_sm8550_resets, 557 .num_resets = ARRAY_SIZE(gpu_cc_sm8550_resets), 558 .gdscs = gpu_cc_sm8550_gdscs, 559 .num_gdscs = ARRAY_SIZE(gpu_cc_sm8550_gdscs), 560 }; 561 562 static const struct of_device_id gpu_cc_sm8550_match_table[] = { 563 { .compatible = "qcom,sm8550-gpucc" }, 564 { } 565 }; 566 MODULE_DEVICE_TABLE(of, gpu_cc_sm8550_match_table); 567 568 static int gpu_cc_sm8550_probe(struct platform_device *pdev) 569 { 570 struct regmap *regmap; 571 572 regmap = qcom_cc_map(pdev, &gpu_cc_sm8550_desc); 573 if (IS_ERR(regmap)) 574 return PTR_ERR(regmap); 575 576 clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 577 clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 578 579 /* 580 * Keep clocks always enabled: 581 * gpu_cc_cxo_aon_clk 582 * gpu_cc_demet_clk 583 */ 584 regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0)); 585 regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0)); 586 587 return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap); 588 } 589 590 static struct platform_driver gpu_cc_sm8550_driver = { 591 .probe = gpu_cc_sm8550_probe, 592 .driver = { 593 .name = "gpu_cc-sm8550", 594 .of_match_table = gpu_cc_sm8550_match_table, 595 }, 596 }; 597 598 static int __init gpu_cc_sm8550_init(void) 599 { 600 return platform_driver_register(&gpu_cc_sm8550_driver); 601 } 602 subsys_initcall(gpu_cc_sm8550_init); 603 604 static void __exit gpu_cc_sm8550_exit(void) 605 { 606 platform_driver_unregister(&gpu_cc_sm8550_driver); 607 } 608 module_exit(gpu_cc_sm8550_exit); 609 610 MODULE_DESCRIPTION("QTI GPUCC SM8550 Driver"); 611 MODULE_LICENSE("GPL"); 612