1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h> 12 #include <dt-bindings/reset/qcom,sm8450-gpucc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "clk-regmap-phy-mux.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 DT_BI_TCXO, 26 DT_GPLL0_OUT_MAIN, 27 DT_GPLL0_OUT_MAIN_DIV, 28 }; 29 30 enum { 31 P_BI_TCXO, 32 P_GPLL0_OUT_MAIN, 33 P_GPLL0_OUT_MAIN_DIV, 34 P_GPU_CC_PLL0_OUT_MAIN, 35 P_GPU_CC_PLL1_OUT_MAIN, 36 }; 37 38 static struct pll_vco lucid_evo_vco[] = { 39 { 249600000, 2000000000, 0 }, 40 }; 41 42 static struct alpha_pll_config gpu_cc_pll0_config = { 43 .l = 0x1d, 44 .alpha = 0xb000, 45 .config_ctl_val = 0x20485699, 46 .config_ctl_hi_val = 0x00182261, 47 .config_ctl_hi1_val = 0x32aa299c, 48 .user_ctl_val = 0x00000000, 49 .user_ctl_hi_val = 0x00000805, 50 }; 51 52 static struct clk_alpha_pll gpu_cc_pll0 = { 53 .offset = 0x0, 54 .vco_table = lucid_evo_vco, 55 .num_vco = ARRAY_SIZE(lucid_evo_vco), 56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 57 .clkr = { 58 .hw.init = &(struct clk_init_data){ 59 .name = "gpu_cc_pll0", 60 .parent_data = &(const struct clk_parent_data){ 61 .index = DT_BI_TCXO, 62 }, 63 .num_parents = 1, 64 .ops = &clk_alpha_pll_lucid_evo_ops, 65 }, 66 }, 67 }; 68 69 static struct alpha_pll_config gpu_cc_pll1_config = { 70 .l = 0x34, 71 .alpha = 0x1555, 72 .config_ctl_val = 0x20485699, 73 .config_ctl_hi_val = 0x00182261, 74 .config_ctl_hi1_val = 0x32aa299c, 75 .user_ctl_val = 0x00000000, 76 .user_ctl_hi_val = 0x00000805, 77 }; 78 79 static struct clk_alpha_pll gpu_cc_pll1 = { 80 .offset = 0x1000, 81 .vco_table = lucid_evo_vco, 82 .num_vco = ARRAY_SIZE(lucid_evo_vco), 83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 84 .clkr = { 85 .hw.init = &(struct clk_init_data){ 86 .name = "gpu_cc_pll1", 87 .parent_data = &(const struct clk_parent_data){ 88 .index = DT_BI_TCXO, 89 }, 90 .num_parents = 1, 91 .ops = &clk_alpha_pll_lucid_evo_ops, 92 }, 93 }, 94 }; 95 96 static const struct parent_map gpu_cc_parent_map_0[] = { 97 { P_BI_TCXO, 0 }, 98 { P_GPLL0_OUT_MAIN, 5 }, 99 { P_GPLL0_OUT_MAIN_DIV, 6 }, 100 }; 101 102 static const struct clk_parent_data gpu_cc_parent_data_0[] = { 103 { .index = DT_BI_TCXO }, 104 { .index = DT_GPLL0_OUT_MAIN }, 105 { .index = DT_GPLL0_OUT_MAIN_DIV }, 106 }; 107 108 static const struct parent_map gpu_cc_parent_map_1[] = { 109 { P_BI_TCXO, 0 }, 110 { P_GPU_CC_PLL0_OUT_MAIN, 1 }, 111 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 112 { P_GPLL0_OUT_MAIN, 5 }, 113 { P_GPLL0_OUT_MAIN_DIV, 6 }, 114 }; 115 116 static const struct clk_parent_data gpu_cc_parent_data_1[] = { 117 { .index = DT_BI_TCXO }, 118 { .hw = &gpu_cc_pll0.clkr.hw }, 119 { .hw = &gpu_cc_pll1.clkr.hw }, 120 { .index = DT_GPLL0_OUT_MAIN }, 121 { .index = DT_GPLL0_OUT_MAIN_DIV }, 122 }; 123 124 static const struct parent_map gpu_cc_parent_map_2[] = { 125 { P_BI_TCXO, 0 }, 126 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 127 { P_GPLL0_OUT_MAIN, 5 }, 128 { P_GPLL0_OUT_MAIN_DIV, 6 }, 129 }; 130 131 static const struct clk_parent_data gpu_cc_parent_data_2[] = { 132 { .index = DT_BI_TCXO }, 133 { .hw = &gpu_cc_pll1.clkr.hw }, 134 { .index = DT_GPLL0_OUT_MAIN }, 135 { .index = DT_GPLL0_OUT_MAIN_DIV }, 136 }; 137 138 static const struct parent_map gpu_cc_parent_map_3[] = { 139 { P_BI_TCXO, 0 }, 140 }; 141 142 static const struct clk_parent_data gpu_cc_parent_data_3[] = { 143 { .index = DT_BI_TCXO }, 144 }; 145 146 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { 147 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), 148 { } 149 }; 150 151 static struct clk_rcg2 gpu_cc_ff_clk_src = { 152 .cmd_rcgr = 0x9474, 153 .mnd_width = 0, 154 .hid_width = 5, 155 .parent_map = gpu_cc_parent_map_0, 156 .freq_tbl = ftbl_gpu_cc_ff_clk_src, 157 .hw_clk_ctrl = true, 158 .clkr.hw.init = &(struct clk_init_data){ 159 .name = "gpu_cc_ff_clk_src", 160 .parent_data = gpu_cc_parent_data_0, 161 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 162 .flags = CLK_SET_RATE_PARENT, 163 .ops = &clk_rcg2_shared_ops, 164 }, 165 }; 166 167 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 168 F(19200000, P_BI_TCXO, 1, 0, 0), 169 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), 170 F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), 171 { } 172 }; 173 174 static struct clk_rcg2 gpu_cc_gmu_clk_src = { 175 .cmd_rcgr = 0x9318, 176 .mnd_width = 0, 177 .hid_width = 5, 178 .parent_map = gpu_cc_parent_map_1, 179 .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 180 .hw_clk_ctrl = true, 181 .clkr.hw.init = &(struct clk_init_data){ 182 .name = "gpu_cc_gmu_clk_src", 183 .parent_data = gpu_cc_parent_data_1, 184 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), 185 .flags = CLK_SET_RATE_PARENT, 186 .ops = &clk_rcg2_shared_ops, 187 }, 188 }; 189 190 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { 191 F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), 192 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 193 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 194 { } 195 }; 196 197 static struct clk_rcg2 gpu_cc_hub_clk_src = { 198 .cmd_rcgr = 0x93ec, 199 .mnd_width = 0, 200 .hid_width = 5, 201 .parent_map = gpu_cc_parent_map_2, 202 .freq_tbl = ftbl_gpu_cc_hub_clk_src, 203 .hw_clk_ctrl = true, 204 .clkr.hw.init = &(struct clk_init_data){ 205 .name = "gpu_cc_hub_clk_src", 206 .parent_data = gpu_cc_parent_data_2, 207 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), 208 .flags = CLK_SET_RATE_PARENT, 209 .ops = &clk_rcg2_shared_ops, 210 }, 211 }; 212 213 static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = { 214 F(19200000, P_BI_TCXO, 1, 0, 0), 215 { } 216 }; 217 218 static struct clk_rcg2 gpu_cc_xo_clk_src = { 219 .cmd_rcgr = 0x9010, 220 .mnd_width = 0, 221 .hid_width = 5, 222 .parent_map = gpu_cc_parent_map_3, 223 .freq_tbl = ftbl_gpu_cc_xo_clk_src, 224 .hw_clk_ctrl = true, 225 .clkr.hw.init = &(struct clk_init_data){ 226 .name = "gpu_cc_xo_clk_src", 227 .parent_data = gpu_cc_parent_data_3, 228 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3), 229 .flags = CLK_SET_RATE_PARENT, 230 .ops = &clk_rcg2_shared_ops, 231 }, 232 }; 233 234 static struct clk_regmap_div gpu_cc_demet_div_clk_src = { 235 .reg = 0x9054, 236 .shift = 0, 237 .width = 4, 238 .clkr.hw.init = &(struct clk_init_data) { 239 .name = "gpu_cc_demet_div_clk_src", 240 .parent_hws = (const struct clk_hw*[]){ 241 &gpu_cc_xo_clk_src.clkr.hw, 242 }, 243 .num_parents = 1, 244 .flags = CLK_SET_RATE_PARENT, 245 .ops = &clk_regmap_div_ro_ops, 246 }, 247 }; 248 249 static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { 250 .reg = 0x9430, 251 .shift = 0, 252 .width = 4, 253 .clkr.hw.init = &(struct clk_init_data) { 254 .name = "gpu_cc_hub_ahb_div_clk_src", 255 .parent_hws = (const struct clk_hw*[]){ 256 &gpu_cc_hub_clk_src.clkr.hw, 257 }, 258 .num_parents = 1, 259 .flags = CLK_SET_RATE_PARENT, 260 .ops = &clk_regmap_div_ro_ops, 261 }, 262 }; 263 264 static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { 265 .reg = 0x942c, 266 .shift = 0, 267 .width = 4, 268 .clkr.hw.init = &(struct clk_init_data) { 269 .name = "gpu_cc_hub_cx_int_div_clk_src", 270 .parent_hws = (const struct clk_hw*[]){ 271 &gpu_cc_hub_clk_src.clkr.hw, 272 }, 273 .num_parents = 1, 274 .flags = CLK_SET_RATE_PARENT, 275 .ops = &clk_regmap_div_ro_ops, 276 }, 277 }; 278 279 static struct clk_regmap_div gpu_cc_xo_div_clk_src = { 280 .reg = 0x9050, 281 .shift = 0, 282 .width = 4, 283 .clkr.hw.init = &(struct clk_init_data) { 284 .name = "gpu_cc_xo_div_clk_src", 285 .parent_hws = (const struct clk_hw*[]){ 286 &gpu_cc_xo_clk_src.clkr.hw, 287 }, 288 .num_parents = 1, 289 .flags = CLK_SET_RATE_PARENT, 290 .ops = &clk_regmap_div_ro_ops, 291 }, 292 }; 293 294 static struct clk_branch gpu_cc_ahb_clk = { 295 .halt_reg = 0x911c, 296 .halt_check = BRANCH_HALT_DELAY, 297 .clkr = { 298 .enable_reg = 0x911c, 299 .enable_mask = BIT(0), 300 .hw.init = &(struct clk_init_data){ 301 .name = "gpu_cc_ahb_clk", 302 .parent_hws = (const struct clk_hw*[]) { 303 &gpu_cc_hub_ahb_div_clk_src.clkr.hw, 304 }, 305 .num_parents = 1, 306 .flags = CLK_SET_RATE_PARENT, 307 .ops = &clk_branch2_ops, 308 }, 309 }, 310 }; 311 312 static struct clk_branch gpu_cc_crc_ahb_clk = { 313 .halt_reg = 0x9120, 314 .halt_check = BRANCH_HALT_VOTED, 315 .clkr = { 316 .enable_reg = 0x9120, 317 .enable_mask = BIT(0), 318 .hw.init = &(struct clk_init_data){ 319 .name = "gpu_cc_crc_ahb_clk", 320 .parent_hws = (const struct clk_hw*[]) { 321 &gpu_cc_hub_ahb_div_clk_src.clkr.hw, 322 }, 323 .num_parents = 1, 324 .flags = CLK_SET_RATE_PARENT, 325 .ops = &clk_branch2_ops, 326 }, 327 }, 328 }; 329 330 static struct clk_branch gpu_cc_cx_apb_clk = { 331 .halt_reg = 0x912c, 332 .halt_check = BRANCH_HALT_VOTED, 333 .clkr = { 334 .enable_reg = 0x912c, 335 .enable_mask = BIT(0), 336 .hw.init = &(struct clk_init_data){ 337 .name = "gpu_cc_cx_apb_clk", 338 .ops = &clk_branch2_ops, 339 }, 340 }, 341 }; 342 343 static struct clk_branch gpu_cc_cx_ff_clk = { 344 .halt_reg = 0x914c, 345 .halt_check = BRANCH_HALT, 346 .clkr = { 347 .enable_reg = 0x914c, 348 .enable_mask = BIT(0), 349 .hw.init = &(struct clk_init_data){ 350 .name = "gpu_cc_cx_ff_clk", 351 .parent_hws = (const struct clk_hw*[]) { 352 &gpu_cc_ff_clk_src.clkr.hw, 353 }, 354 .num_parents = 1, 355 .flags = CLK_SET_RATE_PARENT, 356 .ops = &clk_branch2_ops, 357 }, 358 }, 359 }; 360 361 static struct clk_branch gpu_cc_cx_gmu_clk = { 362 .halt_reg = 0x913c, 363 .halt_check = BRANCH_HALT, 364 .clkr = { 365 .enable_reg = 0x913c, 366 .enable_mask = BIT(0), 367 .hw.init = &(struct clk_init_data){ 368 .name = "gpu_cc_cx_gmu_clk", 369 .parent_hws = (const struct clk_hw*[]) { 370 &gpu_cc_gmu_clk_src.clkr.hw, 371 }, 372 .num_parents = 1, 373 .flags = CLK_SET_RATE_PARENT, 374 .ops = &clk_branch2_aon_ops, 375 }, 376 }, 377 }; 378 379 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { 380 .halt_reg = 0x9130, 381 .halt_check = BRANCH_HALT_VOTED, 382 .clkr = { 383 .enable_reg = 0x9130, 384 .enable_mask = BIT(0), 385 .hw.init = &(struct clk_init_data){ 386 .name = "gpu_cc_cx_snoc_dvm_clk", 387 .ops = &clk_branch2_ops, 388 }, 389 }, 390 }; 391 392 static struct clk_branch gpu_cc_cxo_aon_clk = { 393 .halt_reg = 0x9004, 394 .halt_check = BRANCH_HALT_VOTED, 395 .clkr = { 396 .enable_reg = 0x9004, 397 .enable_mask = BIT(0), 398 .hw.init = &(struct clk_init_data){ 399 .name = "gpu_cc_cxo_aon_clk", 400 .parent_hws = (const struct clk_hw*[]) { 401 &gpu_cc_xo_clk_src.clkr.hw, 402 }, 403 .num_parents = 1, 404 .flags = CLK_SET_RATE_PARENT, 405 .ops = &clk_branch2_ops, 406 }, 407 }, 408 }; 409 410 static struct clk_branch gpu_cc_cxo_clk = { 411 .halt_reg = 0x9144, 412 .halt_check = BRANCH_HALT, 413 .clkr = { 414 .enable_reg = 0x9144, 415 .enable_mask = BIT(0), 416 .hw.init = &(struct clk_init_data){ 417 .name = "gpu_cc_cxo_clk", 418 .parent_hws = (const struct clk_hw*[]) { 419 &gpu_cc_xo_clk_src.clkr.hw, 420 }, 421 .num_parents = 1, 422 .flags = CLK_SET_RATE_PARENT, 423 .ops = &clk_branch2_ops, 424 }, 425 }, 426 }; 427 428 static struct clk_branch gpu_cc_demet_clk = { 429 .halt_reg = 0x900c, 430 .halt_check = BRANCH_HALT, 431 .clkr = { 432 .enable_reg = 0x900c, 433 .enable_mask = BIT(0), 434 .hw.init = &(struct clk_init_data){ 435 .name = "gpu_cc_demet_clk", 436 .parent_hws = (const struct clk_hw*[]) { 437 &gpu_cc_demet_div_clk_src.clkr.hw, 438 }, 439 .num_parents = 1, 440 .flags = CLK_SET_RATE_PARENT, 441 .ops = &clk_branch2_aon_ops, 442 }, 443 }, 444 }; 445 446 static struct clk_branch gpu_cc_freq_measure_clk = { 447 .halt_reg = 0x9008, 448 .halt_check = BRANCH_HALT, 449 .clkr = { 450 .enable_reg = 0x9008, 451 .enable_mask = BIT(0), 452 .hw.init = &(struct clk_init_data){ 453 .name = "gpu_cc_freq_measure_clk", 454 .parent_hws = (const struct clk_hw*[]) { 455 &gpu_cc_xo_div_clk_src.clkr.hw, 456 }, 457 .num_parents = 1, 458 .flags = CLK_SET_RATE_PARENT, 459 .ops = &clk_branch2_ops, 460 }, 461 }, 462 }; 463 464 static struct clk_branch gpu_cc_gx_ff_clk = { 465 .halt_reg = 0x90c0, 466 .halt_check = BRANCH_HALT, 467 .clkr = { 468 .enable_reg = 0x90c0, 469 .enable_mask = BIT(0), 470 .hw.init = &(struct clk_init_data){ 471 .name = "gpu_cc_gx_ff_clk", 472 .parent_hws = (const struct clk_hw*[]) { 473 &gpu_cc_ff_clk_src.clkr.hw, 474 }, 475 .num_parents = 1, 476 .flags = CLK_SET_RATE_PARENT, 477 .ops = &clk_branch2_ops, 478 }, 479 }, 480 }; 481 482 static struct clk_branch gpu_cc_gx_gfx3d_clk = { 483 .halt_reg = 0x90a8, 484 .halt_check = BRANCH_HALT, 485 .clkr = { 486 .enable_reg = 0x90a8, 487 .enable_mask = BIT(0), 488 .hw.init = &(struct clk_init_data){ 489 .name = "gpu_cc_gx_gfx3d_clk", 490 .ops = &clk_branch2_ops, 491 }, 492 }, 493 }; 494 495 static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = { 496 .halt_reg = 0x90c8, 497 .halt_check = BRANCH_HALT, 498 .clkr = { 499 .enable_reg = 0x90c8, 500 .enable_mask = BIT(0), 501 .hw.init = &(struct clk_init_data){ 502 .name = "gpu_cc_gx_gfx3d_rdvm_clk", 503 .ops = &clk_branch2_ops, 504 }, 505 }, 506 }; 507 508 static struct clk_branch gpu_cc_gx_gmu_clk = { 509 .halt_reg = 0x90bc, 510 .halt_check = BRANCH_HALT, 511 .clkr = { 512 .enable_reg = 0x90bc, 513 .enable_mask = BIT(0), 514 .hw.init = &(struct clk_init_data){ 515 .name = "gpu_cc_gx_gmu_clk", 516 .parent_hws = (const struct clk_hw*[]) { 517 &gpu_cc_gmu_clk_src.clkr.hw, 518 }, 519 .num_parents = 1, 520 .flags = CLK_SET_RATE_PARENT, 521 .ops = &clk_branch2_ops, 522 }, 523 }, 524 }; 525 526 static struct clk_branch gpu_cc_gx_vsense_clk = { 527 .halt_reg = 0x90b0, 528 .halt_check = BRANCH_HALT_VOTED, 529 .clkr = { 530 .enable_reg = 0x90b0, 531 .enable_mask = BIT(0), 532 .hw.init = &(struct clk_init_data){ 533 .name = "gpu_cc_gx_vsense_clk", 534 .ops = &clk_branch2_ops, 535 }, 536 }, 537 }; 538 539 static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { 540 .halt_reg = 0x7000, 541 .halt_check = BRANCH_HALT_VOTED, 542 .clkr = { 543 .enable_reg = 0x7000, 544 .enable_mask = BIT(0), 545 .hw.init = &(struct clk_init_data){ 546 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", 547 .ops = &clk_branch2_ops, 548 }, 549 }, 550 }; 551 552 static struct clk_branch gpu_cc_hub_aon_clk = { 553 .halt_reg = 0x93e8, 554 .halt_check = BRANCH_HALT, 555 .clkr = { 556 .enable_reg = 0x93e8, 557 .enable_mask = BIT(0), 558 .hw.init = &(struct clk_init_data){ 559 .name = "gpu_cc_hub_aon_clk", 560 .parent_hws = (const struct clk_hw*[]) { 561 &gpu_cc_hub_clk_src.clkr.hw, 562 }, 563 .num_parents = 1, 564 .flags = CLK_SET_RATE_PARENT, 565 .ops = &clk_branch2_aon_ops, 566 }, 567 }, 568 }; 569 570 static struct clk_branch gpu_cc_hub_cx_int_clk = { 571 .halt_reg = 0x9148, 572 .halt_check = BRANCH_HALT, 573 .clkr = { 574 .enable_reg = 0x9148, 575 .enable_mask = BIT(0), 576 .hw.init = &(struct clk_init_data){ 577 .name = "gpu_cc_hub_cx_int_clk", 578 .parent_hws = (const struct clk_hw*[]) { 579 &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, 580 }, 581 .num_parents = 1, 582 .flags = CLK_SET_RATE_PARENT, 583 .ops = &clk_branch2_aon_ops, 584 }, 585 }, 586 }; 587 588 static struct clk_branch gpu_cc_memnoc_gfx_clk = { 589 .halt_reg = 0x9150, 590 .halt_check = BRANCH_HALT, 591 .clkr = { 592 .enable_reg = 0x9150, 593 .enable_mask = BIT(0), 594 .hw.init = &(struct clk_init_data){ 595 .name = "gpu_cc_memnoc_gfx_clk", 596 .ops = &clk_branch2_ops, 597 }, 598 }, 599 }; 600 601 static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { 602 .halt_reg = 0x9288, 603 .halt_check = BRANCH_HALT, 604 .clkr = { 605 .enable_reg = 0x9288, 606 .enable_mask = BIT(0), 607 .hw.init = &(struct clk_init_data){ 608 .name = "gpu_cc_mnd1x_0_gfx3d_clk", 609 .ops = &clk_branch2_ops, 610 }, 611 }, 612 }; 613 614 static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { 615 .halt_reg = 0x928c, 616 .halt_check = BRANCH_HALT, 617 .clkr = { 618 .enable_reg = 0x928c, 619 .enable_mask = BIT(0), 620 .hw.init = &(struct clk_init_data){ 621 .name = "gpu_cc_mnd1x_1_gfx3d_clk", 622 .ops = &clk_branch2_ops, 623 }, 624 }, 625 }; 626 627 static struct clk_branch gpu_cc_sleep_clk = { 628 .halt_reg = 0x9134, 629 .halt_check = BRANCH_HALT_VOTED, 630 .clkr = { 631 .enable_reg = 0x9134, 632 .enable_mask = BIT(0), 633 .hw.init = &(struct clk_init_data){ 634 .name = "gpu_cc_sleep_clk", 635 .ops = &clk_branch2_ops, 636 }, 637 }, 638 }; 639 640 static struct gdsc gpu_cx_gdsc = { 641 .gdscr = 0x9108, 642 .gds_hw_ctrl = 0x953c, 643 .clk_dis_wait_val = 8, 644 .pd = { 645 .name = "gpu_cx_gdsc", 646 }, 647 .pwrsts = PWRSTS_OFF_ON, 648 .flags = VOTABLE | RETAIN_FF_ENABLE, 649 }; 650 651 static struct gdsc gpu_gx_gdsc = { 652 .gdscr = 0x905c, 653 .clamp_io_ctrl = 0x9504, 654 .resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR, 655 GPUCC_GPU_CC_ACD_BCR, 656 GPUCC_GPU_CC_GX_ACD_IROOT_BCR }, 657 .reset_count = 3, 658 .pd = { 659 .name = "gpu_gx_gdsc", 660 .power_on = gdsc_gx_do_nothing_enable, 661 }, 662 .pwrsts = PWRSTS_OFF_ON, 663 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR, 664 }; 665 666 static struct clk_regmap *gpu_cc_sm8450_clocks[] = { 667 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, 668 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, 669 [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, 670 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, 671 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 672 [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, 673 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, 674 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 675 [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, 676 [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr, 677 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, 678 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, 679 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 680 [GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr, 681 [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, 682 [GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr, 683 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, 684 [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, 685 [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, 686 [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, 687 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, 688 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, 689 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, 690 [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, 691 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, 692 [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, 693 [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, 694 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, 695 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 696 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, 697 [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr, 698 [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr, 699 }; 700 701 static const struct qcom_reset_map gpu_cc_sm8450_resets[] = { 702 [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, 703 [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, 704 [GPUCC_GPU_CC_CX_BCR] = { 0x9104 }, 705 [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, 706 [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, 707 [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, 708 [GPUCC_GPU_CC_FF_BCR] = { 0x9470 }, 709 [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 }, 710 [GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c }, 711 }; 712 713 static struct gdsc *gpu_cc_sm8450_gdscs[] = { 714 [GPU_CX_GDSC] = &gpu_cx_gdsc, 715 [GPU_GX_GDSC] = &gpu_gx_gdsc, 716 }; 717 718 static const struct regmap_config gpu_cc_sm8450_regmap_config = { 719 .reg_bits = 32, 720 .reg_stride = 4, 721 .val_bits = 32, 722 .max_register = 0xa000, 723 .fast_io = true, 724 }; 725 726 static const struct qcom_cc_desc gpu_cc_sm8450_desc = { 727 .config = &gpu_cc_sm8450_regmap_config, 728 .clks = gpu_cc_sm8450_clocks, 729 .num_clks = ARRAY_SIZE(gpu_cc_sm8450_clocks), 730 .resets = gpu_cc_sm8450_resets, 731 .num_resets = ARRAY_SIZE(gpu_cc_sm8450_resets), 732 .gdscs = gpu_cc_sm8450_gdscs, 733 .num_gdscs = ARRAY_SIZE(gpu_cc_sm8450_gdscs), 734 }; 735 736 static const struct of_device_id gpu_cc_sm8450_match_table[] = { 737 { .compatible = "qcom,sm8450-gpucc" }, 738 { } 739 }; 740 MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table); 741 742 static int gpu_cc_sm8450_probe(struct platform_device *pdev) 743 { 744 struct regmap *regmap; 745 746 regmap = qcom_cc_map(pdev, &gpu_cc_sm8450_desc); 747 if (IS_ERR(regmap)) 748 return PTR_ERR(regmap); 749 750 clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 751 clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 752 753 return qcom_cc_really_probe(pdev, &gpu_cc_sm8450_desc, regmap); 754 } 755 756 static struct platform_driver gpu_cc_sm8450_driver = { 757 .probe = gpu_cc_sm8450_probe, 758 .driver = { 759 .name = "sm8450-gpucc", 760 .of_match_table = gpu_cc_sm8450_match_table, 761 }, 762 }; 763 module_platform_driver(gpu_cc_sm8450_driver); 764 765 MODULE_DESCRIPTION("QTI GPU_CC SM8450 Driver"); 766 MODULE_LICENSE("GPL"); 767