1160758b0SRobert Foss // SPDX-License-Identifier: GPL-2.0 2160758b0SRobert Foss /* 3160758b0SRobert Foss * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 4160758b0SRobert Foss * Copyright (c) 2022, Linaro Limited 5160758b0SRobert Foss */ 6160758b0SRobert Foss 7160758b0SRobert Foss #include <linux/clk.h> 8160758b0SRobert Foss #include <linux/err.h> 9160758b0SRobert Foss #include <linux/kernel.h> 10160758b0SRobert Foss #include <linux/module.h> 11160758b0SRobert Foss #include <linux/of_device.h> 12160758b0SRobert Foss #include <linux/of.h> 13160758b0SRobert Foss #include <linux/regmap.h> 14160758b0SRobert Foss 15160758b0SRobert Foss #include <dt-bindings/clock/qcom,gpucc-sm8350.h> 16160758b0SRobert Foss 17160758b0SRobert Foss #include "clk-alpha-pll.h" 18160758b0SRobert Foss #include "clk-branch.h" 19160758b0SRobert Foss #include "clk-pll.h" 20160758b0SRobert Foss #include "clk-rcg.h" 21160758b0SRobert Foss #include "clk-regmap.h" 22160758b0SRobert Foss #include "common.h" 23160758b0SRobert Foss #include "clk-regmap-mux.h" 24160758b0SRobert Foss #include "clk-regmap-divider.h" 25160758b0SRobert Foss #include "gdsc.h" 26160758b0SRobert Foss #include "reset.h" 27160758b0SRobert Foss 28160758b0SRobert Foss enum { 29160758b0SRobert Foss P_BI_TCXO, 30160758b0SRobert Foss P_GPLL0_OUT_MAIN, 31160758b0SRobert Foss P_GPLL0_OUT_MAIN_DIV, 32160758b0SRobert Foss P_GPU_CC_PLL0_OUT_MAIN, 33160758b0SRobert Foss P_GPU_CC_PLL1_OUT_MAIN, 34160758b0SRobert Foss }; 35160758b0SRobert Foss 36160758b0SRobert Foss static struct pll_vco lucid_5lpe_vco[] = { 37160758b0SRobert Foss { 249600000, 1750000000, 0 }, 38160758b0SRobert Foss }; 39160758b0SRobert Foss 40160758b0SRobert Foss static const struct alpha_pll_config gpu_cc_pll0_config = { 41160758b0SRobert Foss .l = 0x18, 42160758b0SRobert Foss .alpha = 0x6000, 43160758b0SRobert Foss .config_ctl_val = 0x20485699, 44160758b0SRobert Foss .config_ctl_hi_val = 0x00002261, 45160758b0SRobert Foss .config_ctl_hi1_val = 0x2a9a699c, 46160758b0SRobert Foss .test_ctl_val = 0x00000000, 47160758b0SRobert Foss .test_ctl_hi_val = 0x00000000, 48160758b0SRobert Foss .test_ctl_hi1_val = 0x01800000, 49160758b0SRobert Foss .user_ctl_val = 0x00000000, 50160758b0SRobert Foss .user_ctl_hi_val = 0x00000805, 51160758b0SRobert Foss .user_ctl_hi1_val = 0x00000000, 52160758b0SRobert Foss }; 53160758b0SRobert Foss 54160758b0SRobert Foss static const struct clk_parent_data gpu_cc_parent = { 55160758b0SRobert Foss .fw_name = "bi_tcxo", 56160758b0SRobert Foss }; 57160758b0SRobert Foss 58160758b0SRobert Foss static struct clk_alpha_pll gpu_cc_pll0 = { 59160758b0SRobert Foss .offset = 0x0, 60160758b0SRobert Foss .vco_table = lucid_5lpe_vco, 61160758b0SRobert Foss .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 62160758b0SRobert Foss .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 63160758b0SRobert Foss .clkr = { 64160758b0SRobert Foss .hw.init = &(const struct clk_init_data){ 65160758b0SRobert Foss .name = "gpu_cc_pll0", 66160758b0SRobert Foss .parent_data = &gpu_cc_parent, 67160758b0SRobert Foss .num_parents = 1, 68160758b0SRobert Foss .ops = &clk_alpha_pll_lucid_5lpe_ops, 69160758b0SRobert Foss }, 70160758b0SRobert Foss }, 71160758b0SRobert Foss }; 72160758b0SRobert Foss 73160758b0SRobert Foss static const struct alpha_pll_config gpu_cc_pll1_config = { 74160758b0SRobert Foss .l = 0x1a, 75160758b0SRobert Foss .alpha = 0xaaa, 76160758b0SRobert Foss .config_ctl_val = 0x20485699, 77160758b0SRobert Foss .config_ctl_hi_val = 0x00002261, 78160758b0SRobert Foss .config_ctl_hi1_val = 0x2a9a699c, 79160758b0SRobert Foss .test_ctl_val = 0x00000000, 80160758b0SRobert Foss .test_ctl_hi_val = 0x00000000, 81160758b0SRobert Foss .test_ctl_hi1_val = 0x01800000, 82160758b0SRobert Foss .user_ctl_val = 0x00000000, 83160758b0SRobert Foss .user_ctl_hi_val = 0x00000805, 84160758b0SRobert Foss .user_ctl_hi1_val = 0x00000000, 85160758b0SRobert Foss }; 86160758b0SRobert Foss 87160758b0SRobert Foss static struct clk_alpha_pll gpu_cc_pll1 = { 88160758b0SRobert Foss .offset = 0x100, 89160758b0SRobert Foss .vco_table = lucid_5lpe_vco, 90160758b0SRobert Foss .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 91160758b0SRobert Foss .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 92160758b0SRobert Foss .clkr = { 93160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 94160758b0SRobert Foss .name = "gpu_cc_pll1", 95160758b0SRobert Foss .parent_data = &gpu_cc_parent, 96160758b0SRobert Foss .num_parents = 1, 97160758b0SRobert Foss .ops = &clk_alpha_pll_lucid_5lpe_ops, 98160758b0SRobert Foss }, 99160758b0SRobert Foss }, 100160758b0SRobert Foss }; 101160758b0SRobert Foss 102160758b0SRobert Foss static const struct parent_map gpu_cc_parent_map_0[] = { 103160758b0SRobert Foss { P_BI_TCXO, 0 }, 104160758b0SRobert Foss { P_GPU_CC_PLL0_OUT_MAIN, 1 }, 105160758b0SRobert Foss { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 106160758b0SRobert Foss { P_GPLL0_OUT_MAIN, 5 }, 107160758b0SRobert Foss { P_GPLL0_OUT_MAIN_DIV, 6 }, 108160758b0SRobert Foss }; 109160758b0SRobert Foss 110160758b0SRobert Foss static const struct clk_parent_data gpu_cc_parent_data_0[] = { 111*b5eb8cdeSRen Zhijie { .fw_name = "bi_tcxo" }, 112160758b0SRobert Foss { .hw = &gpu_cc_pll0.clkr.hw }, 113160758b0SRobert Foss { .hw = &gpu_cc_pll1.clkr.hw }, 114160758b0SRobert Foss { .fw_name = "gcc_gpu_gpll0_clk_src" }, 115160758b0SRobert Foss { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, 116160758b0SRobert Foss }; 117160758b0SRobert Foss 118160758b0SRobert Foss static const struct parent_map gpu_cc_parent_map_1[] = { 119160758b0SRobert Foss { P_BI_TCXO, 0 }, 120160758b0SRobert Foss { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 121160758b0SRobert Foss { P_GPLL0_OUT_MAIN, 5 }, 122160758b0SRobert Foss { P_GPLL0_OUT_MAIN_DIV, 6 }, 123160758b0SRobert Foss }; 124160758b0SRobert Foss 125160758b0SRobert Foss static const struct clk_parent_data gpu_cc_parent_data_1[] = { 126*b5eb8cdeSRen Zhijie { .fw_name = "bi_tcxo" }, 127160758b0SRobert Foss { .hw = &gpu_cc_pll1.clkr.hw }, 128160758b0SRobert Foss { .fw_name = "gcc_gpu_gpll0_clk_src" }, 129160758b0SRobert Foss { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, 130160758b0SRobert Foss }; 131160758b0SRobert Foss 132160758b0SRobert Foss static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 133160758b0SRobert Foss F(19200000, P_BI_TCXO, 1, 0, 0), 134160758b0SRobert Foss F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), 135160758b0SRobert Foss F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), 136160758b0SRobert Foss { } 137160758b0SRobert Foss }; 138160758b0SRobert Foss 139160758b0SRobert Foss static struct clk_rcg2 gpu_cc_gmu_clk_src = { 140160758b0SRobert Foss .cmd_rcgr = 0x1120, 141160758b0SRobert Foss .mnd_width = 0, 142160758b0SRobert Foss .hid_width = 5, 143160758b0SRobert Foss .parent_map = gpu_cc_parent_map_0, 144160758b0SRobert Foss .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 145160758b0SRobert Foss .clkr.hw.init = &(struct clk_init_data){ 146160758b0SRobert Foss .name = "gpu_cc_gmu_clk_src", 147160758b0SRobert Foss .parent_data = gpu_cc_parent_data_0, 148160758b0SRobert Foss .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 149160758b0SRobert Foss .flags = CLK_SET_RATE_PARENT, 150160758b0SRobert Foss .ops = &clk_rcg2_ops, 151160758b0SRobert Foss }, 152160758b0SRobert Foss }; 153160758b0SRobert Foss 154160758b0SRobert Foss static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { 155160758b0SRobert Foss F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), 156160758b0SRobert Foss F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 157160758b0SRobert Foss F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 158160758b0SRobert Foss { } 159160758b0SRobert Foss }; 160160758b0SRobert Foss 161160758b0SRobert Foss static struct clk_rcg2 gpu_cc_hub_clk_src = { 162160758b0SRobert Foss .cmd_rcgr = 0x117c, 163160758b0SRobert Foss .mnd_width = 0, 164160758b0SRobert Foss .hid_width = 5, 165160758b0SRobert Foss .parent_map = gpu_cc_parent_map_1, 166160758b0SRobert Foss .freq_tbl = ftbl_gpu_cc_hub_clk_src, 167160758b0SRobert Foss .clkr.hw.init = &(struct clk_init_data){ 168160758b0SRobert Foss .name = "gpu_cc_hub_clk_src", 169160758b0SRobert Foss .parent_data = gpu_cc_parent_data_1, 170160758b0SRobert Foss .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), 171160758b0SRobert Foss .flags = CLK_SET_RATE_PARENT, 172160758b0SRobert Foss .ops = &clk_rcg2_ops, 173160758b0SRobert Foss }, 174160758b0SRobert Foss }; 175160758b0SRobert Foss 176160758b0SRobert Foss static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { 177160758b0SRobert Foss .reg = 0x11c0, 178160758b0SRobert Foss .shift = 0, 179160758b0SRobert Foss .width = 4, 180160758b0SRobert Foss .clkr.hw.init = &(struct clk_init_data) { 181160758b0SRobert Foss .name = "gpu_cc_hub_ahb_div_clk_src", 182160758b0SRobert Foss .parent_hws = (const struct clk_hw*[]){ 183160758b0SRobert Foss &gpu_cc_hub_clk_src.clkr.hw, 184160758b0SRobert Foss }, 185160758b0SRobert Foss .num_parents = 1, 186160758b0SRobert Foss .flags = CLK_SET_RATE_PARENT, 187160758b0SRobert Foss .ops = &clk_regmap_div_ro_ops, 188160758b0SRobert Foss }, 189160758b0SRobert Foss }; 190160758b0SRobert Foss 191160758b0SRobert Foss static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { 192160758b0SRobert Foss .reg = 0x11bc, 193160758b0SRobert Foss .shift = 0, 194160758b0SRobert Foss .width = 4, 195160758b0SRobert Foss .clkr.hw.init = &(struct clk_init_data) { 196160758b0SRobert Foss .name = "gpu_cc_hub_cx_int_div_clk_src", 197160758b0SRobert Foss .parent_hws = (const struct clk_hw*[]){ 198160758b0SRobert Foss &gpu_cc_hub_clk_src.clkr.hw, 199160758b0SRobert Foss }, 200160758b0SRobert Foss .num_parents = 1, 201160758b0SRobert Foss .flags = CLK_SET_RATE_PARENT, 202160758b0SRobert Foss .ops = &clk_regmap_div_ro_ops, 203160758b0SRobert Foss }, 204160758b0SRobert Foss }; 205160758b0SRobert Foss 206160758b0SRobert Foss static struct clk_branch gpu_cc_ahb_clk = { 207160758b0SRobert Foss .halt_reg = 0x1078, 208160758b0SRobert Foss .halt_check = BRANCH_HALT_DELAY, 209160758b0SRobert Foss .clkr = { 210160758b0SRobert Foss .enable_reg = 0x1078, 211160758b0SRobert Foss .enable_mask = BIT(0), 212160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 213160758b0SRobert Foss .name = "gpu_cc_ahb_clk", 214160758b0SRobert Foss .parent_hws = (const struct clk_hw*[]){ 215160758b0SRobert Foss &gpu_cc_hub_ahb_div_clk_src.clkr.hw, 216160758b0SRobert Foss }, 217160758b0SRobert Foss .num_parents = 1, 218160758b0SRobert Foss .flags = CLK_SET_RATE_PARENT, 219160758b0SRobert Foss .ops = &clk_branch2_ops, 220160758b0SRobert Foss }, 221160758b0SRobert Foss }, 222160758b0SRobert Foss }; 223160758b0SRobert Foss 224160758b0SRobert Foss static struct clk_branch gpu_cc_cb_clk = { 225160758b0SRobert Foss .halt_reg = 0x1170, 226160758b0SRobert Foss .halt_check = BRANCH_HALT, 227160758b0SRobert Foss .clkr = { 228160758b0SRobert Foss .enable_reg = 0x1170, 229160758b0SRobert Foss .enable_mask = BIT(0), 230160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 231160758b0SRobert Foss .name = "gpu_cc_cb_clk", 232160758b0SRobert Foss .ops = &clk_branch2_ops, 233160758b0SRobert Foss }, 234160758b0SRobert Foss }, 235160758b0SRobert Foss }; 236160758b0SRobert Foss 237160758b0SRobert Foss static struct clk_branch gpu_cc_crc_ahb_clk = { 238160758b0SRobert Foss .halt_reg = 0x107c, 239160758b0SRobert Foss .halt_check = BRANCH_HALT_VOTED, 240160758b0SRobert Foss .clkr = { 241160758b0SRobert Foss .enable_reg = 0x107c, 242160758b0SRobert Foss .enable_mask = BIT(0), 243160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 244160758b0SRobert Foss .name = "gpu_cc_crc_ahb_clk", 245160758b0SRobert Foss .parent_hws = (const struct clk_hw*[]){ 246160758b0SRobert Foss &gpu_cc_hub_ahb_div_clk_src.clkr.hw, 247160758b0SRobert Foss }, 248160758b0SRobert Foss .num_parents = 1, 249160758b0SRobert Foss .flags = CLK_SET_RATE_PARENT, 250160758b0SRobert Foss .ops = &clk_branch2_ops, 251160758b0SRobert Foss }, 252160758b0SRobert Foss }, 253160758b0SRobert Foss }; 254160758b0SRobert Foss 255160758b0SRobert Foss static struct clk_branch gpu_cc_cx_apb_clk = { 256160758b0SRobert Foss .halt_reg = 0x1088, 257160758b0SRobert Foss .halt_check = BRANCH_HALT_VOTED, 258160758b0SRobert Foss .clkr = { 259160758b0SRobert Foss .enable_reg = 0x1088, 260160758b0SRobert Foss .enable_mask = BIT(0), 261160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 262160758b0SRobert Foss .name = "gpu_cc_cx_apb_clk", 263160758b0SRobert Foss .ops = &clk_branch2_ops, 264160758b0SRobert Foss }, 265160758b0SRobert Foss }, 266160758b0SRobert Foss }; 267160758b0SRobert Foss 268160758b0SRobert Foss static struct clk_branch gpu_cc_cx_gmu_clk = { 269160758b0SRobert Foss .halt_reg = 0x1098, 270160758b0SRobert Foss .halt_check = BRANCH_HALT, 271160758b0SRobert Foss .clkr = { 272160758b0SRobert Foss .enable_reg = 0x1098, 273160758b0SRobert Foss .enable_mask = BIT(0), 274160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 275160758b0SRobert Foss .name = "gpu_cc_cx_gmu_clk", 276160758b0SRobert Foss .parent_hws = (const struct clk_hw*[]){ 277160758b0SRobert Foss &gpu_cc_gmu_clk_src.clkr.hw, 278160758b0SRobert Foss }, 279160758b0SRobert Foss .num_parents = 1, 280160758b0SRobert Foss .flags = CLK_SET_RATE_PARENT, 281160758b0SRobert Foss .ops = &clk_branch2_aon_ops, 282160758b0SRobert Foss }, 283160758b0SRobert Foss }, 284160758b0SRobert Foss }; 285160758b0SRobert Foss 286160758b0SRobert Foss static struct clk_branch gpu_cc_cx_qdss_at_clk = { 287160758b0SRobert Foss .halt_reg = 0x1080, 288160758b0SRobert Foss .halt_check = BRANCH_HALT_VOTED, 289160758b0SRobert Foss .clkr = { 290160758b0SRobert Foss .enable_reg = 0x1080, 291160758b0SRobert Foss .enable_mask = BIT(0), 292160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 293160758b0SRobert Foss .name = "gpu_cc_cx_qdss_at_clk", 294160758b0SRobert Foss .ops = &clk_branch2_ops, 295160758b0SRobert Foss }, 296160758b0SRobert Foss }, 297160758b0SRobert Foss }; 298160758b0SRobert Foss 299160758b0SRobert Foss static struct clk_branch gpu_cc_cx_qdss_trig_clk = { 300160758b0SRobert Foss .halt_reg = 0x1094, 301160758b0SRobert Foss .halt_check = BRANCH_HALT_VOTED, 302160758b0SRobert Foss .clkr = { 303160758b0SRobert Foss .enable_reg = 0x1094, 304160758b0SRobert Foss .enable_mask = BIT(0), 305160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 306160758b0SRobert Foss .name = "gpu_cc_cx_qdss_trig_clk", 307160758b0SRobert Foss .ops = &clk_branch2_ops, 308160758b0SRobert Foss }, 309160758b0SRobert Foss }, 310160758b0SRobert Foss }; 311160758b0SRobert Foss 312160758b0SRobert Foss static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = { 313160758b0SRobert Foss .halt_reg = 0x1084, 314160758b0SRobert Foss .halt_check = BRANCH_HALT_VOTED, 315160758b0SRobert Foss .clkr = { 316160758b0SRobert Foss .enable_reg = 0x1084, 317160758b0SRobert Foss .enable_mask = BIT(0), 318160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 319160758b0SRobert Foss .name = "gpu_cc_cx_qdss_tsctr_clk", 320160758b0SRobert Foss .ops = &clk_branch2_ops, 321160758b0SRobert Foss }, 322160758b0SRobert Foss }, 323160758b0SRobert Foss }; 324160758b0SRobert Foss 325160758b0SRobert Foss static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { 326160758b0SRobert Foss .halt_reg = 0x108c, 327160758b0SRobert Foss .halt_check = BRANCH_HALT_VOTED, 328160758b0SRobert Foss .clkr = { 329160758b0SRobert Foss .enable_reg = 0x108c, 330160758b0SRobert Foss .enable_mask = BIT(0), 331160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 332160758b0SRobert Foss .name = "gpu_cc_cx_snoc_dvm_clk", 333160758b0SRobert Foss .ops = &clk_branch2_ops, 334160758b0SRobert Foss }, 335160758b0SRobert Foss }, 336160758b0SRobert Foss }; 337160758b0SRobert Foss 338160758b0SRobert Foss static struct clk_branch gpu_cc_cxo_aon_clk = { 339160758b0SRobert Foss .halt_reg = 0x1004, 340160758b0SRobert Foss .halt_check = BRANCH_HALT_VOTED, 341160758b0SRobert Foss .clkr = { 342160758b0SRobert Foss .enable_reg = 0x1004, 343160758b0SRobert Foss .enable_mask = BIT(0), 344160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 345160758b0SRobert Foss .name = "gpu_cc_cxo_aon_clk", 346160758b0SRobert Foss .ops = &clk_branch2_ops, 347160758b0SRobert Foss }, 348160758b0SRobert Foss }, 349160758b0SRobert Foss }; 350160758b0SRobert Foss 351160758b0SRobert Foss static struct clk_branch gpu_cc_cxo_clk = { 352160758b0SRobert Foss .halt_reg = 0x109c, 353160758b0SRobert Foss .halt_check = BRANCH_HALT, 354160758b0SRobert Foss .clkr = { 355160758b0SRobert Foss .enable_reg = 0x109c, 356160758b0SRobert Foss .enable_mask = BIT(0), 357160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 358160758b0SRobert Foss .name = "gpu_cc_cxo_clk", 359160758b0SRobert Foss .ops = &clk_branch2_ops, 360160758b0SRobert Foss }, 361160758b0SRobert Foss }, 362160758b0SRobert Foss }; 363160758b0SRobert Foss 364160758b0SRobert Foss static struct clk_branch gpu_cc_freq_measure_clk = { 365160758b0SRobert Foss .halt_reg = 0x120c, 366160758b0SRobert Foss .halt_check = BRANCH_HALT, 367160758b0SRobert Foss .clkr = { 368160758b0SRobert Foss .enable_reg = 0x120c, 369160758b0SRobert Foss .enable_mask = BIT(0), 370160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 371160758b0SRobert Foss .name = "gpu_cc_freq_measure_clk", 372160758b0SRobert Foss .ops = &clk_branch2_ops, 373160758b0SRobert Foss }, 374160758b0SRobert Foss }, 375160758b0SRobert Foss }; 376160758b0SRobert Foss 377160758b0SRobert Foss static struct clk_branch gpu_cc_gx_gmu_clk = { 378160758b0SRobert Foss .halt_reg = 0x1064, 379160758b0SRobert Foss .halt_check = BRANCH_HALT, 380160758b0SRobert Foss .clkr = { 381160758b0SRobert Foss .enable_reg = 0x1064, 382160758b0SRobert Foss .enable_mask = BIT(0), 383160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 384160758b0SRobert Foss .name = "gpu_cc_gx_gmu_clk", 385160758b0SRobert Foss .parent_hws = (const struct clk_hw*[]){ 386160758b0SRobert Foss &gpu_cc_gmu_clk_src.clkr.hw, 387160758b0SRobert Foss }, 388160758b0SRobert Foss .num_parents = 1, 389160758b0SRobert Foss .flags = CLK_SET_RATE_PARENT, 390160758b0SRobert Foss .ops = &clk_branch2_ops, 391160758b0SRobert Foss }, 392160758b0SRobert Foss }, 393160758b0SRobert Foss }; 394160758b0SRobert Foss 395160758b0SRobert Foss static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = { 396160758b0SRobert Foss .halt_reg = 0x105c, 397160758b0SRobert Foss .halt_check = BRANCH_HALT_VOTED, 398160758b0SRobert Foss .clkr = { 399160758b0SRobert Foss .enable_reg = 0x105c, 400160758b0SRobert Foss .enable_mask = BIT(0), 401160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 402160758b0SRobert Foss .name = "gpu_cc_gx_qdss_tsctr_clk", 403160758b0SRobert Foss .ops = &clk_branch2_ops, 404160758b0SRobert Foss }, 405160758b0SRobert Foss }, 406160758b0SRobert Foss }; 407160758b0SRobert Foss 408160758b0SRobert Foss static struct clk_branch gpu_cc_gx_vsense_clk = { 409160758b0SRobert Foss .halt_reg = 0x1058, 410160758b0SRobert Foss .halt_check = BRANCH_HALT_VOTED, 411160758b0SRobert Foss .clkr = { 412160758b0SRobert Foss .enable_reg = 0x1058, 413160758b0SRobert Foss .enable_mask = BIT(0), 414160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 415160758b0SRobert Foss .name = "gpu_cc_gx_vsense_clk", 416160758b0SRobert Foss .ops = &clk_branch2_ops, 417160758b0SRobert Foss }, 418160758b0SRobert Foss }, 419160758b0SRobert Foss }; 420160758b0SRobert Foss 421160758b0SRobert Foss static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { 422160758b0SRobert Foss .halt_reg = 0x5000, 423160758b0SRobert Foss .halt_check = BRANCH_HALT_VOTED, 424160758b0SRobert Foss .clkr = { 425160758b0SRobert Foss .enable_reg = 0x5000, 426160758b0SRobert Foss .enable_mask = BIT(0), 427160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 428160758b0SRobert Foss .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", 429160758b0SRobert Foss .ops = &clk_branch2_ops, 430160758b0SRobert Foss }, 431160758b0SRobert Foss }, 432160758b0SRobert Foss }; 433160758b0SRobert Foss 434160758b0SRobert Foss static struct clk_branch gpu_cc_hub_aon_clk = { 435160758b0SRobert Foss .halt_reg = 0x1178, 436160758b0SRobert Foss .halt_check = BRANCH_HALT, 437160758b0SRobert Foss .clkr = { 438160758b0SRobert Foss .enable_reg = 0x1178, 439160758b0SRobert Foss .enable_mask = BIT(0), 440160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 441160758b0SRobert Foss .name = "gpu_cc_hub_aon_clk", 442160758b0SRobert Foss .parent_hws = (const struct clk_hw*[]){ 443160758b0SRobert Foss &gpu_cc_hub_clk_src.clkr.hw, 444160758b0SRobert Foss }, 445160758b0SRobert Foss .num_parents = 1, 446160758b0SRobert Foss .flags = CLK_SET_RATE_PARENT, 447160758b0SRobert Foss .ops = &clk_branch2_aon_ops, 448160758b0SRobert Foss }, 449160758b0SRobert Foss }, 450160758b0SRobert Foss }; 451160758b0SRobert Foss 452160758b0SRobert Foss static struct clk_branch gpu_cc_hub_cx_int_clk = { 453160758b0SRobert Foss .halt_reg = 0x1204, 454160758b0SRobert Foss .halt_check = BRANCH_HALT, 455160758b0SRobert Foss .clkr = { 456160758b0SRobert Foss .enable_reg = 0x1204, 457160758b0SRobert Foss .enable_mask = BIT(0), 458160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 459160758b0SRobert Foss .name = "gpu_cc_hub_cx_int_clk", 460160758b0SRobert Foss .parent_hws = (const struct clk_hw*[]){ 461160758b0SRobert Foss &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, 462160758b0SRobert Foss }, 463160758b0SRobert Foss .num_parents = 1, 464160758b0SRobert Foss .flags = CLK_SET_RATE_PARENT, 465160758b0SRobert Foss .ops = &clk_branch2_aon_ops, 466160758b0SRobert Foss }, 467160758b0SRobert Foss }, 468160758b0SRobert Foss }; 469160758b0SRobert Foss 470160758b0SRobert Foss static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { 471160758b0SRobert Foss .halt_reg = 0x802c, 472160758b0SRobert Foss .halt_check = BRANCH_HALT, 473160758b0SRobert Foss .clkr = { 474160758b0SRobert Foss .enable_reg = 0x802c, 475160758b0SRobert Foss .enable_mask = BIT(0), 476160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 477160758b0SRobert Foss .name = "gpu_cc_mnd1x_0_gfx3d_clk", 478160758b0SRobert Foss .ops = &clk_branch2_ops, 479160758b0SRobert Foss }, 480160758b0SRobert Foss }, 481160758b0SRobert Foss }; 482160758b0SRobert Foss 483160758b0SRobert Foss static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { 484160758b0SRobert Foss .halt_reg = 0x8030, 485160758b0SRobert Foss .halt_check = BRANCH_HALT, 486160758b0SRobert Foss .clkr = { 487160758b0SRobert Foss .enable_reg = 0x8030, 488160758b0SRobert Foss .enable_mask = BIT(0), 489160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 490160758b0SRobert Foss .name = "gpu_cc_mnd1x_1_gfx3d_clk", 491160758b0SRobert Foss .ops = &clk_branch2_ops, 492160758b0SRobert Foss }, 493160758b0SRobert Foss }, 494160758b0SRobert Foss }; 495160758b0SRobert Foss 496160758b0SRobert Foss static struct clk_branch gpu_cc_sleep_clk = { 497160758b0SRobert Foss .halt_reg = 0x1090, 498160758b0SRobert Foss .halt_check = BRANCH_HALT_VOTED, 499160758b0SRobert Foss .clkr = { 500160758b0SRobert Foss .enable_reg = 0x1090, 501160758b0SRobert Foss .enable_mask = BIT(0), 502160758b0SRobert Foss .hw.init = &(struct clk_init_data){ 503160758b0SRobert Foss .name = "gpu_cc_sleep_clk", 504160758b0SRobert Foss .ops = &clk_branch2_ops, 505160758b0SRobert Foss }, 506160758b0SRobert Foss }, 507160758b0SRobert Foss }; 508160758b0SRobert Foss 509160758b0SRobert Foss static struct gdsc gpu_cx_gdsc = { 510160758b0SRobert Foss .gdscr = 0x106c, 511160758b0SRobert Foss .gds_hw_ctrl = 0x1540, 512160758b0SRobert Foss .pd = { 513160758b0SRobert Foss .name = "gpu_cx_gdsc", 514160758b0SRobert Foss }, 515160758b0SRobert Foss .pwrsts = PWRSTS_OFF_ON, 516160758b0SRobert Foss .flags = VOTABLE, 517160758b0SRobert Foss }; 518160758b0SRobert Foss 519160758b0SRobert Foss static struct gdsc gpu_gx_gdsc = { 520160758b0SRobert Foss .gdscr = 0x100c, 521160758b0SRobert Foss .clamp_io_ctrl = 0x1508, 522160758b0SRobert Foss .pd = { 523160758b0SRobert Foss .name = "gpu_gx_gdsc", 524160758b0SRobert Foss .power_on = gdsc_gx_do_nothing_enable, 525160758b0SRobert Foss }, 526160758b0SRobert Foss .pwrsts = PWRSTS_OFF_ON, 527160758b0SRobert Foss .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, 528160758b0SRobert Foss }; 529160758b0SRobert Foss 530160758b0SRobert Foss static struct clk_regmap *gpu_cc_sm8350_clocks[] = { 531160758b0SRobert Foss [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, 532160758b0SRobert Foss [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, 533160758b0SRobert Foss [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, 534160758b0SRobert Foss [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, 535160758b0SRobert Foss [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 536160758b0SRobert Foss [GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr, 537160758b0SRobert Foss [GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr, 538160758b0SRobert Foss [GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr, 539160758b0SRobert Foss [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, 540160758b0SRobert Foss [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, 541160758b0SRobert Foss [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 542160758b0SRobert Foss [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, 543160758b0SRobert Foss [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 544160758b0SRobert Foss [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, 545160758b0SRobert Foss [GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr, 546160758b0SRobert Foss [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, 547160758b0SRobert Foss [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, 548160758b0SRobert Foss [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, 549160758b0SRobert Foss [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, 550160758b0SRobert Foss [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, 551160758b0SRobert Foss [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, 552160758b0SRobert Foss [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, 553160758b0SRobert Foss [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, 554160758b0SRobert Foss [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, 555160758b0SRobert Foss [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, 556160758b0SRobert Foss [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 557160758b0SRobert Foss [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, 558160758b0SRobert Foss }; 559160758b0SRobert Foss 560160758b0SRobert Foss static const struct qcom_reset_map gpu_cc_sm8350_resets[] = { 561160758b0SRobert Foss [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 }, 562160758b0SRobert Foss [GPUCC_GPU_CC_CB_BCR] = { 0x116c }, 563160758b0SRobert Foss [GPUCC_GPU_CC_CX_BCR] = { 0x1068 }, 564160758b0SRobert Foss [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 }, 565160758b0SRobert Foss [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 }, 566160758b0SRobert Foss [GPUCC_GPU_CC_GMU_BCR] = { 0x111c }, 567160758b0SRobert Foss [GPUCC_GPU_CC_GX_BCR] = { 0x1008 }, 568160758b0SRobert Foss [GPUCC_GPU_CC_XO_BCR] = { 0x1000 }, 569160758b0SRobert Foss }; 570160758b0SRobert Foss 571160758b0SRobert Foss static struct gdsc *gpu_cc_sm8350_gdscs[] = { 572160758b0SRobert Foss [GPU_CX_GDSC] = &gpu_cx_gdsc, 573160758b0SRobert Foss [GPU_GX_GDSC] = &gpu_gx_gdsc, 574160758b0SRobert Foss }; 575160758b0SRobert Foss 576160758b0SRobert Foss static const struct regmap_config gpu_cc_sm8350_regmap_config = { 577160758b0SRobert Foss .reg_bits = 32, 578160758b0SRobert Foss .reg_stride = 4, 579160758b0SRobert Foss .val_bits = 32, 580160758b0SRobert Foss .max_register = 0x8030, 581160758b0SRobert Foss .fast_io = true, 582160758b0SRobert Foss }; 583160758b0SRobert Foss 584160758b0SRobert Foss static const struct qcom_cc_desc gpu_cc_sm8350_desc = { 585160758b0SRobert Foss .config = &gpu_cc_sm8350_regmap_config, 586160758b0SRobert Foss .clks = gpu_cc_sm8350_clocks, 587160758b0SRobert Foss .num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks), 588160758b0SRobert Foss .resets = gpu_cc_sm8350_resets, 589160758b0SRobert Foss .num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets), 590160758b0SRobert Foss .gdscs = gpu_cc_sm8350_gdscs, 591160758b0SRobert Foss .num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs), 592160758b0SRobert Foss }; 593160758b0SRobert Foss 594160758b0SRobert Foss static int gpu_cc_sm8350_probe(struct platform_device *pdev) 595160758b0SRobert Foss { 596160758b0SRobert Foss struct regmap *regmap; 597160758b0SRobert Foss 598160758b0SRobert Foss regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc); 599160758b0SRobert Foss if (IS_ERR(regmap)) { 600160758b0SRobert Foss dev_err(&pdev->dev, "Failed to map gpu cc registers\n"); 601160758b0SRobert Foss return PTR_ERR(regmap); 602160758b0SRobert Foss } 603160758b0SRobert Foss 604160758b0SRobert Foss clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 605160758b0SRobert Foss clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 606160758b0SRobert Foss 607160758b0SRobert Foss return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap); 608160758b0SRobert Foss } 609160758b0SRobert Foss 610160758b0SRobert Foss static const struct of_device_id gpu_cc_sm8350_match_table[] = { 611160758b0SRobert Foss { .compatible = "qcom,sm8350-gpucc" }, 612160758b0SRobert Foss { } 613160758b0SRobert Foss }; 614160758b0SRobert Foss MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table); 615160758b0SRobert Foss 616160758b0SRobert Foss static struct platform_driver gpu_cc_sm8350_driver = { 617160758b0SRobert Foss .probe = gpu_cc_sm8350_probe, 618160758b0SRobert Foss .driver = { 619160758b0SRobert Foss .name = "sm8350-gpucc", 620160758b0SRobert Foss .of_match_table = gpu_cc_sm8350_match_table, 621160758b0SRobert Foss }, 622160758b0SRobert Foss }; 623160758b0SRobert Foss 624160758b0SRobert Foss static int __init gpu_cc_sm8350_init(void) 625160758b0SRobert Foss { 626160758b0SRobert Foss return platform_driver_register(&gpu_cc_sm8350_driver); 627160758b0SRobert Foss } 628160758b0SRobert Foss subsys_initcall(gpu_cc_sm8350_init); 629160758b0SRobert Foss 630160758b0SRobert Foss static void __exit gpu_cc_sm8350_exit(void) 631160758b0SRobert Foss { 632160758b0SRobert Foss platform_driver_unregister(&gpu_cc_sm8350_driver); 633160758b0SRobert Foss } 634160758b0SRobert Foss module_exit(gpu_cc_sm8350_exit); 635160758b0SRobert Foss 636160758b0SRobert Foss MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver"); 637160758b0SRobert Foss MODULE_LICENSE("GPL v2"); 638