1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,gpucc-sm8150.h> 12 13 #include "common.h" 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "reset.h" 20 #include "gdsc.h" 21 22 enum { 23 P_BI_TCXO, 24 P_GPLL0_OUT_MAIN, 25 P_GPLL0_OUT_MAIN_DIV, 26 P_GPU_CC_PLL1_OUT_MAIN, 27 }; 28 29 static const struct pll_vco trion_vco[] = { 30 { 249600000, 2000000000, 0 }, 31 }; 32 33 static struct alpha_pll_config gpu_cc_pll1_config = { 34 .l = 0x1a, 35 .alpha = 0xaaa, 36 .config_ctl_val = 0x20485699, 37 .config_ctl_hi_val = 0x00002267, 38 .config_ctl_hi1_val = 0x00000024, 39 .test_ctl_val = 0x00000000, 40 .test_ctl_hi_val = 0x00000002, 41 .test_ctl_hi1_val = 0x00000000, 42 .user_ctl_val = 0x00000000, 43 .user_ctl_hi_val = 0x00000805, 44 .user_ctl_hi1_val = 0x000000d0, 45 }; 46 47 static struct clk_alpha_pll gpu_cc_pll1 = { 48 .offset = 0x100, 49 .vco_table = trion_vco, 50 .num_vco = ARRAY_SIZE(trion_vco), 51 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 52 .clkr = { 53 .hw.init = &(struct clk_init_data){ 54 .name = "gpu_cc_pll1", 55 .parent_data = &(const struct clk_parent_data){ 56 .fw_name = "bi_tcxo", 57 }, 58 .num_parents = 1, 59 .ops = &clk_alpha_pll_trion_ops, 60 }, 61 }, 62 }; 63 64 static const struct parent_map gpu_cc_parent_map_0[] = { 65 { P_BI_TCXO, 0 }, 66 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 67 { P_GPLL0_OUT_MAIN, 5 }, 68 { P_GPLL0_OUT_MAIN_DIV, 6 }, 69 }; 70 71 static const struct clk_parent_data gpu_cc_parent_data_0[] = { 72 { .fw_name = "bi_tcxo" }, 73 { .hw = &gpu_cc_pll1.clkr.hw }, 74 { .fw_name = "gcc_gpu_gpll0_clk_src" }, 75 { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, 76 }; 77 78 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 79 F(19200000, P_BI_TCXO, 1, 0, 0), 80 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), 81 F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), 82 { } 83 }; 84 85 static struct clk_rcg2 gpu_cc_gmu_clk_src = { 86 .cmd_rcgr = 0x1120, 87 .mnd_width = 0, 88 .hid_width = 5, 89 .parent_map = gpu_cc_parent_map_0, 90 .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 91 .clkr.hw.init = &(struct clk_init_data){ 92 .name = "gpu_cc_gmu_clk_src", 93 .parent_data = gpu_cc_parent_data_0, 94 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 95 .flags = CLK_SET_RATE_PARENT, 96 .ops = &clk_rcg2_ops, 97 }, 98 }; 99 100 static struct clk_branch gpu_cc_ahb_clk = { 101 .halt_reg = 0x1078, 102 .halt_check = BRANCH_HALT_DELAY, 103 .clkr = { 104 .enable_reg = 0x1078, 105 .enable_mask = BIT(0), 106 .hw.init = &(struct clk_init_data){ 107 .name = "gpu_cc_ahb_clk", 108 .ops = &clk_branch2_ops, 109 }, 110 }, 111 }; 112 113 static struct clk_branch gpu_cc_crc_ahb_clk = { 114 .halt_reg = 0x107c, 115 .halt_check = BRANCH_HALT, 116 .clkr = { 117 .enable_reg = 0x107c, 118 .enable_mask = BIT(0), 119 .hw.init = &(struct clk_init_data){ 120 .name = "gpu_cc_crc_ahb_clk", 121 .ops = &clk_branch2_ops, 122 }, 123 }, 124 }; 125 126 static struct clk_branch gpu_cc_cx_apb_clk = { 127 .halt_reg = 0x1088, 128 .halt_check = BRANCH_HALT, 129 .clkr = { 130 .enable_reg = 0x1088, 131 .enable_mask = BIT(0), 132 .hw.init = &(struct clk_init_data){ 133 .name = "gpu_cc_cx_apb_clk", 134 .ops = &clk_branch2_ops, 135 }, 136 }, 137 }; 138 139 static struct clk_branch gpu_cc_cx_gmu_clk = { 140 .halt_reg = 0x1098, 141 .halt_check = BRANCH_HALT, 142 .clkr = { 143 .enable_reg = 0x1098, 144 .enable_mask = BIT(0), 145 .hw.init = &(struct clk_init_data){ 146 .name = "gpu_cc_cx_gmu_clk", 147 .parent_data = &(const struct clk_parent_data){ 148 .hw = &gpu_cc_gmu_clk_src.clkr.hw, 149 }, 150 .num_parents = 1, 151 .flags = CLK_SET_RATE_PARENT, 152 .ops = &clk_branch2_ops, 153 }, 154 }, 155 }; 156 157 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { 158 .halt_reg = 0x108c, 159 .halt_check = BRANCH_HALT, 160 .clkr = { 161 .enable_reg = 0x108c, 162 .enable_mask = BIT(0), 163 .hw.init = &(struct clk_init_data){ 164 .name = "gpu_cc_cx_snoc_dvm_clk", 165 .ops = &clk_branch2_ops, 166 }, 167 }, 168 }; 169 170 static struct clk_branch gpu_cc_cxo_aon_clk = { 171 .halt_reg = 0x1004, 172 .halt_check = BRANCH_HALT, 173 .clkr = { 174 .enable_reg = 0x1004, 175 .enable_mask = BIT(0), 176 .hw.init = &(struct clk_init_data){ 177 .name = "gpu_cc_cxo_aon_clk", 178 .ops = &clk_branch2_ops, 179 }, 180 }, 181 }; 182 183 static struct clk_branch gpu_cc_cxo_clk = { 184 .halt_reg = 0x109c, 185 .halt_check = BRANCH_HALT, 186 .clkr = { 187 .enable_reg = 0x109c, 188 .enable_mask = BIT(0), 189 .hw.init = &(struct clk_init_data){ 190 .name = "gpu_cc_cxo_clk", 191 .ops = &clk_branch2_ops, 192 }, 193 }, 194 }; 195 196 static struct clk_branch gpu_cc_gx_gmu_clk = { 197 .halt_reg = 0x1064, 198 .halt_check = BRANCH_HALT, 199 .clkr = { 200 .enable_reg = 0x1064, 201 .enable_mask = BIT(0), 202 .hw.init = &(struct clk_init_data){ 203 .name = "gpu_cc_gx_gmu_clk", 204 .parent_data = &(const struct clk_parent_data){ 205 .hw = &gpu_cc_gmu_clk_src.clkr.hw, 206 }, 207 .num_parents = 1, 208 .flags = CLK_SET_RATE_PARENT, 209 .ops = &clk_branch2_ops, 210 }, 211 }, 212 }; 213 214 static struct gdsc gpu_cx_gdsc = { 215 .gdscr = 0x106c, 216 .gds_hw_ctrl = 0x1540, 217 .pd = { 218 .name = "gpu_cx_gdsc", 219 }, 220 .pwrsts = PWRSTS_OFF_ON, 221 .flags = VOTABLE, 222 }; 223 224 static struct gdsc gpu_gx_gdsc = { 225 .gdscr = 0x100c, 226 .clamp_io_ctrl = 0x1508, 227 .pd = { 228 .name = "gpu_gx_gdsc", 229 .power_on = gdsc_gx_do_nothing_enable, 230 }, 231 .pwrsts = PWRSTS_OFF_ON, 232 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, 233 }; 234 235 static struct clk_regmap *gpu_cc_sm8150_clocks[] = { 236 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, 237 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, 238 [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, 239 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 240 [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, 241 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, 242 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 243 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 244 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, 245 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 246 }; 247 248 static const struct qcom_reset_map gpu_cc_sm8150_resets[] = { 249 [GPUCC_GPU_CC_CX_BCR] = { 0x1068 }, 250 [GPUCC_GPU_CC_GMU_BCR] = { 0x111c }, 251 [GPUCC_GPU_CC_GX_BCR] = { 0x1008 }, 252 [GPUCC_GPU_CC_SPDM_BCR] = { 0x1110 }, 253 [GPUCC_GPU_CC_XO_BCR] = { 0x1000 }, 254 }; 255 256 static struct gdsc *gpu_cc_sm8150_gdscs[] = { 257 [GPU_CX_GDSC] = &gpu_cx_gdsc, 258 [GPU_GX_GDSC] = &gpu_gx_gdsc, 259 }; 260 261 static const struct regmap_config gpu_cc_sm8150_regmap_config = { 262 .reg_bits = 32, 263 .reg_stride = 4, 264 .val_bits = 32, 265 .max_register = 0x8008, 266 .fast_io = true, 267 }; 268 269 static const struct qcom_cc_desc gpu_cc_sm8150_desc = { 270 .config = &gpu_cc_sm8150_regmap_config, 271 .clks = gpu_cc_sm8150_clocks, 272 .num_clks = ARRAY_SIZE(gpu_cc_sm8150_clocks), 273 .resets = gpu_cc_sm8150_resets, 274 .num_resets = ARRAY_SIZE(gpu_cc_sm8150_resets), 275 .gdscs = gpu_cc_sm8150_gdscs, 276 .num_gdscs = ARRAY_SIZE(gpu_cc_sm8150_gdscs), 277 }; 278 279 static const struct of_device_id gpu_cc_sm8150_match_table[] = { 280 { .compatible = "qcom,sm8150-gpucc" }, 281 { } 282 }; 283 MODULE_DEVICE_TABLE(of, gpu_cc_sm8150_match_table); 284 285 static int gpu_cc_sm8150_probe(struct platform_device *pdev) 286 { 287 struct regmap *regmap; 288 289 regmap = qcom_cc_map(pdev, &gpu_cc_sm8150_desc); 290 if (IS_ERR(regmap)) 291 return PTR_ERR(regmap); 292 293 clk_trion_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 294 295 return qcom_cc_really_probe(pdev, &gpu_cc_sm8150_desc, regmap); 296 } 297 298 static struct platform_driver gpu_cc_sm8150_driver = { 299 .probe = gpu_cc_sm8150_probe, 300 .driver = { 301 .name = "sm8150-gpucc", 302 .of_match_table = gpu_cc_sm8150_match_table, 303 }, 304 }; 305 306 static int __init gpu_cc_sm8150_init(void) 307 { 308 return platform_driver_register(&gpu_cc_sm8150_driver); 309 } 310 subsys_initcall(gpu_cc_sm8150_init); 311 312 static void __exit gpu_cc_sm8150_exit(void) 313 { 314 platform_driver_unregister(&gpu_cc_sm8150_driver); 315 } 316 module_exit(gpu_cc_sm8150_exit); 317 318 MODULE_DESCRIPTION("QTI GPUCC SM8150 Driver"); 319 MODULE_LICENSE("GPL v2"); 320