1453361cdSAmit Nischal // SPDX-License-Identifier: GPL-2.0 2453361cdSAmit Nischal /* 3453361cdSAmit Nischal * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4453361cdSAmit Nischal */ 5453361cdSAmit Nischal 6453361cdSAmit Nischal #include <linux/clk-provider.h> 7453361cdSAmit Nischal #include <linux/module.h> 8453361cdSAmit Nischal #include <linux/platform_device.h> 9453361cdSAmit Nischal #include <linux/regmap.h> 10453361cdSAmit Nischal 11453361cdSAmit Nischal #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12453361cdSAmit Nischal 13453361cdSAmit Nischal #include "common.h" 14453361cdSAmit Nischal #include "clk-alpha-pll.h" 15453361cdSAmit Nischal #include "clk-branch.h" 16453361cdSAmit Nischal #include "clk-pll.h" 17453361cdSAmit Nischal #include "clk-rcg.h" 18453361cdSAmit Nischal #include "clk-regmap.h" 19453361cdSAmit Nischal #include "gdsc.h" 20453361cdSAmit Nischal 21453361cdSAmit Nischal #define CX_GMU_CBCR_SLEEP_MASK 0xf 22453361cdSAmit Nischal #define CX_GMU_CBCR_SLEEP_SHIFT 4 23453361cdSAmit Nischal #define CX_GMU_CBCR_WAKE_MASK 0xf 24453361cdSAmit Nischal #define CX_GMU_CBCR_WAKE_SHIFT 8 25453361cdSAmit Nischal #define CLK_DIS_WAIT_SHIFT 12 26453361cdSAmit Nischal #define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT) 27453361cdSAmit Nischal 28453361cdSAmit Nischal enum { 29453361cdSAmit Nischal P_BI_TCXO, 30453361cdSAmit Nischal P_GPLL0_OUT_MAIN, 31453361cdSAmit Nischal P_GPLL0_OUT_MAIN_DIV, 32453361cdSAmit Nischal P_GPU_CC_PLL1_OUT_MAIN, 33453361cdSAmit Nischal }; 34453361cdSAmit Nischal 35453361cdSAmit Nischal static const struct alpha_pll_config gpu_cc_pll1_config = { 36453361cdSAmit Nischal .l = 0x1a, 37453361cdSAmit Nischal .alpha = 0xaab, 38453361cdSAmit Nischal }; 39453361cdSAmit Nischal 40453361cdSAmit Nischal static struct clk_alpha_pll gpu_cc_pll1 = { 41453361cdSAmit Nischal .offset = 0x100, 42453361cdSAmit Nischal .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 43453361cdSAmit Nischal .clkr = { 44453361cdSAmit Nischal .hw.init = &(struct clk_init_data){ 45453361cdSAmit Nischal .name = "gpu_cc_pll1", 46040184b7SDmitry Baryshkov .parent_data = &(const struct clk_parent_data){ 47040184b7SDmitry Baryshkov .fw_name = "bi_tcxo", .name = "bi_tcxo", 48040184b7SDmitry Baryshkov }, 49453361cdSAmit Nischal .num_parents = 1, 50453361cdSAmit Nischal .ops = &clk_alpha_pll_fabia_ops, 51453361cdSAmit Nischal }, 52453361cdSAmit Nischal }, 53453361cdSAmit Nischal }; 54453361cdSAmit Nischal 55040184b7SDmitry Baryshkov static const struct parent_map gpu_cc_parent_map_0[] = { 56040184b7SDmitry Baryshkov { P_BI_TCXO, 0 }, 57040184b7SDmitry Baryshkov { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 58040184b7SDmitry Baryshkov { P_GPLL0_OUT_MAIN, 5 }, 59040184b7SDmitry Baryshkov { P_GPLL0_OUT_MAIN_DIV, 6 }, 60040184b7SDmitry Baryshkov }; 61040184b7SDmitry Baryshkov 62040184b7SDmitry Baryshkov static const struct clk_parent_data gpu_cc_parent_data_0[] = { 63040184b7SDmitry Baryshkov { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 64040184b7SDmitry Baryshkov { .hw = &gpu_cc_pll1.clkr.hw }, 65040184b7SDmitry Baryshkov { .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" }, 66040184b7SDmitry Baryshkov { .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" }, 67040184b7SDmitry Baryshkov }; 68040184b7SDmitry Baryshkov 69453361cdSAmit Nischal static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 70453361cdSAmit Nischal F(19200000, P_BI_TCXO, 1, 0, 0), 71453361cdSAmit Nischal F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), 72453361cdSAmit Nischal F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), 73453361cdSAmit Nischal { } 74453361cdSAmit Nischal }; 75453361cdSAmit Nischal 76453361cdSAmit Nischal static struct clk_rcg2 gpu_cc_gmu_clk_src = { 77453361cdSAmit Nischal .cmd_rcgr = 0x1120, 78453361cdSAmit Nischal .mnd_width = 0, 79453361cdSAmit Nischal .hid_width = 5, 80453361cdSAmit Nischal .parent_map = gpu_cc_parent_map_0, 81453361cdSAmit Nischal .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 82453361cdSAmit Nischal .clkr.hw.init = &(struct clk_init_data){ 83453361cdSAmit Nischal .name = "gpu_cc_gmu_clk_src", 84040184b7SDmitry Baryshkov .parent_data = gpu_cc_parent_data_0, 85040184b7SDmitry Baryshkov .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 86453361cdSAmit Nischal .ops = &clk_rcg2_shared_ops, 87453361cdSAmit Nischal }, 88453361cdSAmit Nischal }; 89453361cdSAmit Nischal 90453361cdSAmit Nischal static struct clk_branch gpu_cc_cx_gmu_clk = { 91453361cdSAmit Nischal .halt_reg = 0x1098, 92453361cdSAmit Nischal .halt_check = BRANCH_HALT, 93453361cdSAmit Nischal .clkr = { 94453361cdSAmit Nischal .enable_reg = 0x1098, 95453361cdSAmit Nischal .enable_mask = BIT(0), 96453361cdSAmit Nischal .hw.init = &(struct clk_init_data){ 97453361cdSAmit Nischal .name = "gpu_cc_cx_gmu_clk", 98040184b7SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 99040184b7SDmitry Baryshkov &gpu_cc_gmu_clk_src.clkr.hw, 100453361cdSAmit Nischal }, 101453361cdSAmit Nischal .num_parents = 1, 102453361cdSAmit Nischal .flags = CLK_SET_RATE_PARENT, 103453361cdSAmit Nischal .ops = &clk_branch2_ops, 104453361cdSAmit Nischal }, 105453361cdSAmit Nischal }, 106453361cdSAmit Nischal }; 107453361cdSAmit Nischal 108453361cdSAmit Nischal static struct clk_branch gpu_cc_cxo_clk = { 109453361cdSAmit Nischal .halt_reg = 0x109c, 110453361cdSAmit Nischal .halt_check = BRANCH_HALT, 111453361cdSAmit Nischal .clkr = { 112453361cdSAmit Nischal .enable_reg = 0x109c, 113453361cdSAmit Nischal .enable_mask = BIT(0), 114453361cdSAmit Nischal .hw.init = &(struct clk_init_data){ 115453361cdSAmit Nischal .name = "gpu_cc_cxo_clk", 116453361cdSAmit Nischal .ops = &clk_branch2_ops, 117453361cdSAmit Nischal }, 118453361cdSAmit Nischal }, 119453361cdSAmit Nischal }; 120453361cdSAmit Nischal 121453361cdSAmit Nischal static struct gdsc gpu_cx_gdsc = { 122453361cdSAmit Nischal .gdscr = 0x106c, 123453361cdSAmit Nischal .gds_hw_ctrl = 0x1540, 124453361cdSAmit Nischal .pd = { 125453361cdSAmit Nischal .name = "gpu_cx_gdsc", 126453361cdSAmit Nischal }, 127453361cdSAmit Nischal .pwrsts = PWRSTS_OFF_ON, 128453361cdSAmit Nischal .flags = VOTABLE, 129453361cdSAmit Nischal }; 130453361cdSAmit Nischal 131453361cdSAmit Nischal static struct gdsc gpu_gx_gdsc = { 132453361cdSAmit Nischal .gdscr = 0x100c, 133453361cdSAmit Nischal .clamp_io_ctrl = 0x1508, 134453361cdSAmit Nischal .pd = { 135453361cdSAmit Nischal .name = "gpu_gx_gdsc", 1360638226dSJonathan Marek .power_on = gdsc_gx_do_nothing_enable, 137453361cdSAmit Nischal }, 138453361cdSAmit Nischal .pwrsts = PWRSTS_OFF_ON, 139453361cdSAmit Nischal .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, 140453361cdSAmit Nischal }; 141453361cdSAmit Nischal 142453361cdSAmit Nischal static struct clk_regmap *gpu_cc_sdm845_clocks[] = { 143453361cdSAmit Nischal [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 144453361cdSAmit Nischal [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 145453361cdSAmit Nischal [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 146453361cdSAmit Nischal [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 147453361cdSAmit Nischal }; 148453361cdSAmit Nischal 149453361cdSAmit Nischal static struct gdsc *gpu_cc_sdm845_gdscs[] = { 150453361cdSAmit Nischal [GPU_CX_GDSC] = &gpu_cx_gdsc, 151453361cdSAmit Nischal [GPU_GX_GDSC] = &gpu_gx_gdsc, 152453361cdSAmit Nischal }; 153453361cdSAmit Nischal 154453361cdSAmit Nischal static const struct regmap_config gpu_cc_sdm845_regmap_config = { 155453361cdSAmit Nischal .reg_bits = 32, 156453361cdSAmit Nischal .reg_stride = 4, 157453361cdSAmit Nischal .val_bits = 32, 158453361cdSAmit Nischal .max_register = 0x8008, 159453361cdSAmit Nischal .fast_io = true, 160453361cdSAmit Nischal }; 161453361cdSAmit Nischal 162453361cdSAmit Nischal static const struct qcom_cc_desc gpu_cc_sdm845_desc = { 163453361cdSAmit Nischal .config = &gpu_cc_sdm845_regmap_config, 164453361cdSAmit Nischal .clks = gpu_cc_sdm845_clocks, 165453361cdSAmit Nischal .num_clks = ARRAY_SIZE(gpu_cc_sdm845_clocks), 166453361cdSAmit Nischal .gdscs = gpu_cc_sdm845_gdscs, 167453361cdSAmit Nischal .num_gdscs = ARRAY_SIZE(gpu_cc_sdm845_gdscs), 168453361cdSAmit Nischal }; 169453361cdSAmit Nischal 170453361cdSAmit Nischal static const struct of_device_id gpu_cc_sdm845_match_table[] = { 171453361cdSAmit Nischal { .compatible = "qcom,sdm845-gpucc" }, 172453361cdSAmit Nischal { } 173453361cdSAmit Nischal }; 174453361cdSAmit Nischal MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table); 175453361cdSAmit Nischal 176453361cdSAmit Nischal static int gpu_cc_sdm845_probe(struct platform_device *pdev) 177453361cdSAmit Nischal { 178453361cdSAmit Nischal struct regmap *regmap; 179453361cdSAmit Nischal unsigned int value, mask; 180453361cdSAmit Nischal 181453361cdSAmit Nischal regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc); 182453361cdSAmit Nischal if (IS_ERR(regmap)) 183453361cdSAmit Nischal return PTR_ERR(regmap); 184453361cdSAmit Nischal 185453361cdSAmit Nischal clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 186453361cdSAmit Nischal 187453361cdSAmit Nischal /* 188453361cdSAmit Nischal * Configure gpu_cc_cx_gmu_clk with recommended 189453361cdSAmit Nischal * wakeup/sleep settings 190453361cdSAmit Nischal */ 191453361cdSAmit Nischal mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT; 192453361cdSAmit Nischal mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; 193453361cdSAmit Nischal value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; 194453361cdSAmit Nischal regmap_update_bits(regmap, 0x1098, mask, value); 195453361cdSAmit Nischal 196453361cdSAmit Nischal /* Configure clk_dis_wait for gpu_cx_gdsc */ 197453361cdSAmit Nischal regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK, 198453361cdSAmit Nischal 8 << CLK_DIS_WAIT_SHIFT); 199453361cdSAmit Nischal 200453361cdSAmit Nischal return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap); 201453361cdSAmit Nischal } 202453361cdSAmit Nischal 203453361cdSAmit Nischal static struct platform_driver gpu_cc_sdm845_driver = { 204453361cdSAmit Nischal .probe = gpu_cc_sdm845_probe, 205453361cdSAmit Nischal .driver = { 206453361cdSAmit Nischal .name = "sdm845-gpucc", 207453361cdSAmit Nischal .of_match_table = gpu_cc_sdm845_match_table, 208*99c0f7d3SAbel Vesa .sync_state = clk_sync_state_disable_unused, 209453361cdSAmit Nischal }, 210453361cdSAmit Nischal }; 211453361cdSAmit Nischal 212453361cdSAmit Nischal static int __init gpu_cc_sdm845_init(void) 213453361cdSAmit Nischal { 214453361cdSAmit Nischal return platform_driver_register(&gpu_cc_sdm845_driver); 215453361cdSAmit Nischal } 216453361cdSAmit Nischal subsys_initcall(gpu_cc_sdm845_init); 217453361cdSAmit Nischal 218453361cdSAmit Nischal static void __exit gpu_cc_sdm845_exit(void) 219453361cdSAmit Nischal { 220453361cdSAmit Nischal platform_driver_unregister(&gpu_cc_sdm845_driver); 221453361cdSAmit Nischal } 222453361cdSAmit Nischal module_exit(gpu_cc_sdm845_exit); 223453361cdSAmit Nischal 224453361cdSAmit Nischal MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver"); 225453361cdSAmit Nischal MODULE_LICENSE("GPL v2"); 226