1453361cdSAmit Nischal // SPDX-License-Identifier: GPL-2.0 2453361cdSAmit Nischal /* 3453361cdSAmit Nischal * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4453361cdSAmit Nischal */ 5453361cdSAmit Nischal 6453361cdSAmit Nischal #include <linux/clk-provider.h> 7453361cdSAmit Nischal #include <linux/module.h> 8453361cdSAmit Nischal #include <linux/platform_device.h> 9453361cdSAmit Nischal #include <linux/regmap.h> 10453361cdSAmit Nischal 11453361cdSAmit Nischal #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12453361cdSAmit Nischal 13453361cdSAmit Nischal #include "common.h" 14453361cdSAmit Nischal #include "clk-alpha-pll.h" 15453361cdSAmit Nischal #include "clk-branch.h" 16453361cdSAmit Nischal #include "clk-pll.h" 17453361cdSAmit Nischal #include "clk-rcg.h" 18453361cdSAmit Nischal #include "clk-regmap.h" 19453361cdSAmit Nischal #include "gdsc.h" 20453361cdSAmit Nischal 21453361cdSAmit Nischal #define CX_GMU_CBCR_SLEEP_MASK 0xf 22453361cdSAmit Nischal #define CX_GMU_CBCR_SLEEP_SHIFT 4 23453361cdSAmit Nischal #define CX_GMU_CBCR_WAKE_MASK 0xf 24453361cdSAmit Nischal #define CX_GMU_CBCR_WAKE_SHIFT 8 25453361cdSAmit Nischal #define CLK_DIS_WAIT_SHIFT 12 26453361cdSAmit Nischal #define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT) 27453361cdSAmit Nischal 28453361cdSAmit Nischal enum { 29453361cdSAmit Nischal P_BI_TCXO, 30453361cdSAmit Nischal P_CORE_BI_PLL_TEST_SE, 31453361cdSAmit Nischal P_GPLL0_OUT_MAIN, 32453361cdSAmit Nischal P_GPLL0_OUT_MAIN_DIV, 33453361cdSAmit Nischal P_GPU_CC_PLL1_OUT_MAIN, 34453361cdSAmit Nischal }; 35453361cdSAmit Nischal 36453361cdSAmit Nischal static const struct alpha_pll_config gpu_cc_pll1_config = { 37453361cdSAmit Nischal .l = 0x1a, 38453361cdSAmit Nischal .alpha = 0xaab, 39453361cdSAmit Nischal }; 40453361cdSAmit Nischal 41453361cdSAmit Nischal static struct clk_alpha_pll gpu_cc_pll1 = { 42453361cdSAmit Nischal .offset = 0x100, 43453361cdSAmit Nischal .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 44453361cdSAmit Nischal .clkr = { 45453361cdSAmit Nischal .hw.init = &(struct clk_init_data){ 46453361cdSAmit Nischal .name = "gpu_cc_pll1", 47*040184b7SDmitry Baryshkov .parent_data = &(const struct clk_parent_data){ 48*040184b7SDmitry Baryshkov .fw_name = "bi_tcxo", .name = "bi_tcxo", 49*040184b7SDmitry Baryshkov }, 50453361cdSAmit Nischal .num_parents = 1, 51453361cdSAmit Nischal .ops = &clk_alpha_pll_fabia_ops, 52453361cdSAmit Nischal }, 53453361cdSAmit Nischal }, 54453361cdSAmit Nischal }; 55453361cdSAmit Nischal 56*040184b7SDmitry Baryshkov static const struct parent_map gpu_cc_parent_map_0[] = { 57*040184b7SDmitry Baryshkov { P_BI_TCXO, 0 }, 58*040184b7SDmitry Baryshkov { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 59*040184b7SDmitry Baryshkov { P_GPLL0_OUT_MAIN, 5 }, 60*040184b7SDmitry Baryshkov { P_GPLL0_OUT_MAIN_DIV, 6 }, 61*040184b7SDmitry Baryshkov { P_CORE_BI_PLL_TEST_SE, 7 }, 62*040184b7SDmitry Baryshkov }; 63*040184b7SDmitry Baryshkov 64*040184b7SDmitry Baryshkov static const struct clk_parent_data gpu_cc_parent_data_0[] = { 65*040184b7SDmitry Baryshkov { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 66*040184b7SDmitry Baryshkov { .hw = &gpu_cc_pll1.clkr.hw }, 67*040184b7SDmitry Baryshkov { .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" }, 68*040184b7SDmitry Baryshkov { .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" }, 69*040184b7SDmitry Baryshkov { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 70*040184b7SDmitry Baryshkov }; 71*040184b7SDmitry Baryshkov 72453361cdSAmit Nischal static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 73453361cdSAmit Nischal F(19200000, P_BI_TCXO, 1, 0, 0), 74453361cdSAmit Nischal F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), 75453361cdSAmit Nischal F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), 76453361cdSAmit Nischal { } 77453361cdSAmit Nischal }; 78453361cdSAmit Nischal 79453361cdSAmit Nischal static struct clk_rcg2 gpu_cc_gmu_clk_src = { 80453361cdSAmit Nischal .cmd_rcgr = 0x1120, 81453361cdSAmit Nischal .mnd_width = 0, 82453361cdSAmit Nischal .hid_width = 5, 83453361cdSAmit Nischal .parent_map = gpu_cc_parent_map_0, 84453361cdSAmit Nischal .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 85453361cdSAmit Nischal .clkr.hw.init = &(struct clk_init_data){ 86453361cdSAmit Nischal .name = "gpu_cc_gmu_clk_src", 87*040184b7SDmitry Baryshkov .parent_data = gpu_cc_parent_data_0, 88*040184b7SDmitry Baryshkov .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 89453361cdSAmit Nischal .ops = &clk_rcg2_shared_ops, 90453361cdSAmit Nischal }, 91453361cdSAmit Nischal }; 92453361cdSAmit Nischal 93453361cdSAmit Nischal static struct clk_branch gpu_cc_cx_gmu_clk = { 94453361cdSAmit Nischal .halt_reg = 0x1098, 95453361cdSAmit Nischal .halt_check = BRANCH_HALT, 96453361cdSAmit Nischal .clkr = { 97453361cdSAmit Nischal .enable_reg = 0x1098, 98453361cdSAmit Nischal .enable_mask = BIT(0), 99453361cdSAmit Nischal .hw.init = &(struct clk_init_data){ 100453361cdSAmit Nischal .name = "gpu_cc_cx_gmu_clk", 101*040184b7SDmitry Baryshkov .parent_hws = (const struct clk_hw*[]){ 102*040184b7SDmitry Baryshkov &gpu_cc_gmu_clk_src.clkr.hw, 103453361cdSAmit Nischal }, 104453361cdSAmit Nischal .num_parents = 1, 105453361cdSAmit Nischal .flags = CLK_SET_RATE_PARENT, 106453361cdSAmit Nischal .ops = &clk_branch2_ops, 107453361cdSAmit Nischal }, 108453361cdSAmit Nischal }, 109453361cdSAmit Nischal }; 110453361cdSAmit Nischal 111453361cdSAmit Nischal static struct clk_branch gpu_cc_cxo_clk = { 112453361cdSAmit Nischal .halt_reg = 0x109c, 113453361cdSAmit Nischal .halt_check = BRANCH_HALT, 114453361cdSAmit Nischal .clkr = { 115453361cdSAmit Nischal .enable_reg = 0x109c, 116453361cdSAmit Nischal .enable_mask = BIT(0), 117453361cdSAmit Nischal .hw.init = &(struct clk_init_data){ 118453361cdSAmit Nischal .name = "gpu_cc_cxo_clk", 119453361cdSAmit Nischal .ops = &clk_branch2_ops, 120453361cdSAmit Nischal }, 121453361cdSAmit Nischal }, 122453361cdSAmit Nischal }; 123453361cdSAmit Nischal 124453361cdSAmit Nischal static struct gdsc gpu_cx_gdsc = { 125453361cdSAmit Nischal .gdscr = 0x106c, 126453361cdSAmit Nischal .gds_hw_ctrl = 0x1540, 127453361cdSAmit Nischal .pd = { 128453361cdSAmit Nischal .name = "gpu_cx_gdsc", 129453361cdSAmit Nischal }, 130453361cdSAmit Nischal .pwrsts = PWRSTS_OFF_ON, 131453361cdSAmit Nischal .flags = VOTABLE, 132453361cdSAmit Nischal }; 133453361cdSAmit Nischal 134453361cdSAmit Nischal static struct gdsc gpu_gx_gdsc = { 135453361cdSAmit Nischal .gdscr = 0x100c, 136453361cdSAmit Nischal .clamp_io_ctrl = 0x1508, 137453361cdSAmit Nischal .pd = { 138453361cdSAmit Nischal .name = "gpu_gx_gdsc", 1390638226dSJonathan Marek .power_on = gdsc_gx_do_nothing_enable, 140453361cdSAmit Nischal }, 141453361cdSAmit Nischal .pwrsts = PWRSTS_OFF_ON, 142453361cdSAmit Nischal .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, 143453361cdSAmit Nischal }; 144453361cdSAmit Nischal 145453361cdSAmit Nischal static struct clk_regmap *gpu_cc_sdm845_clocks[] = { 146453361cdSAmit Nischal [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 147453361cdSAmit Nischal [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 148453361cdSAmit Nischal [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 149453361cdSAmit Nischal [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 150453361cdSAmit Nischal }; 151453361cdSAmit Nischal 152453361cdSAmit Nischal static struct gdsc *gpu_cc_sdm845_gdscs[] = { 153453361cdSAmit Nischal [GPU_CX_GDSC] = &gpu_cx_gdsc, 154453361cdSAmit Nischal [GPU_GX_GDSC] = &gpu_gx_gdsc, 155453361cdSAmit Nischal }; 156453361cdSAmit Nischal 157453361cdSAmit Nischal static const struct regmap_config gpu_cc_sdm845_regmap_config = { 158453361cdSAmit Nischal .reg_bits = 32, 159453361cdSAmit Nischal .reg_stride = 4, 160453361cdSAmit Nischal .val_bits = 32, 161453361cdSAmit Nischal .max_register = 0x8008, 162453361cdSAmit Nischal .fast_io = true, 163453361cdSAmit Nischal }; 164453361cdSAmit Nischal 165453361cdSAmit Nischal static const struct qcom_cc_desc gpu_cc_sdm845_desc = { 166453361cdSAmit Nischal .config = &gpu_cc_sdm845_regmap_config, 167453361cdSAmit Nischal .clks = gpu_cc_sdm845_clocks, 168453361cdSAmit Nischal .num_clks = ARRAY_SIZE(gpu_cc_sdm845_clocks), 169453361cdSAmit Nischal .gdscs = gpu_cc_sdm845_gdscs, 170453361cdSAmit Nischal .num_gdscs = ARRAY_SIZE(gpu_cc_sdm845_gdscs), 171453361cdSAmit Nischal }; 172453361cdSAmit Nischal 173453361cdSAmit Nischal static const struct of_device_id gpu_cc_sdm845_match_table[] = { 174453361cdSAmit Nischal { .compatible = "qcom,sdm845-gpucc" }, 175453361cdSAmit Nischal { } 176453361cdSAmit Nischal }; 177453361cdSAmit Nischal MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table); 178453361cdSAmit Nischal 179453361cdSAmit Nischal static int gpu_cc_sdm845_probe(struct platform_device *pdev) 180453361cdSAmit Nischal { 181453361cdSAmit Nischal struct regmap *regmap; 182453361cdSAmit Nischal unsigned int value, mask; 183453361cdSAmit Nischal 184453361cdSAmit Nischal regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc); 185453361cdSAmit Nischal if (IS_ERR(regmap)) 186453361cdSAmit Nischal return PTR_ERR(regmap); 187453361cdSAmit Nischal 188453361cdSAmit Nischal clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 189453361cdSAmit Nischal 190453361cdSAmit Nischal /* 191453361cdSAmit Nischal * Configure gpu_cc_cx_gmu_clk with recommended 192453361cdSAmit Nischal * wakeup/sleep settings 193453361cdSAmit Nischal */ 194453361cdSAmit Nischal mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT; 195453361cdSAmit Nischal mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; 196453361cdSAmit Nischal value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; 197453361cdSAmit Nischal regmap_update_bits(regmap, 0x1098, mask, value); 198453361cdSAmit Nischal 199453361cdSAmit Nischal /* Configure clk_dis_wait for gpu_cx_gdsc */ 200453361cdSAmit Nischal regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK, 201453361cdSAmit Nischal 8 << CLK_DIS_WAIT_SHIFT); 202453361cdSAmit Nischal 203453361cdSAmit Nischal return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap); 204453361cdSAmit Nischal } 205453361cdSAmit Nischal 206453361cdSAmit Nischal static struct platform_driver gpu_cc_sdm845_driver = { 207453361cdSAmit Nischal .probe = gpu_cc_sdm845_probe, 208453361cdSAmit Nischal .driver = { 209453361cdSAmit Nischal .name = "sdm845-gpucc", 210453361cdSAmit Nischal .of_match_table = gpu_cc_sdm845_match_table, 211453361cdSAmit Nischal }, 212453361cdSAmit Nischal }; 213453361cdSAmit Nischal 214453361cdSAmit Nischal static int __init gpu_cc_sdm845_init(void) 215453361cdSAmit Nischal { 216453361cdSAmit Nischal return platform_driver_register(&gpu_cc_sdm845_driver); 217453361cdSAmit Nischal } 218453361cdSAmit Nischal subsys_initcall(gpu_cc_sdm845_init); 219453361cdSAmit Nischal 220453361cdSAmit Nischal static void __exit gpu_cc_sdm845_exit(void) 221453361cdSAmit Nischal { 222453361cdSAmit Nischal platform_driver_unregister(&gpu_cc_sdm845_driver); 223453361cdSAmit Nischal } 224453361cdSAmit Nischal module_exit(gpu_cc_sdm845_exit); 225453361cdSAmit Nischal 226453361cdSAmit Nischal MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver"); 227453361cdSAmit Nischal MODULE_LICENSE("GPL v2"); 228