1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020, AngeloGioacchino Del Regno 5 * <angelogioacchino.delregno@somainline.org> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/err.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/regmap.h> 18 #include <linux/reset-controller.h> 19 #include <dt-bindings/clock/qcom,gpucc-sdm660.h> 20 21 #include "clk-alpha-pll.h" 22 #include "common.h" 23 #include "clk-regmap.h" 24 #include "clk-pll.h" 25 #include "clk-rcg.h" 26 #include "clk-branch.h" 27 #include "gdsc.h" 28 #include "reset.h" 29 30 enum { 31 P_GPU_XO, 32 P_CORE_BI_PLL_TEST_SE, 33 P_GPLL0_OUT_MAIN, 34 P_GPLL0_OUT_MAIN_DIV, 35 P_GPU_PLL0_PLL_OUT_MAIN, 36 P_GPU_PLL1_PLL_OUT_MAIN, 37 }; 38 39 static struct clk_branch gpucc_cxo_clk = { 40 .halt_reg = 0x1020, 41 .clkr = { 42 .enable_reg = 0x1020, 43 .enable_mask = BIT(0), 44 .hw.init = &(struct clk_init_data){ 45 .name = "gpucc_cxo_clk", 46 .parent_data = &(const struct clk_parent_data){ 47 .fw_name = "xo" 48 }, 49 .num_parents = 1, 50 .ops = &clk_branch2_ops, 51 .flags = CLK_IS_CRITICAL, 52 }, 53 }, 54 }; 55 56 static struct pll_vco gpu_vco[] = { 57 { 1000000000, 2000000000, 0 }, 58 { 500000000, 1000000000, 2 }, 59 { 250000000, 500000000, 3 }, 60 }; 61 62 static struct clk_alpha_pll gpu_pll0_pll_out_main = { 63 .offset = 0x0, 64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 65 .vco_table = gpu_vco, 66 .num_vco = ARRAY_SIZE(gpu_vco), 67 .clkr.hw.init = &(struct clk_init_data){ 68 .name = "gpu_pll0_pll_out_main", 69 .parent_data = &(const struct clk_parent_data){ 70 .hw = &gpucc_cxo_clk.clkr.hw, 71 }, 72 .num_parents = 1, 73 .ops = &clk_alpha_pll_ops, 74 }, 75 }; 76 77 static struct clk_alpha_pll gpu_pll1_pll_out_main = { 78 .offset = 0x40, 79 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 80 .vco_table = gpu_vco, 81 .num_vco = ARRAY_SIZE(gpu_vco), 82 .clkr.hw.init = &(struct clk_init_data){ 83 .name = "gpu_pll1_pll_out_main", 84 .parent_data = &(const struct clk_parent_data){ 85 .hw = &gpucc_cxo_clk.clkr.hw, 86 }, 87 .num_parents = 1, 88 .ops = &clk_alpha_pll_ops, 89 }, 90 }; 91 92 static const struct parent_map gpucc_parent_map_1[] = { 93 { P_GPU_XO, 0 }, 94 { P_GPU_PLL0_PLL_OUT_MAIN, 1 }, 95 { P_GPU_PLL1_PLL_OUT_MAIN, 3 }, 96 { P_GPLL0_OUT_MAIN, 5 }, 97 }; 98 99 static const struct clk_parent_data gpucc_parent_data_1[] = { 100 { .hw = &gpucc_cxo_clk.clkr.hw }, 101 { .hw = &gpu_pll0_pll_out_main.clkr.hw }, 102 { .hw = &gpu_pll1_pll_out_main.clkr.hw }, 103 { .fw_name = "gcc_gpu_gpll0_clk" }, 104 }; 105 106 static struct clk_rcg2_gfx3d gfx3d_clk_src = { 107 .div = 2, 108 .rcg = { 109 .cmd_rcgr = 0x1070, 110 .mnd_width = 0, 111 .hid_width = 5, 112 .parent_map = gpucc_parent_map_1, 113 .clkr.hw.init = &(struct clk_init_data){ 114 .name = "gfx3d_clk_src", 115 .parent_data = gpucc_parent_data_1, 116 .num_parents = ARRAY_SIZE(gpucc_parent_data_1), 117 .ops = &clk_gfx3d_ops, 118 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 119 }, 120 }, 121 .hws = (struct clk_hw*[]){ 122 &gpucc_cxo_clk.clkr.hw, 123 &gpu_pll0_pll_out_main.clkr.hw, 124 &gpu_pll1_pll_out_main.clkr.hw, 125 } 126 }; 127 128 static struct clk_branch gpucc_gfx3d_clk = { 129 .halt_reg = 0x1098, 130 .halt_check = BRANCH_HALT, 131 .hwcg_reg = 0x1098, 132 .hwcg_bit = 1, 133 .clkr = { 134 .enable_reg = 0x1098, 135 .enable_mask = BIT(0), 136 .hw.init = &(struct clk_init_data){ 137 .name = "gpucc_gfx3d_clk", 138 .parent_data = &(const struct clk_parent_data){ 139 .hw = &gfx3d_clk_src.rcg.clkr.hw, 140 }, 141 .num_parents = 1, 142 .ops = &clk_branch2_ops, 143 .flags = CLK_SET_RATE_PARENT, 144 }, 145 }, 146 }; 147 148 static const struct parent_map gpucc_parent_map_0[] = { 149 { P_GPU_XO, 0 }, 150 { P_GPLL0_OUT_MAIN, 5 }, 151 { P_GPLL0_OUT_MAIN_DIV, 6 }, 152 }; 153 154 static const struct clk_parent_data gpucc_parent_data_0[] = { 155 { .hw = &gpucc_cxo_clk.clkr.hw }, 156 { .fw_name = "gcc_gpu_gpll0_clk" }, 157 { .fw_name = "gcc_gpu_gpll0_div_clk" }, 158 }; 159 160 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { 161 F(19200000, P_GPU_XO, 1, 0, 0), 162 { } 163 }; 164 165 static struct clk_rcg2 rbbmtimer_clk_src = { 166 .cmd_rcgr = 0x10b0, 167 .mnd_width = 0, 168 .hid_width = 5, 169 .parent_map = gpucc_parent_map_0, 170 .freq_tbl = ftbl_rbbmtimer_clk_src, 171 .clkr.hw.init = &(struct clk_init_data){ 172 .name = "rbbmtimer_clk_src", 173 .parent_data = gpucc_parent_data_0, 174 .num_parents = ARRAY_SIZE(gpucc_parent_data_0), 175 .ops = &clk_rcg2_ops, 176 }, 177 }; 178 179 static const struct freq_tbl ftbl_rbcpr_clk_src[] = { 180 F(19200000, P_GPU_XO, 1, 0, 0), 181 F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), 182 { } 183 }; 184 185 static struct clk_rcg2 rbcpr_clk_src = { 186 .cmd_rcgr = 0x1030, 187 .mnd_width = 0, 188 .hid_width = 5, 189 .parent_map = gpucc_parent_map_0, 190 .freq_tbl = ftbl_rbcpr_clk_src, 191 .clkr.hw.init = &(struct clk_init_data){ 192 .name = "rbcpr_clk_src", 193 .parent_data = gpucc_parent_data_0, 194 .num_parents = ARRAY_SIZE(gpucc_parent_data_0), 195 .ops = &clk_rcg2_ops, 196 }, 197 }; 198 199 static struct clk_branch gpucc_rbbmtimer_clk = { 200 .halt_reg = 0x10d0, 201 .halt_check = BRANCH_HALT, 202 .clkr = { 203 .enable_reg = 0x10d0, 204 .enable_mask = BIT(0), 205 .hw.init = &(struct clk_init_data){ 206 .name = "gpucc_rbbmtimer_clk", 207 .parent_names = (const char *[]){ 208 "rbbmtimer_clk_src", 209 }, 210 .num_parents = 1, 211 .flags = CLK_SET_RATE_PARENT, 212 .ops = &clk_branch2_ops, 213 }, 214 }, 215 }; 216 217 static struct clk_branch gpucc_rbcpr_clk = { 218 .halt_reg = 0x1054, 219 .halt_check = BRANCH_HALT, 220 .clkr = { 221 .enable_reg = 0x1054, 222 .enable_mask = BIT(0), 223 .hw.init = &(struct clk_init_data){ 224 .name = "gpucc_rbcpr_clk", 225 .parent_names = (const char *[]){ 226 "rbcpr_clk_src", 227 }, 228 .num_parents = 1, 229 .flags = CLK_SET_RATE_PARENT, 230 .ops = &clk_branch2_ops, 231 }, 232 }, 233 }; 234 235 static struct gdsc gpu_cx_gdsc = { 236 .gdscr = 0x1004, 237 .gds_hw_ctrl = 0x1008, 238 .pd = { 239 .name = "gpu_cx", 240 }, 241 .pwrsts = PWRSTS_OFF_ON, 242 .flags = VOTABLE, 243 }; 244 245 static struct gdsc gpu_gx_gdsc = { 246 .gdscr = 0x1094, 247 .clamp_io_ctrl = 0x130, 248 .resets = (unsigned int []){ GPU_GX_BCR }, 249 .reset_count = 1, 250 .cxcs = (unsigned int []){ 0x1098 }, 251 .cxc_count = 1, 252 .pd = { 253 .name = "gpu_gx", 254 }, 255 .parent = &gpu_cx_gdsc.pd, 256 .pwrsts = PWRSTS_OFF | PWRSTS_ON | PWRSTS_RET, 257 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH, 258 }; 259 260 static struct gdsc *gpucc_sdm660_gdscs[] = { 261 [GPU_CX_GDSC] = &gpu_cx_gdsc, 262 [GPU_GX_GDSC] = &gpu_gx_gdsc, 263 }; 264 265 static const struct qcom_reset_map gpucc_sdm660_resets[] = { 266 [GPU_CX_BCR] = { 0x1000 }, 267 [RBCPR_BCR] = { 0x1050 }, 268 [GPU_GX_BCR] = { 0x1090 }, 269 [SPDM_BCR] = { 0x10E0 }, 270 }; 271 272 static struct clk_regmap *gpucc_sdm660_clocks[] = { 273 [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr, 274 [GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr, 275 [GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr, 276 [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr, 277 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 278 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 279 [GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr, 280 [GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr, 281 [GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr, 282 }; 283 284 static const struct regmap_config gpucc_660_regmap_config = { 285 .reg_bits = 32, 286 .reg_stride = 4, 287 .val_bits = 32, 288 .max_register = 0x9034, 289 .fast_io = true, 290 }; 291 292 static const struct qcom_cc_desc gpucc_sdm660_desc = { 293 .config = &gpucc_660_regmap_config, 294 .clks = gpucc_sdm660_clocks, 295 .num_clks = ARRAY_SIZE(gpucc_sdm660_clocks), 296 .resets = gpucc_sdm660_resets, 297 .num_resets = ARRAY_SIZE(gpucc_sdm660_resets), 298 .gdscs = gpucc_sdm660_gdscs, 299 .num_gdscs = ARRAY_SIZE(gpucc_sdm660_gdscs), 300 }; 301 302 static const struct of_device_id gpucc_sdm660_match_table[] = { 303 { .compatible = "qcom,gpucc-sdm660" }, 304 { .compatible = "qcom,gpucc-sdm630" }, 305 { } 306 }; 307 MODULE_DEVICE_TABLE(of, gpucc_sdm660_match_table); 308 309 static int gpucc_sdm660_probe(struct platform_device *pdev) 310 { 311 struct regmap *regmap; 312 struct alpha_pll_config gpu_pll_config = { 313 .config_ctl_val = 0x4001055b, 314 .alpha = 0xaaaaab00, 315 .alpha_en_mask = BIT(24), 316 .vco_val = 0x2 << 20, 317 .vco_mask = 0x3 << 20, 318 .main_output_mask = 0x1, 319 }; 320 321 regmap = qcom_cc_map(pdev, &gpucc_sdm660_desc); 322 if (IS_ERR(regmap)) 323 return PTR_ERR(regmap); 324 325 /* 800MHz configuration for GPU PLL0 */ 326 gpu_pll_config.l = 0x29; 327 gpu_pll_config.alpha_hi = 0xaa; 328 clk_alpha_pll_configure(&gpu_pll0_pll_out_main, regmap, &gpu_pll_config); 329 330 /* 740MHz configuration for GPU PLL1 */ 331 gpu_pll_config.l = 0x26; 332 gpu_pll_config.alpha_hi = 0x8a; 333 clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, &gpu_pll_config); 334 335 return qcom_cc_really_probe(pdev, &gpucc_sdm660_desc, regmap); 336 } 337 338 static struct platform_driver gpucc_sdm660_driver = { 339 .probe = gpucc_sdm660_probe, 340 .driver = { 341 .name = "gpucc-sdm660", 342 .of_match_table = gpucc_sdm660_match_table, 343 }, 344 }; 345 module_platform_driver(gpucc_sdm660_driver); 346 347 MODULE_DESCRIPTION("Qualcomm SDM630/SDM660 GPUCC Driver"); 348 MODULE_LICENSE("GPL v2"); 349