1*3e0f01d6STaniya Das // SPDX-License-Identifier: GPL-2.0-only 2*3e0f01d6STaniya Das /* 3*3e0f01d6STaniya Das * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4*3e0f01d6STaniya Das */ 5*3e0f01d6STaniya Das 6*3e0f01d6STaniya Das #include <linux/clk-provider.h> 7*3e0f01d6STaniya Das #include <linux/module.h> 8*3e0f01d6STaniya Das #include <linux/platform_device.h> 9*3e0f01d6STaniya Das #include <linux/regmap.h> 10*3e0f01d6STaniya Das 11*3e0f01d6STaniya Das #include <dt-bindings/clock/qcom,gpucc-sc7280.h> 12*3e0f01d6STaniya Das 13*3e0f01d6STaniya Das #include "clk-alpha-pll.h" 14*3e0f01d6STaniya Das #include "clk-branch.h" 15*3e0f01d6STaniya Das #include "clk-rcg.h" 16*3e0f01d6STaniya Das #include "clk-regmap-divider.h" 17*3e0f01d6STaniya Das #include "common.h" 18*3e0f01d6STaniya Das #include "reset.h" 19*3e0f01d6STaniya Das #include "gdsc.h" 20*3e0f01d6STaniya Das 21*3e0f01d6STaniya Das enum { 22*3e0f01d6STaniya Das P_BI_TCXO, 23*3e0f01d6STaniya Das P_GCC_GPU_GPLL0_CLK_SRC, 24*3e0f01d6STaniya Das P_GCC_GPU_GPLL0_DIV_CLK_SRC, 25*3e0f01d6STaniya Das P_GPU_CC_PLL0_OUT_MAIN, 26*3e0f01d6STaniya Das P_GPU_CC_PLL1_OUT_MAIN, 27*3e0f01d6STaniya Das }; 28*3e0f01d6STaniya Das 29*3e0f01d6STaniya Das static const struct pll_vco lucid_vco[] = { 30*3e0f01d6STaniya Das { 249600000, 2000000000, 0 }, 31*3e0f01d6STaniya Das }; 32*3e0f01d6STaniya Das 33*3e0f01d6STaniya Das static struct clk_alpha_pll gpu_cc_pll0 = { 34*3e0f01d6STaniya Das .offset = 0x0, 35*3e0f01d6STaniya Das .vco_table = lucid_vco, 36*3e0f01d6STaniya Das .num_vco = ARRAY_SIZE(lucid_vco), 37*3e0f01d6STaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 38*3e0f01d6STaniya Das .clkr = { 39*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 40*3e0f01d6STaniya Das .name = "gpu_cc_pll0", 41*3e0f01d6STaniya Das .parent_data = &(const struct clk_parent_data){ 42*3e0f01d6STaniya Das .fw_name = "bi_tcxo", 43*3e0f01d6STaniya Das }, 44*3e0f01d6STaniya Das .num_parents = 1, 45*3e0f01d6STaniya Das .ops = &clk_alpha_pll_lucid_ops, 46*3e0f01d6STaniya Das }, 47*3e0f01d6STaniya Das }, 48*3e0f01d6STaniya Das }; 49*3e0f01d6STaniya Das 50*3e0f01d6STaniya Das /* 500MHz Configuration */ 51*3e0f01d6STaniya Das static const struct alpha_pll_config gpu_cc_pll1_config = { 52*3e0f01d6STaniya Das .l = 0x1A, 53*3e0f01d6STaniya Das .alpha = 0xAAA, 54*3e0f01d6STaniya Das .config_ctl_val = 0x20485699, 55*3e0f01d6STaniya Das .config_ctl_hi_val = 0x00002261, 56*3e0f01d6STaniya Das .config_ctl_hi1_val = 0x329A299C, 57*3e0f01d6STaniya Das .user_ctl_val = 0x00000001, 58*3e0f01d6STaniya Das .user_ctl_hi_val = 0x00000805, 59*3e0f01d6STaniya Das .user_ctl_hi1_val = 0x00000000, 60*3e0f01d6STaniya Das }; 61*3e0f01d6STaniya Das 62*3e0f01d6STaniya Das static struct clk_alpha_pll gpu_cc_pll1 = { 63*3e0f01d6STaniya Das .offset = 0x100, 64*3e0f01d6STaniya Das .vco_table = lucid_vco, 65*3e0f01d6STaniya Das .num_vco = ARRAY_SIZE(lucid_vco), 66*3e0f01d6STaniya Das .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 67*3e0f01d6STaniya Das .clkr = { 68*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 69*3e0f01d6STaniya Das .name = "gpu_cc_pll1", 70*3e0f01d6STaniya Das .parent_data = &(const struct clk_parent_data){ 71*3e0f01d6STaniya Das .fw_name = "bi_tcxo", 72*3e0f01d6STaniya Das }, 73*3e0f01d6STaniya Das .num_parents = 1, 74*3e0f01d6STaniya Das .ops = &clk_alpha_pll_lucid_ops, 75*3e0f01d6STaniya Das }, 76*3e0f01d6STaniya Das }, 77*3e0f01d6STaniya Das }; 78*3e0f01d6STaniya Das 79*3e0f01d6STaniya Das static const struct parent_map gpu_cc_parent_map_0[] = { 80*3e0f01d6STaniya Das { P_BI_TCXO, 0 }, 81*3e0f01d6STaniya Das { P_GPU_CC_PLL0_OUT_MAIN, 1 }, 82*3e0f01d6STaniya Das { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 83*3e0f01d6STaniya Das { P_GCC_GPU_GPLL0_CLK_SRC, 5 }, 84*3e0f01d6STaniya Das { P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 }, 85*3e0f01d6STaniya Das }; 86*3e0f01d6STaniya Das 87*3e0f01d6STaniya Das static const struct clk_parent_data gpu_cc_parent_data_0[] = { 88*3e0f01d6STaniya Das { .fw_name = "bi_tcxo" }, 89*3e0f01d6STaniya Das { .hw = &gpu_cc_pll0.clkr.hw }, 90*3e0f01d6STaniya Das { .hw = &gpu_cc_pll1.clkr.hw }, 91*3e0f01d6STaniya Das { .fw_name = "gcc_gpu_gpll0_clk_src" }, 92*3e0f01d6STaniya Das { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, 93*3e0f01d6STaniya Das }; 94*3e0f01d6STaniya Das 95*3e0f01d6STaniya Das static const struct parent_map gpu_cc_parent_map_1[] = { 96*3e0f01d6STaniya Das { P_BI_TCXO, 0 }, 97*3e0f01d6STaniya Das { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 98*3e0f01d6STaniya Das { P_GCC_GPU_GPLL0_CLK_SRC, 5 }, 99*3e0f01d6STaniya Das { P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 }, 100*3e0f01d6STaniya Das }; 101*3e0f01d6STaniya Das 102*3e0f01d6STaniya Das static const struct clk_parent_data gpu_cc_parent_data_1[] = { 103*3e0f01d6STaniya Das { .fw_name = "bi_tcxo", }, 104*3e0f01d6STaniya Das { .hw = &gpu_cc_pll1.clkr.hw }, 105*3e0f01d6STaniya Das { .fw_name = "gcc_gpu_gpll0_clk_src", }, 106*3e0f01d6STaniya Das { .fw_name = "gcc_gpu_gpll0_div_clk_src", }, 107*3e0f01d6STaniya Das }; 108*3e0f01d6STaniya Das 109*3e0f01d6STaniya Das static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 110*3e0f01d6STaniya Das F(19200000, P_BI_TCXO, 1, 0, 0), 111*3e0f01d6STaniya Das F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0), 112*3e0f01d6STaniya Das F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), 113*3e0f01d6STaniya Das { } 114*3e0f01d6STaniya Das }; 115*3e0f01d6STaniya Das 116*3e0f01d6STaniya Das static struct clk_rcg2 gpu_cc_gmu_clk_src = { 117*3e0f01d6STaniya Das .cmd_rcgr = 0x1120, 118*3e0f01d6STaniya Das .mnd_width = 0, 119*3e0f01d6STaniya Das .hid_width = 5, 120*3e0f01d6STaniya Das .parent_map = gpu_cc_parent_map_0, 121*3e0f01d6STaniya Das .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 122*3e0f01d6STaniya Das .clkr.hw.init = &(struct clk_init_data){ 123*3e0f01d6STaniya Das .name = "gpu_cc_gmu_clk_src", 124*3e0f01d6STaniya Das .parent_data = gpu_cc_parent_data_0, 125*3e0f01d6STaniya Das .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 126*3e0f01d6STaniya Das .ops = &clk_rcg2_shared_ops, 127*3e0f01d6STaniya Das }, 128*3e0f01d6STaniya Das }; 129*3e0f01d6STaniya Das 130*3e0f01d6STaniya Das static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { 131*3e0f01d6STaniya Das F(150000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 2, 0, 0), 132*3e0f01d6STaniya Das F(240000000, P_GCC_GPU_GPLL0_CLK_SRC, 2.5, 0, 0), 133*3e0f01d6STaniya Das F(300000000, P_GCC_GPU_GPLL0_CLK_SRC, 2, 0, 0), 134*3e0f01d6STaniya Das { } 135*3e0f01d6STaniya Das }; 136*3e0f01d6STaniya Das 137*3e0f01d6STaniya Das static struct clk_rcg2 gpu_cc_hub_clk_src = { 138*3e0f01d6STaniya Das .cmd_rcgr = 0x117c, 139*3e0f01d6STaniya Das .mnd_width = 0, 140*3e0f01d6STaniya Das .hid_width = 5, 141*3e0f01d6STaniya Das .parent_map = gpu_cc_parent_map_1, 142*3e0f01d6STaniya Das .freq_tbl = ftbl_gpu_cc_hub_clk_src, 143*3e0f01d6STaniya Das .clkr.hw.init = &(struct clk_init_data){ 144*3e0f01d6STaniya Das .name = "gpu_cc_hub_clk_src", 145*3e0f01d6STaniya Das .parent_data = gpu_cc_parent_data_1, 146*3e0f01d6STaniya Das .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), 147*3e0f01d6STaniya Das .ops = &clk_rcg2_shared_ops, 148*3e0f01d6STaniya Das }, 149*3e0f01d6STaniya Das }; 150*3e0f01d6STaniya Das 151*3e0f01d6STaniya Das static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { 152*3e0f01d6STaniya Das .reg = 0x11c0, 153*3e0f01d6STaniya Das .shift = 0, 154*3e0f01d6STaniya Das .width = 4, 155*3e0f01d6STaniya Das .clkr.hw.init = &(struct clk_init_data) { 156*3e0f01d6STaniya Das .name = "gpu_cc_hub_ahb_div_clk_src", 157*3e0f01d6STaniya Das .parent_hws = (const struct clk_hw*[]){ 158*3e0f01d6STaniya Das &gpu_cc_hub_clk_src.clkr.hw, 159*3e0f01d6STaniya Das }, 160*3e0f01d6STaniya Das .num_parents = 1, 161*3e0f01d6STaniya Das .flags = CLK_SET_RATE_PARENT, 162*3e0f01d6STaniya Das .ops = &clk_regmap_div_ro_ops, 163*3e0f01d6STaniya Das }, 164*3e0f01d6STaniya Das }; 165*3e0f01d6STaniya Das 166*3e0f01d6STaniya Das static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { 167*3e0f01d6STaniya Das .reg = 0x11bc, 168*3e0f01d6STaniya Das .shift = 0, 169*3e0f01d6STaniya Das .width = 4, 170*3e0f01d6STaniya Das .clkr.hw.init = &(struct clk_init_data) { 171*3e0f01d6STaniya Das .name = "gpu_cc_hub_cx_int_div_clk_src", 172*3e0f01d6STaniya Das .parent_hws = (const struct clk_hw*[]){ 173*3e0f01d6STaniya Das &gpu_cc_hub_clk_src.clkr.hw, 174*3e0f01d6STaniya Das }, 175*3e0f01d6STaniya Das .num_parents = 1, 176*3e0f01d6STaniya Das .flags = CLK_SET_RATE_PARENT, 177*3e0f01d6STaniya Das .ops = &clk_regmap_div_ro_ops, 178*3e0f01d6STaniya Das }, 179*3e0f01d6STaniya Das }; 180*3e0f01d6STaniya Das 181*3e0f01d6STaniya Das static struct clk_branch gpu_cc_ahb_clk = { 182*3e0f01d6STaniya Das .halt_reg = 0x1078, 183*3e0f01d6STaniya Das .halt_check = BRANCH_HALT_DELAY, 184*3e0f01d6STaniya Das .clkr = { 185*3e0f01d6STaniya Das .enable_reg = 0x1078, 186*3e0f01d6STaniya Das .enable_mask = BIT(0), 187*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 188*3e0f01d6STaniya Das .name = "gpu_cc_ahb_clk", 189*3e0f01d6STaniya Das .parent_hws = (const struct clk_hw*[]){ 190*3e0f01d6STaniya Das &gpu_cc_hub_ahb_div_clk_src.clkr.hw, 191*3e0f01d6STaniya Das }, 192*3e0f01d6STaniya Das .num_parents = 1, 193*3e0f01d6STaniya Das .flags = CLK_SET_RATE_PARENT, 194*3e0f01d6STaniya Das .ops = &clk_branch2_ops, 195*3e0f01d6STaniya Das }, 196*3e0f01d6STaniya Das }, 197*3e0f01d6STaniya Das }; 198*3e0f01d6STaniya Das 199*3e0f01d6STaniya Das static struct clk_branch gpu_cc_crc_ahb_clk = { 200*3e0f01d6STaniya Das .halt_reg = 0x107c, 201*3e0f01d6STaniya Das .halt_check = BRANCH_HALT_VOTED, 202*3e0f01d6STaniya Das .clkr = { 203*3e0f01d6STaniya Das .enable_reg = 0x107c, 204*3e0f01d6STaniya Das .enable_mask = BIT(0), 205*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 206*3e0f01d6STaniya Das .name = "gpu_cc_crc_ahb_clk", 207*3e0f01d6STaniya Das .parent_hws = (const struct clk_hw*[]){ 208*3e0f01d6STaniya Das &gpu_cc_hub_ahb_div_clk_src.clkr.hw, 209*3e0f01d6STaniya Das }, 210*3e0f01d6STaniya Das .num_parents = 1, 211*3e0f01d6STaniya Das .flags = CLK_SET_RATE_PARENT, 212*3e0f01d6STaniya Das .ops = &clk_branch2_ops, 213*3e0f01d6STaniya Das }, 214*3e0f01d6STaniya Das }, 215*3e0f01d6STaniya Das }; 216*3e0f01d6STaniya Das 217*3e0f01d6STaniya Das static struct clk_branch gpu_cc_cx_gmu_clk = { 218*3e0f01d6STaniya Das .halt_reg = 0x1098, 219*3e0f01d6STaniya Das .halt_check = BRANCH_HALT, 220*3e0f01d6STaniya Das .clkr = { 221*3e0f01d6STaniya Das .enable_reg = 0x1098, 222*3e0f01d6STaniya Das .enable_mask = BIT(0), 223*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 224*3e0f01d6STaniya Das .name = "gpu_cc_cx_gmu_clk", 225*3e0f01d6STaniya Das .parent_hws = (const struct clk_hw*[]){ 226*3e0f01d6STaniya Das &gpu_cc_gmu_clk_src.clkr.hw, 227*3e0f01d6STaniya Das }, 228*3e0f01d6STaniya Das .num_parents = 1, 229*3e0f01d6STaniya Das .flags = CLK_SET_RATE_PARENT, 230*3e0f01d6STaniya Das .ops = &clk_branch2_aon_ops, 231*3e0f01d6STaniya Das }, 232*3e0f01d6STaniya Das }, 233*3e0f01d6STaniya Das }; 234*3e0f01d6STaniya Das 235*3e0f01d6STaniya Das static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { 236*3e0f01d6STaniya Das .halt_reg = 0x108c, 237*3e0f01d6STaniya Das .halt_check = BRANCH_HALT_VOTED, 238*3e0f01d6STaniya Das .clkr = { 239*3e0f01d6STaniya Das .enable_reg = 0x108c, 240*3e0f01d6STaniya Das .enable_mask = BIT(0), 241*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 242*3e0f01d6STaniya Das .name = "gpu_cc_cx_snoc_dvm_clk", 243*3e0f01d6STaniya Das .ops = &clk_branch2_ops, 244*3e0f01d6STaniya Das }, 245*3e0f01d6STaniya Das }, 246*3e0f01d6STaniya Das }; 247*3e0f01d6STaniya Das 248*3e0f01d6STaniya Das static struct clk_branch gpu_cc_cxo_aon_clk = { 249*3e0f01d6STaniya Das .halt_reg = 0x1004, 250*3e0f01d6STaniya Das .halt_check = BRANCH_HALT_VOTED, 251*3e0f01d6STaniya Das .clkr = { 252*3e0f01d6STaniya Das .enable_reg = 0x1004, 253*3e0f01d6STaniya Das .enable_mask = BIT(0), 254*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 255*3e0f01d6STaniya Das .name = "gpu_cc_cxo_aon_clk", 256*3e0f01d6STaniya Das .ops = &clk_branch2_ops, 257*3e0f01d6STaniya Das }, 258*3e0f01d6STaniya Das }, 259*3e0f01d6STaniya Das }; 260*3e0f01d6STaniya Das 261*3e0f01d6STaniya Das static struct clk_branch gpu_cc_cxo_clk = { 262*3e0f01d6STaniya Das .halt_reg = 0x109c, 263*3e0f01d6STaniya Das .halt_check = BRANCH_HALT, 264*3e0f01d6STaniya Das .clkr = { 265*3e0f01d6STaniya Das .enable_reg = 0x109c, 266*3e0f01d6STaniya Das .enable_mask = BIT(0), 267*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 268*3e0f01d6STaniya Das .name = "gpu_cc_cxo_clk", 269*3e0f01d6STaniya Das .ops = &clk_branch2_aon_ops, 270*3e0f01d6STaniya Das }, 271*3e0f01d6STaniya Das }, 272*3e0f01d6STaniya Das }; 273*3e0f01d6STaniya Das 274*3e0f01d6STaniya Das static struct clk_branch gpu_cc_gx_gmu_clk = { 275*3e0f01d6STaniya Das .halt_reg = 0x1064, 276*3e0f01d6STaniya Das .halt_check = BRANCH_HALT, 277*3e0f01d6STaniya Das .clkr = { 278*3e0f01d6STaniya Das .enable_reg = 0x1064, 279*3e0f01d6STaniya Das .enable_mask = BIT(0), 280*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 281*3e0f01d6STaniya Das .name = "gpu_cc_gx_gmu_clk", 282*3e0f01d6STaniya Das .parent_hws = (const struct clk_hw*[]){ 283*3e0f01d6STaniya Das &gpu_cc_gmu_clk_src.clkr.hw, 284*3e0f01d6STaniya Das }, 285*3e0f01d6STaniya Das .num_parents = 1, 286*3e0f01d6STaniya Das .flags = CLK_SET_RATE_PARENT, 287*3e0f01d6STaniya Das .ops = &clk_branch2_ops, 288*3e0f01d6STaniya Das }, 289*3e0f01d6STaniya Das }, 290*3e0f01d6STaniya Das }; 291*3e0f01d6STaniya Das 292*3e0f01d6STaniya Das static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { 293*3e0f01d6STaniya Das .halt_reg = 0x5000, 294*3e0f01d6STaniya Das .halt_check = BRANCH_VOTED, 295*3e0f01d6STaniya Das .clkr = { 296*3e0f01d6STaniya Das .enable_reg = 0x5000, 297*3e0f01d6STaniya Das .enable_mask = BIT(0), 298*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 299*3e0f01d6STaniya Das .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", 300*3e0f01d6STaniya Das .ops = &clk_branch2_ops, 301*3e0f01d6STaniya Das }, 302*3e0f01d6STaniya Das }, 303*3e0f01d6STaniya Das }; 304*3e0f01d6STaniya Das 305*3e0f01d6STaniya Das static struct clk_branch gpu_cc_hub_aon_clk = { 306*3e0f01d6STaniya Das .halt_reg = 0x1178, 307*3e0f01d6STaniya Das .halt_check = BRANCH_HALT, 308*3e0f01d6STaniya Das .clkr = { 309*3e0f01d6STaniya Das .enable_reg = 0x1178, 310*3e0f01d6STaniya Das .enable_mask = BIT(0), 311*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 312*3e0f01d6STaniya Das .name = "gpu_cc_hub_aon_clk", 313*3e0f01d6STaniya Das .parent_hws = (const struct clk_hw*[]){ 314*3e0f01d6STaniya Das &gpu_cc_hub_clk_src.clkr.hw, 315*3e0f01d6STaniya Das }, 316*3e0f01d6STaniya Das .num_parents = 1, 317*3e0f01d6STaniya Das .flags = CLK_SET_RATE_PARENT, 318*3e0f01d6STaniya Das .ops = &clk_branch2_aon_ops, 319*3e0f01d6STaniya Das }, 320*3e0f01d6STaniya Das }, 321*3e0f01d6STaniya Das }; 322*3e0f01d6STaniya Das 323*3e0f01d6STaniya Das static struct clk_branch gpu_cc_hub_cx_int_clk = { 324*3e0f01d6STaniya Das .halt_reg = 0x1204, 325*3e0f01d6STaniya Das .halt_check = BRANCH_HALT, 326*3e0f01d6STaniya Das .clkr = { 327*3e0f01d6STaniya Das .enable_reg = 0x1204, 328*3e0f01d6STaniya Das .enable_mask = BIT(0), 329*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 330*3e0f01d6STaniya Das .name = "gpu_cc_hub_cx_int_clk", 331*3e0f01d6STaniya Das .parent_hws = (const struct clk_hw*[]){ 332*3e0f01d6STaniya Das &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, 333*3e0f01d6STaniya Das }, 334*3e0f01d6STaniya Das .num_parents = 1, 335*3e0f01d6STaniya Das .flags = CLK_SET_RATE_PARENT, 336*3e0f01d6STaniya Das .ops = &clk_branch2_aon_ops, 337*3e0f01d6STaniya Das }, 338*3e0f01d6STaniya Das }, 339*3e0f01d6STaniya Das }; 340*3e0f01d6STaniya Das 341*3e0f01d6STaniya Das static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { 342*3e0f01d6STaniya Das .halt_reg = 0x802c, 343*3e0f01d6STaniya Das .halt_check = BRANCH_HALT_SKIP, 344*3e0f01d6STaniya Das .clkr = { 345*3e0f01d6STaniya Das .enable_reg = 0x802c, 346*3e0f01d6STaniya Das .enable_mask = BIT(0), 347*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 348*3e0f01d6STaniya Das .name = "gpu_cc_mnd1x_0_gfx3d_clk", 349*3e0f01d6STaniya Das .ops = &clk_branch2_ops, 350*3e0f01d6STaniya Das }, 351*3e0f01d6STaniya Das }, 352*3e0f01d6STaniya Das }; 353*3e0f01d6STaniya Das 354*3e0f01d6STaniya Das static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { 355*3e0f01d6STaniya Das .halt_reg = 0x8030, 356*3e0f01d6STaniya Das .halt_check = BRANCH_HALT_SKIP, 357*3e0f01d6STaniya Das .clkr = { 358*3e0f01d6STaniya Das .enable_reg = 0x8030, 359*3e0f01d6STaniya Das .enable_mask = BIT(0), 360*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 361*3e0f01d6STaniya Das .name = "gpu_cc_mnd1x_1_gfx3d_clk", 362*3e0f01d6STaniya Das .ops = &clk_branch2_ops, 363*3e0f01d6STaniya Das }, 364*3e0f01d6STaniya Das }, 365*3e0f01d6STaniya Das }; 366*3e0f01d6STaniya Das 367*3e0f01d6STaniya Das static struct clk_branch gpu_cc_sleep_clk = { 368*3e0f01d6STaniya Das .halt_reg = 0x1090, 369*3e0f01d6STaniya Das .halt_check = BRANCH_HALT_VOTED, 370*3e0f01d6STaniya Das .clkr = { 371*3e0f01d6STaniya Das .enable_reg = 0x1090, 372*3e0f01d6STaniya Das .enable_mask = BIT(0), 373*3e0f01d6STaniya Das .hw.init = &(struct clk_init_data){ 374*3e0f01d6STaniya Das .name = "gpu_cc_sleep_clk", 375*3e0f01d6STaniya Das .ops = &clk_branch2_ops, 376*3e0f01d6STaniya Das }, 377*3e0f01d6STaniya Das }, 378*3e0f01d6STaniya Das }; 379*3e0f01d6STaniya Das 380*3e0f01d6STaniya Das static struct gdsc cx_gdsc = { 381*3e0f01d6STaniya Das .gdscr = 0x106c, 382*3e0f01d6STaniya Das .gds_hw_ctrl = 0x1540, 383*3e0f01d6STaniya Das .pd = { 384*3e0f01d6STaniya Das .name = "cx_gdsc", 385*3e0f01d6STaniya Das }, 386*3e0f01d6STaniya Das .pwrsts = PWRSTS_OFF_ON, 387*3e0f01d6STaniya Das .flags = VOTABLE | RETAIN_FF_ENABLE, 388*3e0f01d6STaniya Das }; 389*3e0f01d6STaniya Das 390*3e0f01d6STaniya Das static struct gdsc gx_gdsc = { 391*3e0f01d6STaniya Das .gdscr = 0x100c, 392*3e0f01d6STaniya Das .clamp_io_ctrl = 0x1508, 393*3e0f01d6STaniya Das .pd = { 394*3e0f01d6STaniya Das .name = "gx_gdsc", 395*3e0f01d6STaniya Das .power_on = gdsc_gx_do_nothing_enable, 396*3e0f01d6STaniya Das }, 397*3e0f01d6STaniya Das .pwrsts = PWRSTS_OFF_ON, 398*3e0f01d6STaniya Das .flags = CLAMP_IO | RETAIN_FF_ENABLE, 399*3e0f01d6STaniya Das }; 400*3e0f01d6STaniya Das 401*3e0f01d6STaniya Das static struct gdsc *gpu_cc_sc7180_gdscs[] = { 402*3e0f01d6STaniya Das [GPU_CC_CX_GDSC] = &cx_gdsc, 403*3e0f01d6STaniya Das [GPU_CC_GX_GDSC] = &gx_gdsc, 404*3e0f01d6STaniya Das }; 405*3e0f01d6STaniya Das 406*3e0f01d6STaniya Das static struct clk_regmap *gpu_cc_sc7280_clocks[] = { 407*3e0f01d6STaniya Das [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, 408*3e0f01d6STaniya Das [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, 409*3e0f01d6STaniya Das [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 410*3e0f01d6STaniya Das [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, 411*3e0f01d6STaniya Das [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, 412*3e0f01d6STaniya Das [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 413*3e0f01d6STaniya Das [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 414*3e0f01d6STaniya Das [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, 415*3e0f01d6STaniya Das [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, 416*3e0f01d6STaniya Das [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, 417*3e0f01d6STaniya Das [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, 418*3e0f01d6STaniya Das [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, 419*3e0f01d6STaniya Das [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, 420*3e0f01d6STaniya Das [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, 421*3e0f01d6STaniya Das [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, 422*3e0f01d6STaniya Das [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, 423*3e0f01d6STaniya Das [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, 424*3e0f01d6STaniya Das [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 425*3e0f01d6STaniya Das [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, 426*3e0f01d6STaniya Das }; 427*3e0f01d6STaniya Das 428*3e0f01d6STaniya Das static const struct regmap_config gpu_cc_sc7280_regmap_config = { 429*3e0f01d6STaniya Das .reg_bits = 32, 430*3e0f01d6STaniya Das .reg_stride = 4, 431*3e0f01d6STaniya Das .val_bits = 32, 432*3e0f01d6STaniya Das .max_register = 0x8030, 433*3e0f01d6STaniya Das .fast_io = true, 434*3e0f01d6STaniya Das }; 435*3e0f01d6STaniya Das 436*3e0f01d6STaniya Das static const struct qcom_cc_desc gpu_cc_sc7280_desc = { 437*3e0f01d6STaniya Das .config = &gpu_cc_sc7280_regmap_config, 438*3e0f01d6STaniya Das .clks = gpu_cc_sc7280_clocks, 439*3e0f01d6STaniya Das .num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks), 440*3e0f01d6STaniya Das .gdscs = gpu_cc_sc7180_gdscs, 441*3e0f01d6STaniya Das .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs), 442*3e0f01d6STaniya Das }; 443*3e0f01d6STaniya Das 444*3e0f01d6STaniya Das static const struct of_device_id gpu_cc_sc7280_match_table[] = { 445*3e0f01d6STaniya Das { .compatible = "qcom,sc7280-gpucc" }, 446*3e0f01d6STaniya Das { } 447*3e0f01d6STaniya Das }; 448*3e0f01d6STaniya Das MODULE_DEVICE_TABLE(of, gpu_cc_sc7280_match_table); 449*3e0f01d6STaniya Das 450*3e0f01d6STaniya Das static int gpu_cc_sc7280_probe(struct platform_device *pdev) 451*3e0f01d6STaniya Das { 452*3e0f01d6STaniya Das struct regmap *regmap; 453*3e0f01d6STaniya Das 454*3e0f01d6STaniya Das regmap = qcom_cc_map(pdev, &gpu_cc_sc7280_desc); 455*3e0f01d6STaniya Das if (IS_ERR(regmap)) 456*3e0f01d6STaniya Das return PTR_ERR(regmap); 457*3e0f01d6STaniya Das 458*3e0f01d6STaniya Das clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 459*3e0f01d6STaniya Das 460*3e0f01d6STaniya Das /* 461*3e0f01d6STaniya Das * Keep the clocks always-ON 462*3e0f01d6STaniya Das * GPU_CC_CB_CLK, GPUCC_CX_GMU_CLK 463*3e0f01d6STaniya Das */ 464*3e0f01d6STaniya Das regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); 465*3e0f01d6STaniya Das regmap_update_bits(regmap, 0x1098, BIT(0), BIT(0)); 466*3e0f01d6STaniya Das 467*3e0f01d6STaniya Das return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap); 468*3e0f01d6STaniya Das } 469*3e0f01d6STaniya Das 470*3e0f01d6STaniya Das static struct platform_driver gpu_cc_sc7280_driver = { 471*3e0f01d6STaniya Das .probe = gpu_cc_sc7280_probe, 472*3e0f01d6STaniya Das .driver = { 473*3e0f01d6STaniya Das .name = "gpu_cc-sc7280", 474*3e0f01d6STaniya Das .of_match_table = gpu_cc_sc7280_match_table, 475*3e0f01d6STaniya Das }, 476*3e0f01d6STaniya Das }; 477*3e0f01d6STaniya Das 478*3e0f01d6STaniya Das static int __init gpu_cc_sc7280_init(void) 479*3e0f01d6STaniya Das { 480*3e0f01d6STaniya Das return platform_driver_register(&gpu_cc_sc7280_driver); 481*3e0f01d6STaniya Das } 482*3e0f01d6STaniya Das subsys_initcall(gpu_cc_sc7280_init); 483*3e0f01d6STaniya Das 484*3e0f01d6STaniya Das static void __exit gpu_cc_sc7280_exit(void) 485*3e0f01d6STaniya Das { 486*3e0f01d6STaniya Das platform_driver_unregister(&gpu_cc_sc7280_driver); 487*3e0f01d6STaniya Das } 488*3e0f01d6STaniya Das module_exit(gpu_cc_sc7280_exit); 489*3e0f01d6STaniya Das 490*3e0f01d6STaniya Das MODULE_DESCRIPTION("QTI GPU_CC SC7280 Driver"); 491*3e0f01d6STaniya Das MODULE_LICENSE("GPL v2"); 492