xref: /openbmc/linux/drivers/clk/qcom/gpucc-sc7180.c (revision 745ff069) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10 
11 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
12 
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-rcg.h"
16 #include "clk-regmap.h"
17 #include "common.h"
18 #include "gdsc.h"
19 
20 #define CX_GMU_CBCR_SLEEP_MASK		0xF
21 #define CX_GMU_CBCR_SLEEP_SHIFT		4
22 #define CX_GMU_CBCR_WAKE_MASK		0xF
23 #define CX_GMU_CBCR_WAKE_SHIFT		8
24 #define CLK_DIS_WAIT_SHIFT		12
25 #define CLK_DIS_WAIT_MASK		(0xf << CLK_DIS_WAIT_SHIFT)
26 
27 enum {
28 	P_BI_TCXO,
29 	P_CORE_BI_PLL_TEST_SE,
30 	P_GPLL0_OUT_MAIN,
31 	P_GPLL0_OUT_MAIN_DIV,
32 	P_GPU_CC_PLL1_OUT_EVEN,
33 	P_GPU_CC_PLL1_OUT_MAIN,
34 	P_GPU_CC_PLL1_OUT_ODD,
35 };
36 
37 static const struct pll_vco fabia_vco[] = {
38 	{ 249600000, 2000000000, 0 },
39 };
40 
41 static struct clk_alpha_pll gpu_cc_pll1 = {
42 	.offset = 0x100,
43 	.vco_table = fabia_vco,
44 	.num_vco = ARRAY_SIZE(fabia_vco),
45 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
46 	.clkr = {
47 		.hw.init = &(struct clk_init_data){
48 			.name = "gpu_cc_pll1",
49 			.parent_data =  &(const struct clk_parent_data){
50 				.fw_name = "bi_tcxo",
51 			},
52 			.num_parents = 1,
53 			.ops = &clk_alpha_pll_fabia_ops,
54 		},
55 	},
56 };
57 
58 static const struct parent_map gpu_cc_parent_map_0[] = {
59 	{ P_BI_TCXO, 0 },
60 	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
61 	{ P_GPLL0_OUT_MAIN, 5 },
62 	{ P_GPLL0_OUT_MAIN_DIV, 6 },
63 	{ P_CORE_BI_PLL_TEST_SE, 7 },
64 };
65 
66 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
67 	{ .fw_name = "bi_tcxo" },
68 	{ .hw = &gpu_cc_pll1.clkr.hw },
69 	{ .fw_name = "gcc_gpu_gpll0_clk_src" },
70 	{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
71 	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
72 };
73 
74 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
75 	F(19200000, P_BI_TCXO, 1, 0, 0),
76 	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
77 	{ }
78 };
79 
80 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
81 	.cmd_rcgr = 0x1120,
82 	.mnd_width = 0,
83 	.hid_width = 5,
84 	.parent_map = gpu_cc_parent_map_0,
85 	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
86 	.clkr.hw.init = &(struct clk_init_data){
87 		.name = "gpu_cc_gmu_clk_src",
88 		.parent_data = gpu_cc_parent_data_0,
89 		.num_parents = 5,
90 		.flags = CLK_SET_RATE_PARENT,
91 		.ops = &clk_rcg2_shared_ops,
92 	},
93 };
94 
95 static struct clk_branch gpu_cc_crc_ahb_clk = {
96 	.halt_reg = 0x107c,
97 	.halt_check = BRANCH_HALT_DELAY,
98 	.clkr = {
99 		.enable_reg = 0x107c,
100 		.enable_mask = BIT(0),
101 		.hw.init = &(struct clk_init_data){
102 			.name = "gpu_cc_crc_ahb_clk",
103 			.ops = &clk_branch2_ops,
104 		},
105 	},
106 };
107 
108 static struct clk_branch gpu_cc_cx_gmu_clk = {
109 	.halt_reg = 0x1098,
110 	.halt_check = BRANCH_HALT,
111 	.clkr = {
112 		.enable_reg = 0x1098,
113 		.enable_mask = BIT(0),
114 		.hw.init = &(struct clk_init_data){
115 			.name = "gpu_cc_cx_gmu_clk",
116 			.parent_data =  &(const struct clk_parent_data){
117 				.hw = &gpu_cc_gmu_clk_src.clkr.hw,
118 			},
119 			.num_parents = 1,
120 			.flags = CLK_SET_RATE_PARENT,
121 			.ops = &clk_branch2_ops,
122 		},
123 	},
124 };
125 
126 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
127 	.halt_reg = 0x108c,
128 	.halt_check = BRANCH_HALT_DELAY,
129 	.clkr = {
130 		.enable_reg = 0x108c,
131 		.enable_mask = BIT(0),
132 		.hw.init = &(struct clk_init_data){
133 			.name = "gpu_cc_cx_snoc_dvm_clk",
134 			.ops = &clk_branch2_ops,
135 		},
136 	},
137 };
138 
139 static struct clk_branch gpu_cc_cxo_aon_clk = {
140 	.halt_reg = 0x1004,
141 	.halt_check = BRANCH_HALT_DELAY,
142 	.clkr = {
143 		.enable_reg = 0x1004,
144 		.enable_mask = BIT(0),
145 		.hw.init = &(struct clk_init_data){
146 			.name = "gpu_cc_cxo_aon_clk",
147 			.ops = &clk_branch2_ops,
148 		},
149 	},
150 };
151 
152 static struct clk_branch gpu_cc_cxo_clk = {
153 	.halt_reg = 0x109c,
154 	.halt_check = BRANCH_HALT,
155 	.clkr = {
156 		.enable_reg = 0x109c,
157 		.enable_mask = BIT(0),
158 		.hw.init = &(struct clk_init_data){
159 			.name = "gpu_cc_cxo_clk",
160 			.ops = &clk_branch2_ops,
161 		},
162 	},
163 };
164 
165 static struct gdsc cx_gdsc = {
166 	.gdscr = 0x106c,
167 	.gds_hw_ctrl = 0x1540,
168 	.pd = {
169 		.name = "cx_gdsc",
170 	},
171 	.pwrsts = PWRSTS_OFF_ON,
172 	.flags = VOTABLE,
173 };
174 
175 static struct gdsc *gpu_cc_sc7180_gdscs[] = {
176 	[CX_GDSC] = &cx_gdsc,
177 };
178 
179 static struct clk_regmap *gpu_cc_sc7180_clocks[] = {
180 	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
181 	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
182 	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
183 	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
184 	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
185 	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
186 	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
187 };
188 
189 static const struct regmap_config gpu_cc_sc7180_regmap_config = {
190 	.reg_bits =	32,
191 	.reg_stride =	4,
192 	.val_bits =	32,
193 	.max_register =	0x8008,
194 	.fast_io =	true,
195 };
196 
197 static const struct qcom_cc_desc gpu_cc_sc7180_desc = {
198 	.config = &gpu_cc_sc7180_regmap_config,
199 	.clks = gpu_cc_sc7180_clocks,
200 	.num_clks = ARRAY_SIZE(gpu_cc_sc7180_clocks),
201 	.gdscs = gpu_cc_sc7180_gdscs,
202 	.num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
203 };
204 
205 static const struct of_device_id gpu_cc_sc7180_match_table[] = {
206 	{ .compatible = "qcom,sc7180-gpucc" },
207 	{ }
208 };
209 MODULE_DEVICE_TABLE(of, gpu_cc_sc7180_match_table);
210 
211 static int gpu_cc_sc7180_probe(struct platform_device *pdev)
212 {
213 	struct regmap *regmap;
214 	struct alpha_pll_config gpu_cc_pll_config = {};
215 	unsigned int value, mask;
216 
217 	regmap = qcom_cc_map(pdev, &gpu_cc_sc7180_desc);
218 	if (IS_ERR(regmap))
219 		return PTR_ERR(regmap);
220 
221 	/* 360MHz Configuration */
222 	gpu_cc_pll_config.l = 0x12;
223 	gpu_cc_pll_config.alpha = 0xc000;
224 	gpu_cc_pll_config.config_ctl_val = 0x20485699;
225 	gpu_cc_pll_config.config_ctl_hi_val = 0x00002067;
226 	gpu_cc_pll_config.user_ctl_val = 0x00000001;
227 	gpu_cc_pll_config.user_ctl_hi_val = 0x00004805;
228 	gpu_cc_pll_config.test_ctl_hi_val = 0x40000000;
229 
230 	clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll_config);
231 
232 	/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
233 	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
234 	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
235 	value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
236 	regmap_update_bits(regmap, 0x1098, mask, value);
237 
238 	/* Configure clk_dis_wait for gpu_cx_gdsc */
239 	regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
240 						8 << CLK_DIS_WAIT_SHIFT);
241 
242 	return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap);
243 }
244 
245 static struct platform_driver gpu_cc_sc7180_driver = {
246 	.probe = gpu_cc_sc7180_probe,
247 	.driver = {
248 		.name = "sc7180-gpucc",
249 		.of_match_table = gpu_cc_sc7180_match_table,
250 	},
251 };
252 
253 static int __init gpu_cc_sc7180_init(void)
254 {
255 	return platform_driver_register(&gpu_cc_sc7180_driver);
256 }
257 subsys_initcall(gpu_cc_sc7180_init);
258 
259 static void __exit gpu_cc_sc7180_exit(void)
260 {
261 	platform_driver_unregister(&gpu_cc_sc7180_driver);
262 }
263 module_exit(gpu_cc_sc7180_exit);
264 
265 MODULE_DESCRIPTION("QTI GPU_CC SC7180 Driver");
266 MODULE_LICENSE("GPL v2");
267