xref: /openbmc/linux/drivers/clk/qcom/gpucc-sc7180.c (revision 72de7a19) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10 
11 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
12 
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-rcg.h"
16 #include "clk-regmap.h"
17 #include "common.h"
18 #include "gdsc.h"
19 
20 #define CX_GMU_CBCR_SLEEP_MASK		0xF
21 #define CX_GMU_CBCR_SLEEP_SHIFT		4
22 #define CX_GMU_CBCR_WAKE_MASK		0xF
23 #define CX_GMU_CBCR_WAKE_SHIFT		8
24 #define CLK_DIS_WAIT_SHIFT		12
25 #define CLK_DIS_WAIT_MASK		(0xf << CLK_DIS_WAIT_SHIFT)
26 
27 enum {
28 	P_BI_TCXO,
29 	P_CORE_BI_PLL_TEST_SE,
30 	P_GPLL0_OUT_MAIN,
31 	P_GPLL0_OUT_MAIN_DIV,
32 	P_GPU_CC_PLL1_OUT_EVEN,
33 	P_GPU_CC_PLL1_OUT_MAIN,
34 	P_GPU_CC_PLL1_OUT_ODD,
35 };
36 
37 static const struct pll_vco fabia_vco[] = {
38 	{ 249600000, 2000000000, 0 },
39 };
40 
41 static struct clk_alpha_pll gpu_cc_pll1 = {
42 	.offset = 0x100,
43 	.vco_table = fabia_vco,
44 	.num_vco = ARRAY_SIZE(fabia_vco),
45 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
46 	.clkr = {
47 		.hw.init = &(struct clk_init_data){
48 			.name = "gpu_cc_pll1",
49 			.parent_data =  &(const struct clk_parent_data){
50 				.fw_name = "bi_tcxo",
51 			},
52 			.num_parents = 1,
53 			.ops = &clk_alpha_pll_fabia_ops,
54 		},
55 	},
56 };
57 
58 static const struct parent_map gpu_cc_parent_map_0[] = {
59 	{ P_BI_TCXO, 0 },
60 	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
61 	{ P_GPLL0_OUT_MAIN, 5 },
62 	{ P_GPLL0_OUT_MAIN_DIV, 6 },
63 };
64 
65 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
66 	{ .fw_name = "bi_tcxo" },
67 	{ .hw = &gpu_cc_pll1.clkr.hw },
68 	{ .fw_name = "gcc_gpu_gpll0_clk_src" },
69 	{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
70 };
71 
72 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
73 	F(19200000, P_BI_TCXO, 1, 0, 0),
74 	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
75 	{ }
76 };
77 
78 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
79 	.cmd_rcgr = 0x1120,
80 	.mnd_width = 0,
81 	.hid_width = 5,
82 	.parent_map = gpu_cc_parent_map_0,
83 	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
84 	.clkr.hw.init = &(struct clk_init_data){
85 		.name = "gpu_cc_gmu_clk_src",
86 		.parent_data = gpu_cc_parent_data_0,
87 		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
88 		.flags = CLK_SET_RATE_PARENT,
89 		.ops = &clk_rcg2_shared_ops,
90 	},
91 };
92 
93 static struct clk_branch gpu_cc_crc_ahb_clk = {
94 	.halt_reg = 0x107c,
95 	.halt_check = BRANCH_HALT_DELAY,
96 	.clkr = {
97 		.enable_reg = 0x107c,
98 		.enable_mask = BIT(0),
99 		.hw.init = &(struct clk_init_data){
100 			.name = "gpu_cc_crc_ahb_clk",
101 			.ops = &clk_branch2_ops,
102 		},
103 	},
104 };
105 
106 static struct clk_branch gpu_cc_cx_gmu_clk = {
107 	.halt_reg = 0x1098,
108 	.halt_check = BRANCH_HALT,
109 	.clkr = {
110 		.enable_reg = 0x1098,
111 		.enable_mask = BIT(0),
112 		.hw.init = &(struct clk_init_data){
113 			.name = "gpu_cc_cx_gmu_clk",
114 			.parent_data =  &(const struct clk_parent_data){
115 				.hw = &gpu_cc_gmu_clk_src.clkr.hw,
116 			},
117 			.num_parents = 1,
118 			.flags = CLK_SET_RATE_PARENT,
119 			.ops = &clk_branch2_ops,
120 		},
121 	},
122 };
123 
124 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
125 	.halt_reg = 0x108c,
126 	.halt_check = BRANCH_HALT_DELAY,
127 	.clkr = {
128 		.enable_reg = 0x108c,
129 		.enable_mask = BIT(0),
130 		.hw.init = &(struct clk_init_data){
131 			.name = "gpu_cc_cx_snoc_dvm_clk",
132 			.ops = &clk_branch2_ops,
133 		},
134 	},
135 };
136 
137 static struct clk_branch gpu_cc_cxo_aon_clk = {
138 	.halt_reg = 0x1004,
139 	.halt_check = BRANCH_HALT_DELAY,
140 	.clkr = {
141 		.enable_reg = 0x1004,
142 		.enable_mask = BIT(0),
143 		.hw.init = &(struct clk_init_data){
144 			.name = "gpu_cc_cxo_aon_clk",
145 			.ops = &clk_branch2_ops,
146 		},
147 	},
148 };
149 
150 static struct clk_branch gpu_cc_cxo_clk = {
151 	.halt_reg = 0x109c,
152 	.halt_check = BRANCH_HALT,
153 	.clkr = {
154 		.enable_reg = 0x109c,
155 		.enable_mask = BIT(0),
156 		.hw.init = &(struct clk_init_data){
157 			.name = "gpu_cc_cxo_clk",
158 			.ops = &clk_branch2_ops,
159 		},
160 	},
161 };
162 
163 static struct gdsc cx_gdsc = {
164 	.gdscr = 0x106c,
165 	.gds_hw_ctrl = 0x1540,
166 	.pd = {
167 		.name = "cx_gdsc",
168 	},
169 	.pwrsts = PWRSTS_OFF_ON,
170 	.flags = VOTABLE,
171 };
172 
173 static struct gdsc *gpu_cc_sc7180_gdscs[] = {
174 	[CX_GDSC] = &cx_gdsc,
175 };
176 
177 static struct clk_regmap *gpu_cc_sc7180_clocks[] = {
178 	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
179 	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
180 	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
181 	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
182 	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
183 	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
184 	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
185 };
186 
187 static const struct regmap_config gpu_cc_sc7180_regmap_config = {
188 	.reg_bits =	32,
189 	.reg_stride =	4,
190 	.val_bits =	32,
191 	.max_register =	0x8008,
192 	.fast_io =	true,
193 };
194 
195 static const struct qcom_cc_desc gpu_cc_sc7180_desc = {
196 	.config = &gpu_cc_sc7180_regmap_config,
197 	.clks = gpu_cc_sc7180_clocks,
198 	.num_clks = ARRAY_SIZE(gpu_cc_sc7180_clocks),
199 	.gdscs = gpu_cc_sc7180_gdscs,
200 	.num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
201 };
202 
203 static const struct of_device_id gpu_cc_sc7180_match_table[] = {
204 	{ .compatible = "qcom,sc7180-gpucc" },
205 	{ }
206 };
207 MODULE_DEVICE_TABLE(of, gpu_cc_sc7180_match_table);
208 
209 static int gpu_cc_sc7180_probe(struct platform_device *pdev)
210 {
211 	struct regmap *regmap;
212 	struct alpha_pll_config gpu_cc_pll_config = {};
213 	unsigned int value, mask;
214 
215 	regmap = qcom_cc_map(pdev, &gpu_cc_sc7180_desc);
216 	if (IS_ERR(regmap))
217 		return PTR_ERR(regmap);
218 
219 	/* 360MHz Configuration */
220 	gpu_cc_pll_config.l = 0x12;
221 	gpu_cc_pll_config.alpha = 0xc000;
222 	gpu_cc_pll_config.config_ctl_val = 0x20485699;
223 	gpu_cc_pll_config.config_ctl_hi_val = 0x00002067;
224 	gpu_cc_pll_config.user_ctl_val = 0x00000001;
225 	gpu_cc_pll_config.user_ctl_hi_val = 0x00004805;
226 	gpu_cc_pll_config.test_ctl_hi_val = 0x40000000;
227 
228 	clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll_config);
229 
230 	/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
231 	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
232 	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
233 	value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
234 	regmap_update_bits(regmap, 0x1098, mask, value);
235 
236 	/* Configure clk_dis_wait for gpu_cx_gdsc */
237 	regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
238 						8 << CLK_DIS_WAIT_SHIFT);
239 
240 	return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap);
241 }
242 
243 static struct platform_driver gpu_cc_sc7180_driver = {
244 	.probe = gpu_cc_sc7180_probe,
245 	.driver = {
246 		.name = "sc7180-gpucc",
247 		.of_match_table = gpu_cc_sc7180_match_table,
248 	},
249 };
250 
251 static int __init gpu_cc_sc7180_init(void)
252 {
253 	return platform_driver_register(&gpu_cc_sc7180_driver);
254 }
255 subsys_initcall(gpu_cc_sc7180_init);
256 
257 static void __exit gpu_cc_sc7180_exit(void)
258 {
259 	platform_driver_unregister(&gpu_cc_sc7180_driver);
260 }
261 module_exit(gpu_cc_sc7180_exit);
262 
263 MODULE_DESCRIPTION("QTI GPU_CC SC7180 Driver");
264 MODULE_LICENSE("GPL v2");
265