1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,gpucc-sc7180.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "common.h" 18 #include "gdsc.h" 19 20 #define CX_GMU_CBCR_SLEEP_MASK 0xF 21 #define CX_GMU_CBCR_SLEEP_SHIFT 4 22 #define CX_GMU_CBCR_WAKE_MASK 0xF 23 #define CX_GMU_CBCR_WAKE_SHIFT 8 24 #define CLK_DIS_WAIT_SHIFT 12 25 #define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT) 26 27 enum { 28 P_BI_TCXO, 29 P_GPLL0_OUT_MAIN, 30 P_GPLL0_OUT_MAIN_DIV, 31 P_GPU_CC_PLL1_OUT_MAIN, 32 }; 33 34 static const struct pll_vco fabia_vco[] = { 35 { 249600000, 2000000000, 0 }, 36 }; 37 38 static struct clk_alpha_pll gpu_cc_pll1 = { 39 .offset = 0x100, 40 .vco_table = fabia_vco, 41 .num_vco = ARRAY_SIZE(fabia_vco), 42 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 43 .clkr = { 44 .hw.init = &(struct clk_init_data){ 45 .name = "gpu_cc_pll1", 46 .parent_data = &(const struct clk_parent_data){ 47 .fw_name = "bi_tcxo", 48 }, 49 .num_parents = 1, 50 .ops = &clk_alpha_pll_fabia_ops, 51 }, 52 }, 53 }; 54 55 static const struct parent_map gpu_cc_parent_map_0[] = { 56 { P_BI_TCXO, 0 }, 57 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 58 { P_GPLL0_OUT_MAIN, 5 }, 59 { P_GPLL0_OUT_MAIN_DIV, 6 }, 60 }; 61 62 static const struct clk_parent_data gpu_cc_parent_data_0[] = { 63 { .fw_name = "bi_tcxo" }, 64 { .hw = &gpu_cc_pll1.clkr.hw }, 65 { .fw_name = "gcc_gpu_gpll0_clk_src" }, 66 { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, 67 }; 68 69 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 70 F(19200000, P_BI_TCXO, 1, 0, 0), 71 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), 72 { } 73 }; 74 75 static struct clk_rcg2 gpu_cc_gmu_clk_src = { 76 .cmd_rcgr = 0x1120, 77 .mnd_width = 0, 78 .hid_width = 5, 79 .parent_map = gpu_cc_parent_map_0, 80 .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 81 .clkr.hw.init = &(struct clk_init_data){ 82 .name = "gpu_cc_gmu_clk_src", 83 .parent_data = gpu_cc_parent_data_0, 84 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 85 .flags = CLK_SET_RATE_PARENT, 86 .ops = &clk_rcg2_shared_ops, 87 }, 88 }; 89 90 static struct clk_branch gpu_cc_crc_ahb_clk = { 91 .halt_reg = 0x107c, 92 .halt_check = BRANCH_HALT_DELAY, 93 .clkr = { 94 .enable_reg = 0x107c, 95 .enable_mask = BIT(0), 96 .hw.init = &(struct clk_init_data){ 97 .name = "gpu_cc_crc_ahb_clk", 98 .ops = &clk_branch2_ops, 99 }, 100 }, 101 }; 102 103 static struct clk_branch gpu_cc_cx_gmu_clk = { 104 .halt_reg = 0x1098, 105 .halt_check = BRANCH_HALT, 106 .clkr = { 107 .enable_reg = 0x1098, 108 .enable_mask = BIT(0), 109 .hw.init = &(struct clk_init_data){ 110 .name = "gpu_cc_cx_gmu_clk", 111 .parent_data = &(const struct clk_parent_data){ 112 .hw = &gpu_cc_gmu_clk_src.clkr.hw, 113 }, 114 .num_parents = 1, 115 .flags = CLK_SET_RATE_PARENT, 116 .ops = &clk_branch2_ops, 117 }, 118 }, 119 }; 120 121 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { 122 .halt_reg = 0x108c, 123 .halt_check = BRANCH_HALT_DELAY, 124 .clkr = { 125 .enable_reg = 0x108c, 126 .enable_mask = BIT(0), 127 .hw.init = &(struct clk_init_data){ 128 .name = "gpu_cc_cx_snoc_dvm_clk", 129 .ops = &clk_branch2_ops, 130 }, 131 }, 132 }; 133 134 static struct clk_branch gpu_cc_cxo_aon_clk = { 135 .halt_reg = 0x1004, 136 .halt_check = BRANCH_HALT_DELAY, 137 .clkr = { 138 .enable_reg = 0x1004, 139 .enable_mask = BIT(0), 140 .hw.init = &(struct clk_init_data){ 141 .name = "gpu_cc_cxo_aon_clk", 142 .ops = &clk_branch2_ops, 143 }, 144 }, 145 }; 146 147 static struct clk_branch gpu_cc_cxo_clk = { 148 .halt_reg = 0x109c, 149 .halt_check = BRANCH_HALT, 150 .clkr = { 151 .enable_reg = 0x109c, 152 .enable_mask = BIT(0), 153 .hw.init = &(struct clk_init_data){ 154 .name = "gpu_cc_cxo_clk", 155 .ops = &clk_branch2_ops, 156 }, 157 }, 158 }; 159 160 static struct gdsc cx_gdsc = { 161 .gdscr = 0x106c, 162 .gds_hw_ctrl = 0x1540, 163 .pd = { 164 .name = "cx_gdsc", 165 }, 166 .pwrsts = PWRSTS_OFF_ON, 167 .flags = VOTABLE, 168 }; 169 170 static struct gdsc gx_gdsc = { 171 .gdscr = 0x100c, 172 .clamp_io_ctrl = 0x1508, 173 .pd = { 174 .name = "gx_gdsc", 175 .power_on = gdsc_gx_do_nothing_enable, 176 }, 177 .pwrsts = PWRSTS_OFF_ON, 178 .flags = CLAMP_IO, 179 }; 180 181 static struct gdsc *gpu_cc_sc7180_gdscs[] = { 182 [CX_GDSC] = &cx_gdsc, 183 [GX_GDSC] = &gx_gdsc, 184 }; 185 186 static struct clk_regmap *gpu_cc_sc7180_clocks[] = { 187 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 188 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, 189 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 190 [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, 191 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, 192 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 193 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 194 }; 195 196 static const struct regmap_config gpu_cc_sc7180_regmap_config = { 197 .reg_bits = 32, 198 .reg_stride = 4, 199 .val_bits = 32, 200 .max_register = 0x8008, 201 .fast_io = true, 202 }; 203 204 static const struct qcom_cc_desc gpu_cc_sc7180_desc = { 205 .config = &gpu_cc_sc7180_regmap_config, 206 .clks = gpu_cc_sc7180_clocks, 207 .num_clks = ARRAY_SIZE(gpu_cc_sc7180_clocks), 208 .gdscs = gpu_cc_sc7180_gdscs, 209 .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs), 210 }; 211 212 static const struct of_device_id gpu_cc_sc7180_match_table[] = { 213 { .compatible = "qcom,sc7180-gpucc" }, 214 { } 215 }; 216 MODULE_DEVICE_TABLE(of, gpu_cc_sc7180_match_table); 217 218 static int gpu_cc_sc7180_probe(struct platform_device *pdev) 219 { 220 struct regmap *regmap; 221 struct alpha_pll_config gpu_cc_pll_config = {}; 222 unsigned int value, mask; 223 224 regmap = qcom_cc_map(pdev, &gpu_cc_sc7180_desc); 225 if (IS_ERR(regmap)) 226 return PTR_ERR(regmap); 227 228 /* 360MHz Configuration */ 229 gpu_cc_pll_config.l = 0x12; 230 gpu_cc_pll_config.alpha = 0xc000; 231 gpu_cc_pll_config.config_ctl_val = 0x20485699; 232 gpu_cc_pll_config.config_ctl_hi_val = 0x00002067; 233 gpu_cc_pll_config.user_ctl_val = 0x00000001; 234 gpu_cc_pll_config.user_ctl_hi_val = 0x00004805; 235 gpu_cc_pll_config.test_ctl_hi_val = 0x40000000; 236 237 clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll_config); 238 239 /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ 240 mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT; 241 mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; 242 value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT; 243 regmap_update_bits(regmap, 0x1098, mask, value); 244 245 /* Configure clk_dis_wait for gpu_cx_gdsc */ 246 regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK, 247 8 << CLK_DIS_WAIT_SHIFT); 248 249 return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap); 250 } 251 252 static struct platform_driver gpu_cc_sc7180_driver = { 253 .probe = gpu_cc_sc7180_probe, 254 .driver = { 255 .name = "sc7180-gpucc", 256 .of_match_table = gpu_cc_sc7180_match_table, 257 }, 258 }; 259 260 static int __init gpu_cc_sc7180_init(void) 261 { 262 return platform_driver_register(&gpu_cc_sc7180_driver); 263 } 264 subsys_initcall(gpu_cc_sc7180_init); 265 266 static void __exit gpu_cc_sc7180_exit(void) 267 { 268 platform_driver_unregister(&gpu_cc_sc7180_driver); 269 } 270 module_exit(gpu_cc_sc7180_exit); 271 272 MODULE_DESCRIPTION("QTI GPU_CC SC7180 Driver"); 273 MODULE_LICENSE("GPL v2"); 274