13f7df5baSJeffrey Hugo // SPDX-License-Identifier: GPL-2.0 23f7df5baSJeffrey Hugo /* 33f7df5baSJeffrey Hugo * Copyright (c) 2019, Jeffrey Hugo 43f7df5baSJeffrey Hugo */ 53f7df5baSJeffrey Hugo 63f7df5baSJeffrey Hugo #include <linux/kernel.h> 73f7df5baSJeffrey Hugo #include <linux/bitops.h> 83f7df5baSJeffrey Hugo #include <linux/err.h> 93f7df5baSJeffrey Hugo #include <linux/platform_device.h> 103f7df5baSJeffrey Hugo #include <linux/module.h> 113f7df5baSJeffrey Hugo #include <linux/of.h> 123f7df5baSJeffrey Hugo #include <linux/of_device.h> 133f7df5baSJeffrey Hugo #include <linux/clk-provider.h> 143f7df5baSJeffrey Hugo #include <linux/regmap.h> 153f7df5baSJeffrey Hugo #include <linux/reset-controller.h> 163f7df5baSJeffrey Hugo 173f7df5baSJeffrey Hugo #include <dt-bindings/clock/qcom,gpucc-msm8998.h> 183f7df5baSJeffrey Hugo 193f7df5baSJeffrey Hugo #include "common.h" 203f7df5baSJeffrey Hugo #include "clk-regmap.h" 213f7df5baSJeffrey Hugo #include "clk-regmap-divider.h" 223f7df5baSJeffrey Hugo #include "clk-alpha-pll.h" 233f7df5baSJeffrey Hugo #include "clk-rcg.h" 243f7df5baSJeffrey Hugo #include "clk-branch.h" 253f7df5baSJeffrey Hugo #include "reset.h" 263f7df5baSJeffrey Hugo #include "gdsc.h" 273f7df5baSJeffrey Hugo 283f7df5baSJeffrey Hugo enum { 293f7df5baSJeffrey Hugo P_XO, 303f7df5baSJeffrey Hugo P_GPLL0, 313f7df5baSJeffrey Hugo P_GPUPLL0_OUT_EVEN, 323f7df5baSJeffrey Hugo }; 333f7df5baSJeffrey Hugo 343f7df5baSJeffrey Hugo /* Instead of going directly to the block, XO is routed through this branch */ 353f7df5baSJeffrey Hugo static struct clk_branch gpucc_cxo_clk = { 363f7df5baSJeffrey Hugo .halt_reg = 0x1020, 373f7df5baSJeffrey Hugo .clkr = { 383f7df5baSJeffrey Hugo .enable_reg = 0x1020, 393f7df5baSJeffrey Hugo .enable_mask = BIT(0), 403f7df5baSJeffrey Hugo .hw.init = &(struct clk_init_data){ 413f7df5baSJeffrey Hugo .name = "gpucc_cxo_clk", 423f7df5baSJeffrey Hugo .parent_data = &(const struct clk_parent_data){ 433f7df5baSJeffrey Hugo .fw_name = "xo", 443f7df5baSJeffrey Hugo .name = "xo" 453f7df5baSJeffrey Hugo }, 463f7df5baSJeffrey Hugo .num_parents = 1, 473f7df5baSJeffrey Hugo .ops = &clk_branch2_ops, 483f7df5baSJeffrey Hugo .flags = CLK_IS_CRITICAL, 493f7df5baSJeffrey Hugo }, 503f7df5baSJeffrey Hugo }, 513f7df5baSJeffrey Hugo }; 523f7df5baSJeffrey Hugo 533f7df5baSJeffrey Hugo static const struct clk_div_table post_div_table_fabia_even[] = { 543f7df5baSJeffrey Hugo { 0x0, 1 }, 553f7df5baSJeffrey Hugo { 0x1, 2 }, 563f7df5baSJeffrey Hugo { 0x3, 4 }, 573f7df5baSJeffrey Hugo { 0x7, 8 }, 583f7df5baSJeffrey Hugo { } 593f7df5baSJeffrey Hugo }; 603f7df5baSJeffrey Hugo 613f7df5baSJeffrey Hugo static struct clk_alpha_pll gpupll0 = { 623f7df5baSJeffrey Hugo .offset = 0x0, 633f7df5baSJeffrey Hugo .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 643f7df5baSJeffrey Hugo .clkr.hw.init = &(struct clk_init_data){ 653f7df5baSJeffrey Hugo .name = "gpupll0", 663f7df5baSJeffrey Hugo .parent_hws = (const struct clk_hw *[]){ &gpucc_cxo_clk.clkr.hw }, 673f7df5baSJeffrey Hugo .num_parents = 1, 683f7df5baSJeffrey Hugo .ops = &clk_alpha_pll_fixed_fabia_ops, 693f7df5baSJeffrey Hugo }, 703f7df5baSJeffrey Hugo }; 713f7df5baSJeffrey Hugo 723f7df5baSJeffrey Hugo static struct clk_alpha_pll_postdiv gpupll0_out_even = { 733f7df5baSJeffrey Hugo .offset = 0x0, 743f7df5baSJeffrey Hugo .post_div_shift = 8, 753f7df5baSJeffrey Hugo .post_div_table = post_div_table_fabia_even, 763f7df5baSJeffrey Hugo .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 773f7df5baSJeffrey Hugo .width = 4, 783f7df5baSJeffrey Hugo .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 793f7df5baSJeffrey Hugo .clkr.hw.init = &(struct clk_init_data){ 803f7df5baSJeffrey Hugo .name = "gpupll0_out_even", 813f7df5baSJeffrey Hugo .parent_hws = (const struct clk_hw *[]){ &gpupll0.clkr.hw }, 823f7df5baSJeffrey Hugo .num_parents = 1, 833f7df5baSJeffrey Hugo .ops = &clk_alpha_pll_postdiv_fabia_ops, 843f7df5baSJeffrey Hugo }, 853f7df5baSJeffrey Hugo }; 863f7df5baSJeffrey Hugo 873f7df5baSJeffrey Hugo static const struct parent_map gpu_xo_gpll0_map[] = { 883f7df5baSJeffrey Hugo { P_XO, 0 }, 893f7df5baSJeffrey Hugo { P_GPLL0, 5 }, 903f7df5baSJeffrey Hugo }; 913f7df5baSJeffrey Hugo 923f7df5baSJeffrey Hugo static const struct clk_parent_data gpu_xo_gpll0[] = { 933f7df5baSJeffrey Hugo { .hw = &gpucc_cxo_clk.clkr.hw }, 943f7df5baSJeffrey Hugo { .fw_name = "gpll0", .name = "gpll0" }, 953f7df5baSJeffrey Hugo }; 963f7df5baSJeffrey Hugo 973f7df5baSJeffrey Hugo static const struct parent_map gpu_xo_gpupll0_map[] = { 983f7df5baSJeffrey Hugo { P_XO, 0 }, 993f7df5baSJeffrey Hugo { P_GPUPLL0_OUT_EVEN, 1 }, 1003f7df5baSJeffrey Hugo }; 1013f7df5baSJeffrey Hugo 1023f7df5baSJeffrey Hugo static const struct clk_parent_data gpu_xo_gpupll0[] = { 1033f7df5baSJeffrey Hugo { .hw = &gpucc_cxo_clk.clkr.hw }, 1043f7df5baSJeffrey Hugo { .hw = &gpupll0_out_even.clkr.hw }, 1053f7df5baSJeffrey Hugo }; 1063f7df5baSJeffrey Hugo 1073f7df5baSJeffrey Hugo static const struct freq_tbl ftbl_rbcpr_clk_src[] = { 1083f7df5baSJeffrey Hugo F(19200000, P_XO, 1, 0, 0), 1093f7df5baSJeffrey Hugo F(50000000, P_GPLL0, 12, 0, 0), 1103f7df5baSJeffrey Hugo { } 1113f7df5baSJeffrey Hugo }; 1123f7df5baSJeffrey Hugo 1133f7df5baSJeffrey Hugo static struct clk_rcg2 rbcpr_clk_src = { 1143f7df5baSJeffrey Hugo .cmd_rcgr = 0x1030, 1153f7df5baSJeffrey Hugo .hid_width = 5, 1163f7df5baSJeffrey Hugo .parent_map = gpu_xo_gpll0_map, 1173f7df5baSJeffrey Hugo .freq_tbl = ftbl_rbcpr_clk_src, 1183f7df5baSJeffrey Hugo .clkr.hw.init = &(struct clk_init_data){ 1193f7df5baSJeffrey Hugo .name = "rbcpr_clk_src", 1203f7df5baSJeffrey Hugo .parent_data = gpu_xo_gpll0, 1213f7df5baSJeffrey Hugo .num_parents = 2, 1223f7df5baSJeffrey Hugo .ops = &clk_rcg2_ops, 1233f7df5baSJeffrey Hugo }, 1243f7df5baSJeffrey Hugo }; 1253f7df5baSJeffrey Hugo 1263f7df5baSJeffrey Hugo static const struct freq_tbl ftbl_gfx3d_clk_src[] = { 1273f7df5baSJeffrey Hugo { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 }, 1283f7df5baSJeffrey Hugo { } 1293f7df5baSJeffrey Hugo }; 1303f7df5baSJeffrey Hugo 1313f7df5baSJeffrey Hugo static struct clk_rcg2 gfx3d_clk_src = { 1323f7df5baSJeffrey Hugo .cmd_rcgr = 0x1070, 1333f7df5baSJeffrey Hugo .hid_width = 5, 1343f7df5baSJeffrey Hugo .parent_map = gpu_xo_gpupll0_map, 1353f7df5baSJeffrey Hugo .freq_tbl = ftbl_gfx3d_clk_src, 1363f7df5baSJeffrey Hugo .clkr.hw.init = &(struct clk_init_data){ 1373f7df5baSJeffrey Hugo .name = "gfx3d_clk_src", 1383f7df5baSJeffrey Hugo .parent_data = gpu_xo_gpupll0, 1393f7df5baSJeffrey Hugo .num_parents = 2, 1403f7df5baSJeffrey Hugo .ops = &clk_rcg2_ops, 1413f7df5baSJeffrey Hugo .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 1423f7df5baSJeffrey Hugo }, 1433f7df5baSJeffrey Hugo }; 1443f7df5baSJeffrey Hugo 1453f7df5baSJeffrey Hugo static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { 1463f7df5baSJeffrey Hugo F(19200000, P_XO, 1, 0, 0), 1473f7df5baSJeffrey Hugo { } 1483f7df5baSJeffrey Hugo }; 1493f7df5baSJeffrey Hugo 1503f7df5baSJeffrey Hugo static struct clk_rcg2 rbbmtimer_clk_src = { 1513f7df5baSJeffrey Hugo .cmd_rcgr = 0x10b0, 1523f7df5baSJeffrey Hugo .hid_width = 5, 1533f7df5baSJeffrey Hugo .parent_map = gpu_xo_gpll0_map, 1543f7df5baSJeffrey Hugo .freq_tbl = ftbl_rbbmtimer_clk_src, 1553f7df5baSJeffrey Hugo .clkr.hw.init = &(struct clk_init_data){ 1563f7df5baSJeffrey Hugo .name = "rbbmtimer_clk_src", 1573f7df5baSJeffrey Hugo .parent_data = gpu_xo_gpll0, 1583f7df5baSJeffrey Hugo .num_parents = 2, 1593f7df5baSJeffrey Hugo .ops = &clk_rcg2_ops, 1603f7df5baSJeffrey Hugo }, 1613f7df5baSJeffrey Hugo }; 1623f7df5baSJeffrey Hugo 1633f7df5baSJeffrey Hugo static const struct freq_tbl ftbl_gfx3d_isense_clk_src[] = { 1643f7df5baSJeffrey Hugo F(19200000, P_XO, 1, 0, 0), 1653f7df5baSJeffrey Hugo F(40000000, P_GPLL0, 15, 0, 0), 1663f7df5baSJeffrey Hugo F(200000000, P_GPLL0, 3, 0, 0), 1673f7df5baSJeffrey Hugo F(300000000, P_GPLL0, 2, 0, 0), 1683f7df5baSJeffrey Hugo { } 1693f7df5baSJeffrey Hugo }; 1703f7df5baSJeffrey Hugo 1713f7df5baSJeffrey Hugo static struct clk_rcg2 gfx3d_isense_clk_src = { 1723f7df5baSJeffrey Hugo .cmd_rcgr = 0x1100, 1733f7df5baSJeffrey Hugo .hid_width = 5, 1743f7df5baSJeffrey Hugo .parent_map = gpu_xo_gpll0_map, 1753f7df5baSJeffrey Hugo .freq_tbl = ftbl_gfx3d_isense_clk_src, 1763f7df5baSJeffrey Hugo .clkr.hw.init = &(struct clk_init_data){ 1773f7df5baSJeffrey Hugo .name = "gfx3d_isense_clk_src", 1783f7df5baSJeffrey Hugo .parent_data = gpu_xo_gpll0, 1793f7df5baSJeffrey Hugo .num_parents = 2, 1803f7df5baSJeffrey Hugo .ops = &clk_rcg2_ops, 1813f7df5baSJeffrey Hugo }, 1823f7df5baSJeffrey Hugo }; 1833f7df5baSJeffrey Hugo 1843f7df5baSJeffrey Hugo static struct clk_branch rbcpr_clk = { 1853f7df5baSJeffrey Hugo .halt_reg = 0x1054, 1863f7df5baSJeffrey Hugo .clkr = { 1873f7df5baSJeffrey Hugo .enable_reg = 0x1054, 1883f7df5baSJeffrey Hugo .enable_mask = BIT(0), 1893f7df5baSJeffrey Hugo .hw.init = &(struct clk_init_data){ 1903f7df5baSJeffrey Hugo .name = "rbcpr_clk", 1913f7df5baSJeffrey Hugo .parent_hws = (const struct clk_hw *[]){ &rbcpr_clk_src.clkr.hw }, 1923f7df5baSJeffrey Hugo .num_parents = 1, 1933f7df5baSJeffrey Hugo .ops = &clk_branch2_ops, 1943f7df5baSJeffrey Hugo .flags = CLK_SET_RATE_PARENT, 1953f7df5baSJeffrey Hugo }, 1963f7df5baSJeffrey Hugo }, 1973f7df5baSJeffrey Hugo }; 1983f7df5baSJeffrey Hugo 1993f7df5baSJeffrey Hugo static struct clk_branch gfx3d_clk = { 2003f7df5baSJeffrey Hugo .halt_reg = 0x1098, 2013f7df5baSJeffrey Hugo .clkr = { 2023f7df5baSJeffrey Hugo .enable_reg = 0x1098, 2033f7df5baSJeffrey Hugo .enable_mask = BIT(0), 2043f7df5baSJeffrey Hugo .hw.init = &(struct clk_init_data){ 2053f7df5baSJeffrey Hugo .name = "gfx3d_clk", 2063f7df5baSJeffrey Hugo .parent_hws = (const struct clk_hw *[]){ &gfx3d_clk_src.clkr.hw }, 2073f7df5baSJeffrey Hugo .num_parents = 1, 2083f7df5baSJeffrey Hugo .ops = &clk_branch2_ops, 2093f7df5baSJeffrey Hugo .flags = CLK_SET_RATE_PARENT, 2103f7df5baSJeffrey Hugo }, 2113f7df5baSJeffrey Hugo }, 2123f7df5baSJeffrey Hugo }; 2133f7df5baSJeffrey Hugo 2143f7df5baSJeffrey Hugo static struct clk_branch rbbmtimer_clk = { 2153f7df5baSJeffrey Hugo .halt_reg = 0x10d0, 2163f7df5baSJeffrey Hugo .clkr = { 2173f7df5baSJeffrey Hugo .enable_reg = 0x10d0, 2183f7df5baSJeffrey Hugo .enable_mask = BIT(0), 2193f7df5baSJeffrey Hugo .hw.init = &(struct clk_init_data){ 2203f7df5baSJeffrey Hugo .name = "rbbmtimer_clk", 2213f7df5baSJeffrey Hugo .parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw }, 2223f7df5baSJeffrey Hugo .num_parents = 1, 2233f7df5baSJeffrey Hugo .ops = &clk_branch2_ops, 2243f7df5baSJeffrey Hugo .flags = CLK_SET_RATE_PARENT, 2253f7df5baSJeffrey Hugo }, 2263f7df5baSJeffrey Hugo }, 2273f7df5baSJeffrey Hugo }; 2283f7df5baSJeffrey Hugo 2293f7df5baSJeffrey Hugo static struct clk_branch gfx3d_isense_clk = { 2303f7df5baSJeffrey Hugo .halt_reg = 0x1124, 2313f7df5baSJeffrey Hugo .clkr = { 2323f7df5baSJeffrey Hugo .enable_reg = 0x1124, 2333f7df5baSJeffrey Hugo .enable_mask = BIT(0), 2343f7df5baSJeffrey Hugo .hw.init = &(struct clk_init_data){ 2353f7df5baSJeffrey Hugo .name = "gfx3d_isense_clk", 2363f7df5baSJeffrey Hugo .parent_hws = (const struct clk_hw *[]){ &gfx3d_isense_clk_src.clkr.hw }, 2373f7df5baSJeffrey Hugo .num_parents = 1, 2383f7df5baSJeffrey Hugo .ops = &clk_branch2_ops, 2393f7df5baSJeffrey Hugo }, 2403f7df5baSJeffrey Hugo }, 2413f7df5baSJeffrey Hugo }; 2423f7df5baSJeffrey Hugo 2433f7df5baSJeffrey Hugo static struct gdsc gpu_cx_gdsc = { 2443f7df5baSJeffrey Hugo .gdscr = 0x1004, 245781d8ceaSJeffrey Hugo .gds_hw_ctrl = 0x1008, 2463f7df5baSJeffrey Hugo .pd = { 2473f7df5baSJeffrey Hugo .name = "gpu_cx", 2483f7df5baSJeffrey Hugo }, 2493f7df5baSJeffrey Hugo .pwrsts = PWRSTS_OFF_ON, 250781d8ceaSJeffrey Hugo .flags = VOTABLE, 2513f7df5baSJeffrey Hugo }; 2523f7df5baSJeffrey Hugo 2533f7df5baSJeffrey Hugo static struct gdsc gpu_gx_gdsc = { 2543f7df5baSJeffrey Hugo .gdscr = 0x1094, 2553f7df5baSJeffrey Hugo .clamp_io_ctrl = 0x130, 2563f7df5baSJeffrey Hugo .pd = { 2573f7df5baSJeffrey Hugo .name = "gpu_gx", 2583f7df5baSJeffrey Hugo }, 2593f7df5baSJeffrey Hugo .parent = &gpu_cx_gdsc.pd, 2603f7df5baSJeffrey Hugo .pwrsts = PWRSTS_OFF_ON, 2613f7df5baSJeffrey Hugo .flags = CLAMP_IO | AON_RESET, 2623f7df5baSJeffrey Hugo }; 2633f7df5baSJeffrey Hugo 2643f7df5baSJeffrey Hugo static struct clk_regmap *gpucc_msm8998_clocks[] = { 2653f7df5baSJeffrey Hugo [GPUPLL0] = &gpupll0.clkr, 2663f7df5baSJeffrey Hugo [GPUPLL0_OUT_EVEN] = &gpupll0_out_even.clkr, 2673f7df5baSJeffrey Hugo [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 2683f7df5baSJeffrey Hugo [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 2693f7df5baSJeffrey Hugo [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 2703f7df5baSJeffrey Hugo [GFX3D_ISENSE_CLK_SRC] = &gfx3d_isense_clk_src.clkr, 2713f7df5baSJeffrey Hugo [RBCPR_CLK] = &rbcpr_clk.clkr, 2723f7df5baSJeffrey Hugo [GFX3D_CLK] = &gfx3d_clk.clkr, 2733f7df5baSJeffrey Hugo [RBBMTIMER_CLK] = &rbbmtimer_clk.clkr, 2743f7df5baSJeffrey Hugo [GFX3D_ISENSE_CLK] = &gfx3d_isense_clk.clkr, 2753f7df5baSJeffrey Hugo [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr, 2763f7df5baSJeffrey Hugo }; 2773f7df5baSJeffrey Hugo 2783f7df5baSJeffrey Hugo static struct gdsc *gpucc_msm8998_gdscs[] = { 2793f7df5baSJeffrey Hugo [GPU_CX_GDSC] = &gpu_cx_gdsc, 2803f7df5baSJeffrey Hugo [GPU_GX_GDSC] = &gpu_gx_gdsc, 2813f7df5baSJeffrey Hugo }; 2823f7df5baSJeffrey Hugo 2833f7df5baSJeffrey Hugo static const struct qcom_reset_map gpucc_msm8998_resets[] = { 2843f7df5baSJeffrey Hugo [GPU_CX_BCR] = { 0x1000 }, 2853f7df5baSJeffrey Hugo [RBCPR_BCR] = { 0x1050 }, 2863f7df5baSJeffrey Hugo [GPU_GX_BCR] = { 0x1090 }, 2873f7df5baSJeffrey Hugo [GPU_ISENSE_BCR] = { 0x1120 }, 2883f7df5baSJeffrey Hugo }; 2893f7df5baSJeffrey Hugo 2903f7df5baSJeffrey Hugo static const struct regmap_config gpucc_msm8998_regmap_config = { 2913f7df5baSJeffrey Hugo .reg_bits = 32, 2923f7df5baSJeffrey Hugo .reg_stride = 4, 2933f7df5baSJeffrey Hugo .val_bits = 32, 2943f7df5baSJeffrey Hugo .max_register = 0x9000, 2953f7df5baSJeffrey Hugo .fast_io = true, 2963f7df5baSJeffrey Hugo }; 2973f7df5baSJeffrey Hugo 2983f7df5baSJeffrey Hugo static const struct qcom_cc_desc gpucc_msm8998_desc = { 2993f7df5baSJeffrey Hugo .config = &gpucc_msm8998_regmap_config, 3003f7df5baSJeffrey Hugo .clks = gpucc_msm8998_clocks, 3013f7df5baSJeffrey Hugo .num_clks = ARRAY_SIZE(gpucc_msm8998_clocks), 3023f7df5baSJeffrey Hugo .resets = gpucc_msm8998_resets, 3033f7df5baSJeffrey Hugo .num_resets = ARRAY_SIZE(gpucc_msm8998_resets), 3043f7df5baSJeffrey Hugo .gdscs = gpucc_msm8998_gdscs, 3053f7df5baSJeffrey Hugo .num_gdscs = ARRAY_SIZE(gpucc_msm8998_gdscs), 3063f7df5baSJeffrey Hugo }; 3073f7df5baSJeffrey Hugo 3083f7df5baSJeffrey Hugo static const struct of_device_id gpucc_msm8998_match_table[] = { 3093f7df5baSJeffrey Hugo { .compatible = "qcom,msm8998-gpucc" }, 3103f7df5baSJeffrey Hugo { } 3113f7df5baSJeffrey Hugo }; 3123f7df5baSJeffrey Hugo MODULE_DEVICE_TABLE(of, gpucc_msm8998_match_table); 3133f7df5baSJeffrey Hugo 3143f7df5baSJeffrey Hugo static int gpucc_msm8998_probe(struct platform_device *pdev) 3153f7df5baSJeffrey Hugo { 3163f7df5baSJeffrey Hugo struct regmap *regmap; 3173f7df5baSJeffrey Hugo 3183f7df5baSJeffrey Hugo regmap = qcom_cc_map(pdev, &gpucc_msm8998_desc); 3193f7df5baSJeffrey Hugo if (IS_ERR(regmap)) 3203f7df5baSJeffrey Hugo return PTR_ERR(regmap); 3213f7df5baSJeffrey Hugo 3223f7df5baSJeffrey Hugo /* force periph logic on to avoid perf counter corruption */ 3233f7df5baSJeffrey Hugo regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(13), BIT(13)); 3243f7df5baSJeffrey Hugo /* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */ 3253f7df5baSJeffrey Hugo regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0)); 3263f7df5baSJeffrey Hugo 3273f7df5baSJeffrey Hugo return qcom_cc_really_probe(pdev, &gpucc_msm8998_desc, regmap); 3283f7df5baSJeffrey Hugo } 3293f7df5baSJeffrey Hugo 3303f7df5baSJeffrey Hugo static struct platform_driver gpucc_msm8998_driver = { 3313f7df5baSJeffrey Hugo .probe = gpucc_msm8998_probe, 3323f7df5baSJeffrey Hugo .driver = { 3333f7df5baSJeffrey Hugo .name = "gpucc-msm8998", 3343f7df5baSJeffrey Hugo .of_match_table = gpucc_msm8998_match_table, 3353f7df5baSJeffrey Hugo }, 3363f7df5baSJeffrey Hugo }; 3373f7df5baSJeffrey Hugo module_platform_driver(gpucc_msm8998_driver); 3383f7df5baSJeffrey Hugo 3393f7df5baSJeffrey Hugo MODULE_DESCRIPTION("QCOM GPUCC MSM8998 Driver"); 3403f7df5baSJeffrey Hugo MODULE_LICENSE("GPL v2"); 341