13f7df5baSJeffrey Hugo // SPDX-License-Identifier: GPL-2.0
23f7df5baSJeffrey Hugo /*
33f7df5baSJeffrey Hugo * Copyright (c) 2019, Jeffrey Hugo
43f7df5baSJeffrey Hugo */
53f7df5baSJeffrey Hugo
63f7df5baSJeffrey Hugo #include <linux/kernel.h>
73f7df5baSJeffrey Hugo #include <linux/bitops.h>
83f7df5baSJeffrey Hugo #include <linux/err.h>
93f7df5baSJeffrey Hugo #include <linux/platform_device.h>
103f7df5baSJeffrey Hugo #include <linux/module.h>
113f7df5baSJeffrey Hugo #include <linux/of.h>
123f7df5baSJeffrey Hugo #include <linux/clk-provider.h>
133f7df5baSJeffrey Hugo #include <linux/regmap.h>
143f7df5baSJeffrey Hugo #include <linux/reset-controller.h>
153f7df5baSJeffrey Hugo
163f7df5baSJeffrey Hugo #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
173f7df5baSJeffrey Hugo
183f7df5baSJeffrey Hugo #include "common.h"
193f7df5baSJeffrey Hugo #include "clk-regmap.h"
203f7df5baSJeffrey Hugo #include "clk-regmap-divider.h"
213f7df5baSJeffrey Hugo #include "clk-alpha-pll.h"
223f7df5baSJeffrey Hugo #include "clk-rcg.h"
233f7df5baSJeffrey Hugo #include "clk-branch.h"
243f7df5baSJeffrey Hugo #include "reset.h"
253f7df5baSJeffrey Hugo #include "gdsc.h"
263f7df5baSJeffrey Hugo
273f7df5baSJeffrey Hugo enum {
283f7df5baSJeffrey Hugo P_XO,
293f7df5baSJeffrey Hugo P_GPLL0,
303f7df5baSJeffrey Hugo P_GPUPLL0_OUT_EVEN,
313f7df5baSJeffrey Hugo };
323f7df5baSJeffrey Hugo
333f7df5baSJeffrey Hugo /* Instead of going directly to the block, XO is routed through this branch */
343f7df5baSJeffrey Hugo static struct clk_branch gpucc_cxo_clk = {
353f7df5baSJeffrey Hugo .halt_reg = 0x1020,
363f7df5baSJeffrey Hugo .clkr = {
373f7df5baSJeffrey Hugo .enable_reg = 0x1020,
383f7df5baSJeffrey Hugo .enable_mask = BIT(0),
393f7df5baSJeffrey Hugo .hw.init = &(struct clk_init_data){
403f7df5baSJeffrey Hugo .name = "gpucc_cxo_clk",
413f7df5baSJeffrey Hugo .parent_data = &(const struct clk_parent_data){
423f7df5baSJeffrey Hugo .fw_name = "xo"
437837187cSMarijn Suijten },
443f7df5baSJeffrey Hugo .num_parents = 1,
453f7df5baSJeffrey Hugo .ops = &clk_branch2_ops,
463f7df5baSJeffrey Hugo .flags = CLK_IS_CRITICAL,
473f7df5baSJeffrey Hugo },
483f7df5baSJeffrey Hugo },
493f7df5baSJeffrey Hugo };
503f7df5baSJeffrey Hugo
513f7df5baSJeffrey Hugo static struct pll_vco fabia_vco[] = {
5253748348SAngeloGioacchino Del Regno { 249600000, 2000000000, 0 },
5353748348SAngeloGioacchino Del Regno { 125000000, 1000000000, 1 },
5453748348SAngeloGioacchino Del Regno };
5553748348SAngeloGioacchino Del Regno
5653748348SAngeloGioacchino Del Regno static const struct clk_div_table post_div_table_fabia_even[] = {
573f7df5baSJeffrey Hugo { 0x0, 1 },
583f7df5baSJeffrey Hugo { 0x1, 2 },
593f7df5baSJeffrey Hugo { 0x3, 4 },
603f7df5baSJeffrey Hugo { 0x7, 8 },
613f7df5baSJeffrey Hugo { }
623f7df5baSJeffrey Hugo };
633f7df5baSJeffrey Hugo
643f7df5baSJeffrey Hugo static struct clk_alpha_pll gpupll0 = {
653f7df5baSJeffrey Hugo .offset = 0x0,
663f7df5baSJeffrey Hugo .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
673f7df5baSJeffrey Hugo .vco_table = fabia_vco,
6853748348SAngeloGioacchino Del Regno .num_vco = ARRAY_SIZE(fabia_vco),
6953748348SAngeloGioacchino Del Regno .clkr.hw.init = &(struct clk_init_data){
703f7df5baSJeffrey Hugo .name = "gpupll0",
713f7df5baSJeffrey Hugo .parent_hws = (const struct clk_hw *[]){ &gpucc_cxo_clk.clkr.hw },
723f7df5baSJeffrey Hugo .num_parents = 1,
733f7df5baSJeffrey Hugo .ops = &clk_alpha_pll_fabia_ops,
7453748348SAngeloGioacchino Del Regno },
753f7df5baSJeffrey Hugo };
763f7df5baSJeffrey Hugo
773f7df5baSJeffrey Hugo static struct clk_alpha_pll_postdiv gpupll0_out_even = {
783f7df5baSJeffrey Hugo .offset = 0x0,
793f7df5baSJeffrey Hugo .post_div_shift = 8,
803f7df5baSJeffrey Hugo .post_div_table = post_div_table_fabia_even,
813f7df5baSJeffrey Hugo .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
823f7df5baSJeffrey Hugo .width = 4,
833f7df5baSJeffrey Hugo .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
843f7df5baSJeffrey Hugo .clkr.hw.init = &(struct clk_init_data){
853f7df5baSJeffrey Hugo .name = "gpupll0_out_even",
863f7df5baSJeffrey Hugo .parent_hws = (const struct clk_hw *[]){ &gpupll0.clkr.hw },
873f7df5baSJeffrey Hugo .num_parents = 1,
883f7df5baSJeffrey Hugo .flags = CLK_SET_RATE_PARENT,
8953748348SAngeloGioacchino Del Regno .ops = &clk_alpha_pll_postdiv_fabia_ops,
903f7df5baSJeffrey Hugo },
913f7df5baSJeffrey Hugo };
923f7df5baSJeffrey Hugo
933f7df5baSJeffrey Hugo static const struct parent_map gpu_xo_gpll0_map[] = {
943f7df5baSJeffrey Hugo { P_XO, 0 },
953f7df5baSJeffrey Hugo { P_GPLL0, 5 },
963f7df5baSJeffrey Hugo };
973f7df5baSJeffrey Hugo
983f7df5baSJeffrey Hugo static const struct clk_parent_data gpu_xo_gpll0[] = {
993f7df5baSJeffrey Hugo { .hw = &gpucc_cxo_clk.clkr.hw },
1003f7df5baSJeffrey Hugo { .fw_name = "gpll0", .name = "gcc_gpu_gpll0_clk" },
101*03f1b83dSKonrad Dybcio };
1023f7df5baSJeffrey Hugo
1033f7df5baSJeffrey Hugo static const struct parent_map gpu_xo_gpupll0_map[] = {
1043f7df5baSJeffrey Hugo { P_XO, 0 },
1053f7df5baSJeffrey Hugo { P_GPUPLL0_OUT_EVEN, 1 },
1063f7df5baSJeffrey Hugo };
1073f7df5baSJeffrey Hugo
1083f7df5baSJeffrey Hugo static const struct clk_hw *gpu_xo_gpupll0[] = {
109353b18dcSDmitry Baryshkov &gpucc_cxo_clk.clkr.hw,
110353b18dcSDmitry Baryshkov &gpupll0_out_even.clkr.hw,
111353b18dcSDmitry Baryshkov };
1123f7df5baSJeffrey Hugo
1133f7df5baSJeffrey Hugo static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
1143f7df5baSJeffrey Hugo F(19200000, P_XO, 1, 0, 0),
1153f7df5baSJeffrey Hugo F(50000000, P_GPLL0, 12, 0, 0),
1163f7df5baSJeffrey Hugo { }
1173f7df5baSJeffrey Hugo };
1183f7df5baSJeffrey Hugo
1193f7df5baSJeffrey Hugo static struct clk_rcg2 rbcpr_clk_src = {
1203f7df5baSJeffrey Hugo .cmd_rcgr = 0x1030,
1213f7df5baSJeffrey Hugo .hid_width = 5,
1223f7df5baSJeffrey Hugo .parent_map = gpu_xo_gpll0_map,
1233f7df5baSJeffrey Hugo .freq_tbl = ftbl_rbcpr_clk_src,
1243f7df5baSJeffrey Hugo .clkr.hw.init = &(struct clk_init_data){
1253f7df5baSJeffrey Hugo .name = "rbcpr_clk_src",
1263f7df5baSJeffrey Hugo .parent_data = gpu_xo_gpll0,
1273f7df5baSJeffrey Hugo .num_parents = ARRAY_SIZE(gpu_xo_gpll0),
128ce336a51SMarijn Suijten .ops = &clk_rcg2_ops,
1293f7df5baSJeffrey Hugo },
1303f7df5baSJeffrey Hugo };
1313f7df5baSJeffrey Hugo
1323f7df5baSJeffrey Hugo static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
1333f7df5baSJeffrey Hugo { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 },
1343f7df5baSJeffrey Hugo { }
1353f7df5baSJeffrey Hugo };
1363f7df5baSJeffrey Hugo
1373f7df5baSJeffrey Hugo static struct clk_rcg2 gfx3d_clk_src = {
1383f7df5baSJeffrey Hugo .cmd_rcgr = 0x1070,
1393f7df5baSJeffrey Hugo .hid_width = 5,
1403f7df5baSJeffrey Hugo .parent_map = gpu_xo_gpupll0_map,
1413f7df5baSJeffrey Hugo .freq_tbl = ftbl_gfx3d_clk_src,
1423f7df5baSJeffrey Hugo .clkr.hw.init = &(struct clk_init_data){
1433f7df5baSJeffrey Hugo .name = "gfx3d_clk_src",
1443f7df5baSJeffrey Hugo .parent_hws = gpu_xo_gpupll0,
145353b18dcSDmitry Baryshkov .num_parents = ARRAY_SIZE(gpu_xo_gpupll0),
146ce336a51SMarijn Suijten .ops = &clk_rcg2_ops,
1473f7df5baSJeffrey Hugo .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1483f7df5baSJeffrey Hugo },
1493f7df5baSJeffrey Hugo };
1503f7df5baSJeffrey Hugo
1513f7df5baSJeffrey Hugo static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
1523f7df5baSJeffrey Hugo F(19200000, P_XO, 1, 0, 0),
1533f7df5baSJeffrey Hugo { }
1543f7df5baSJeffrey Hugo };
1553f7df5baSJeffrey Hugo
1563f7df5baSJeffrey Hugo static struct clk_rcg2 rbbmtimer_clk_src = {
1573f7df5baSJeffrey Hugo .cmd_rcgr = 0x10b0,
1583f7df5baSJeffrey Hugo .hid_width = 5,
1593f7df5baSJeffrey Hugo .parent_map = gpu_xo_gpll0_map,
1603f7df5baSJeffrey Hugo .freq_tbl = ftbl_rbbmtimer_clk_src,
1613f7df5baSJeffrey Hugo .clkr.hw.init = &(struct clk_init_data){
1623f7df5baSJeffrey Hugo .name = "rbbmtimer_clk_src",
1633f7df5baSJeffrey Hugo .parent_data = gpu_xo_gpll0,
1643f7df5baSJeffrey Hugo .num_parents = ARRAY_SIZE(gpu_xo_gpll0),
165ce336a51SMarijn Suijten .ops = &clk_rcg2_ops,
1663f7df5baSJeffrey Hugo },
1673f7df5baSJeffrey Hugo };
1683f7df5baSJeffrey Hugo
1693f7df5baSJeffrey Hugo static const struct freq_tbl ftbl_gfx3d_isense_clk_src[] = {
1703f7df5baSJeffrey Hugo F(19200000, P_XO, 1, 0, 0),
1713f7df5baSJeffrey Hugo F(40000000, P_GPLL0, 15, 0, 0),
1723f7df5baSJeffrey Hugo F(200000000, P_GPLL0, 3, 0, 0),
1733f7df5baSJeffrey Hugo F(300000000, P_GPLL0, 2, 0, 0),
1743f7df5baSJeffrey Hugo { }
1753f7df5baSJeffrey Hugo };
1763f7df5baSJeffrey Hugo
1773f7df5baSJeffrey Hugo static struct clk_rcg2 gfx3d_isense_clk_src = {
1783f7df5baSJeffrey Hugo .cmd_rcgr = 0x1100,
1793f7df5baSJeffrey Hugo .hid_width = 5,
1803f7df5baSJeffrey Hugo .parent_map = gpu_xo_gpll0_map,
1813f7df5baSJeffrey Hugo .freq_tbl = ftbl_gfx3d_isense_clk_src,
1823f7df5baSJeffrey Hugo .clkr.hw.init = &(struct clk_init_data){
1833f7df5baSJeffrey Hugo .name = "gfx3d_isense_clk_src",
1843f7df5baSJeffrey Hugo .parent_data = gpu_xo_gpll0,
1853f7df5baSJeffrey Hugo .num_parents = ARRAY_SIZE(gpu_xo_gpll0),
186ce336a51SMarijn Suijten .ops = &clk_rcg2_ops,
1873f7df5baSJeffrey Hugo },
1883f7df5baSJeffrey Hugo };
1893f7df5baSJeffrey Hugo
1903f7df5baSJeffrey Hugo static struct clk_branch rbcpr_clk = {
1913f7df5baSJeffrey Hugo .halt_reg = 0x1054,
1923f7df5baSJeffrey Hugo .clkr = {
1933f7df5baSJeffrey Hugo .enable_reg = 0x1054,
1943f7df5baSJeffrey Hugo .enable_mask = BIT(0),
1953f7df5baSJeffrey Hugo .hw.init = &(struct clk_init_data){
1963f7df5baSJeffrey Hugo .name = "rbcpr_clk",
1973f7df5baSJeffrey Hugo .parent_hws = (const struct clk_hw *[]){ &rbcpr_clk_src.clkr.hw },
1983f7df5baSJeffrey Hugo .num_parents = 1,
1993f7df5baSJeffrey Hugo .ops = &clk_branch2_ops,
2003f7df5baSJeffrey Hugo .flags = CLK_SET_RATE_PARENT,
2013f7df5baSJeffrey Hugo },
2023f7df5baSJeffrey Hugo },
2033f7df5baSJeffrey Hugo };
2043f7df5baSJeffrey Hugo
2053f7df5baSJeffrey Hugo static struct clk_branch gfx3d_clk = {
2063f7df5baSJeffrey Hugo .halt_reg = 0x1098,
2073f7df5baSJeffrey Hugo .clkr = {
2083f7df5baSJeffrey Hugo .enable_reg = 0x1098,
2093f7df5baSJeffrey Hugo .enable_mask = BIT(0),
2103f7df5baSJeffrey Hugo .hw.init = &(struct clk_init_data){
2113f7df5baSJeffrey Hugo .name = "gfx3d_clk",
2123f7df5baSJeffrey Hugo .parent_hws = (const struct clk_hw *[]){ &gfx3d_clk_src.clkr.hw },
2133f7df5baSJeffrey Hugo .num_parents = 1,
2143f7df5baSJeffrey Hugo .ops = &clk_branch2_ops,
2153f7df5baSJeffrey Hugo .flags = CLK_SET_RATE_PARENT,
2163f7df5baSJeffrey Hugo },
2173f7df5baSJeffrey Hugo },
2183f7df5baSJeffrey Hugo };
2193f7df5baSJeffrey Hugo
2203f7df5baSJeffrey Hugo static struct clk_branch rbbmtimer_clk = {
2213f7df5baSJeffrey Hugo .halt_reg = 0x10d0,
2223f7df5baSJeffrey Hugo .clkr = {
2233f7df5baSJeffrey Hugo .enable_reg = 0x10d0,
2243f7df5baSJeffrey Hugo .enable_mask = BIT(0),
2253f7df5baSJeffrey Hugo .hw.init = &(struct clk_init_data){
2263f7df5baSJeffrey Hugo .name = "rbbmtimer_clk",
2273f7df5baSJeffrey Hugo .parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw },
2283f7df5baSJeffrey Hugo .num_parents = 1,
2293f7df5baSJeffrey Hugo .ops = &clk_branch2_ops,
2303f7df5baSJeffrey Hugo .flags = CLK_SET_RATE_PARENT,
2313f7df5baSJeffrey Hugo },
2323f7df5baSJeffrey Hugo },
2333f7df5baSJeffrey Hugo };
2343f7df5baSJeffrey Hugo
2353f7df5baSJeffrey Hugo static struct clk_branch gfx3d_isense_clk = {
2363f7df5baSJeffrey Hugo .halt_reg = 0x1124,
2373f7df5baSJeffrey Hugo .clkr = {
2383f7df5baSJeffrey Hugo .enable_reg = 0x1124,
2393f7df5baSJeffrey Hugo .enable_mask = BIT(0),
2403f7df5baSJeffrey Hugo .hw.init = &(struct clk_init_data){
2413f7df5baSJeffrey Hugo .name = "gfx3d_isense_clk",
2423f7df5baSJeffrey Hugo .parent_hws = (const struct clk_hw *[]){ &gfx3d_isense_clk_src.clkr.hw },
2433f7df5baSJeffrey Hugo .num_parents = 1,
2443f7df5baSJeffrey Hugo .ops = &clk_branch2_ops,
2453f7df5baSJeffrey Hugo },
2463f7df5baSJeffrey Hugo },
2473f7df5baSJeffrey Hugo };
2483f7df5baSJeffrey Hugo
2493f7df5baSJeffrey Hugo static struct gdsc gpu_cx_gdsc = {
2503f7df5baSJeffrey Hugo .gdscr = 0x1004,
2513f7df5baSJeffrey Hugo .gds_hw_ctrl = 0x1008,
252781d8ceaSJeffrey Hugo .pd = {
2533f7df5baSJeffrey Hugo .name = "gpu_cx",
2543f7df5baSJeffrey Hugo },
2553f7df5baSJeffrey Hugo .pwrsts = PWRSTS_OFF_ON,
2563f7df5baSJeffrey Hugo .flags = VOTABLE,
257781d8ceaSJeffrey Hugo };
2583f7df5baSJeffrey Hugo
2593f7df5baSJeffrey Hugo static struct gdsc gpu_gx_gdsc = {
2603f7df5baSJeffrey Hugo .gdscr = 0x1094,
2613f7df5baSJeffrey Hugo .clamp_io_ctrl = 0x130,
2623f7df5baSJeffrey Hugo .resets = (unsigned int []){ GPU_GX_BCR },
263a59c16c8SAngeloGioacchino Del Regno .reset_count = 1,
264a59c16c8SAngeloGioacchino Del Regno .cxcs = (unsigned int []){ 0x1098 },
265a59c16c8SAngeloGioacchino Del Regno .cxc_count = 1,
266a59c16c8SAngeloGioacchino Del Regno .pd = {
2673f7df5baSJeffrey Hugo .name = "gpu_gx",
2683f7df5baSJeffrey Hugo },
2693f7df5baSJeffrey Hugo .parent = &gpu_cx_gdsc.pd,
2703f7df5baSJeffrey Hugo .pwrsts = PWRSTS_OFF_ON | PWRSTS_RET,
271a59c16c8SAngeloGioacchino Del Regno .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
272a59c16c8SAngeloGioacchino Del Regno };
2733f7df5baSJeffrey Hugo
2743f7df5baSJeffrey Hugo static struct clk_regmap *gpucc_msm8998_clocks[] = {
2753f7df5baSJeffrey Hugo [GPUPLL0] = &gpupll0.clkr,
2763f7df5baSJeffrey Hugo [GPUPLL0_OUT_EVEN] = &gpupll0_out_even.clkr,
2773f7df5baSJeffrey Hugo [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
2783f7df5baSJeffrey Hugo [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2793f7df5baSJeffrey Hugo [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
2803f7df5baSJeffrey Hugo [GFX3D_ISENSE_CLK_SRC] = &gfx3d_isense_clk_src.clkr,
2813f7df5baSJeffrey Hugo [RBCPR_CLK] = &rbcpr_clk.clkr,
2823f7df5baSJeffrey Hugo [GFX3D_CLK] = &gfx3d_clk.clkr,
2833f7df5baSJeffrey Hugo [RBBMTIMER_CLK] = &rbbmtimer_clk.clkr,
2843f7df5baSJeffrey Hugo [GFX3D_ISENSE_CLK] = &gfx3d_isense_clk.clkr,
2853f7df5baSJeffrey Hugo [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr,
2863f7df5baSJeffrey Hugo };
2873f7df5baSJeffrey Hugo
2883f7df5baSJeffrey Hugo static struct gdsc *gpucc_msm8998_gdscs[] = {
2893f7df5baSJeffrey Hugo [GPU_CX_GDSC] = &gpu_cx_gdsc,
2903f7df5baSJeffrey Hugo [GPU_GX_GDSC] = &gpu_gx_gdsc,
2913f7df5baSJeffrey Hugo };
2923f7df5baSJeffrey Hugo
2933f7df5baSJeffrey Hugo static const struct qcom_reset_map gpucc_msm8998_resets[] = {
2943f7df5baSJeffrey Hugo [GPU_CX_BCR] = { 0x1000 },
2953f7df5baSJeffrey Hugo [RBCPR_BCR] = { 0x1050 },
2963f7df5baSJeffrey Hugo [GPU_GX_BCR] = { 0x1090 },
2973f7df5baSJeffrey Hugo [GPU_ISENSE_BCR] = { 0x1120 },
2983f7df5baSJeffrey Hugo };
2993f7df5baSJeffrey Hugo
3003f7df5baSJeffrey Hugo static const struct regmap_config gpucc_msm8998_regmap_config = {
3013f7df5baSJeffrey Hugo .reg_bits = 32,
3023f7df5baSJeffrey Hugo .reg_stride = 4,
3033f7df5baSJeffrey Hugo .val_bits = 32,
3043f7df5baSJeffrey Hugo .max_register = 0x9000,
3053f7df5baSJeffrey Hugo .fast_io = true,
3063f7df5baSJeffrey Hugo };
3073f7df5baSJeffrey Hugo
3083f7df5baSJeffrey Hugo static const struct qcom_cc_desc gpucc_msm8998_desc = {
3093f7df5baSJeffrey Hugo .config = &gpucc_msm8998_regmap_config,
3103f7df5baSJeffrey Hugo .clks = gpucc_msm8998_clocks,
3113f7df5baSJeffrey Hugo .num_clks = ARRAY_SIZE(gpucc_msm8998_clocks),
3123f7df5baSJeffrey Hugo .resets = gpucc_msm8998_resets,
3133f7df5baSJeffrey Hugo .num_resets = ARRAY_SIZE(gpucc_msm8998_resets),
3143f7df5baSJeffrey Hugo .gdscs = gpucc_msm8998_gdscs,
3153f7df5baSJeffrey Hugo .num_gdscs = ARRAY_SIZE(gpucc_msm8998_gdscs),
3163f7df5baSJeffrey Hugo };
3173f7df5baSJeffrey Hugo
3183f7df5baSJeffrey Hugo static const struct of_device_id gpucc_msm8998_match_table[] = {
3193f7df5baSJeffrey Hugo { .compatible = "qcom,msm8998-gpucc" },
3203f7df5baSJeffrey Hugo { }
3213f7df5baSJeffrey Hugo };
3223f7df5baSJeffrey Hugo MODULE_DEVICE_TABLE(of, gpucc_msm8998_match_table);
3233f7df5baSJeffrey Hugo
gpucc_msm8998_probe(struct platform_device * pdev)3243f7df5baSJeffrey Hugo static int gpucc_msm8998_probe(struct platform_device *pdev)
3253f7df5baSJeffrey Hugo {
3263f7df5baSJeffrey Hugo struct regmap *regmap;
3273f7df5baSJeffrey Hugo
3283f7df5baSJeffrey Hugo regmap = qcom_cc_map(pdev, &gpucc_msm8998_desc);
3293f7df5baSJeffrey Hugo if (IS_ERR(regmap))
3303f7df5baSJeffrey Hugo return PTR_ERR(regmap);
3313f7df5baSJeffrey Hugo
3323f7df5baSJeffrey Hugo /* force periph logic on to avoid perf counter corruption */
3333f7df5baSJeffrey Hugo regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(13), BIT(13));
3343f7df5baSJeffrey Hugo /* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */
3353f7df5baSJeffrey Hugo regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0));
3363f7df5baSJeffrey Hugo
3373f7df5baSJeffrey Hugo return qcom_cc_really_probe(pdev, &gpucc_msm8998_desc, regmap);
3383f7df5baSJeffrey Hugo }
3393f7df5baSJeffrey Hugo
3403f7df5baSJeffrey Hugo static struct platform_driver gpucc_msm8998_driver = {
3413f7df5baSJeffrey Hugo .probe = gpucc_msm8998_probe,
3423f7df5baSJeffrey Hugo .driver = {
3433f7df5baSJeffrey Hugo .name = "gpucc-msm8998",
3443f7df5baSJeffrey Hugo .of_match_table = gpucc_msm8998_match_table,
3453f7df5baSJeffrey Hugo },
3463f7df5baSJeffrey Hugo };
3473f7df5baSJeffrey Hugo module_platform_driver(gpucc_msm8998_driver);
3483f7df5baSJeffrey Hugo
3493f7df5baSJeffrey Hugo MODULE_DESCRIPTION("QCOM GPUCC MSM8998 Driver");
3503f7df5baSJeffrey Hugo MODULE_LICENSE("GPL v2");
3513f7df5baSJeffrey Hugo